- Email: [email protected]
Engineering ReRAM for high-density applications
MEE 9867
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Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee 4 5 3
Engineering ReRAM for high-density applications
6
Alessandro Calderoni ⇑, Scott Sills, Chris Cardon, Emiliano Faraoni, Nirmal Ramaswamy
7
Micron Technology Inc., Boise, ID, USA
9 8 10 1 7 2 2 13 14 15 16 17 18 19 20 21 22 23 24 25 26
a r t i c l e
i n f o
Article history: Received 23 February 2015 Received in revised form 6 April 2015 Accepted 7 April 2015 Available online xxxx Keywords: Resistive memory Endurance Noise Variability Retention MLC Cross-point
a b s t r a c t Resistive random access memory (ReRAM) devices are emerging candidates for the next generation of nonvolatile high-density memory (Sills et al., 2014). The value proposition for this technology is bit alterability, high speed operation, long retention and high endurance. In addition, low-power and low-current operation is highly desirable for high-density memory systems targeting the growing mobile market. This paper presents various challenges in engineering a ReRAM cell suitable for high-density applications such as material selection, programming algorithms, noise issues and scaling path. Ó 2015 Published by Elsevier B.V.
28 29 30 31 32 33 34 35
36 37 38
1. Material selection: O-ReRAM or M-ReRAM?
39
The spectrum of materials showing non-volatile resistance switching is wide and includes several metal oxides as well as chalcogenide-based systems [2,3]. Filamentary switching between a high-resistance state (HRS) and a low-resistance state (LRS) is obtained by oxygen or metal ion movement (O-ReRAM and M-ReRAM, respectively). The reference O-ReRAM stack presented here comprises: a TiN bottom electrode (BE), an amorphous ALD HfSiOx dielectric layer and a reactive Ti top electrode; whereas the M-ReRAM stack is made by a TiN BE, an electrolyte layer and a copper ion reservoir. The BE size is 30 nm. Stable median endurance characteristics are possible for both systems up to 1E6 cycles with read window (LRS to HRS ratio) >50 and >1000 for O-ReRAM and M-ReRAM, respectively (Fig. 1). High-density applications require high read window for a large number of bits, which means that a fair assessment of different ReRAM systems can only be done by comparing variability and full distributions [4]. Read, program and cell-to-cell variability have to be carefully evaluated on the same test vehicle to compare the performance of different systems. Fig. 2a shows read distributions for the two reference systems: although the median window is wide for both systems, variability makes the read margin (difference between LRS and HRS currents
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
⇑ Corresponding author. E-mail address: [email protected] (A. Calderoni).
at 3r) much worse for O-ReRAM compared to M-ReRAM. The choice of a system with a large median window between LRS and HRS, as well as a low variability, is thus indispensable for reliable operations through cycling (Fig. 2b). For this reason, M-ReRAM has been selected over O-ReRAM as a reference material for high-density applications.
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2. Low current operation
67
High-density memory would require low current operation because maintaining high drive capability in scaled access devices is a significant challenge. To realize the advantages of low voltage operation, programming currents need to be low (since parasitic drops across routing and drivers will be high if the programming current is high). It’s thus necessary to engineer a cell capable of operating well below 50 lA. Fig. 3 shows M-ReRAM I–Vs for a wide range of current compliance, from 50 lA down to 1 lA. The cell functions well down to currents as low as 1 lA with a large median read window (>1E4). Nevertheless this intrinsic capability is not enough to ensure reliable operation at low current. This is due to the fact that all the variability components such as read and program noise, increase at low current compliance (ICC) [4]. As ICC is decreased, the number of metal cations comprising the filament significantly reduces, leading to increased variability. Fig. 4 shows that the read margin narrows at very low compliances (<30 lA), although the median read window is >1E4. The lower number of atoms in the conductive filament at low ICC
68
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Please cite this article in press as: A. Calderoni et al., Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2015.04.044
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Fig. 1. O-ReRAM vs. M-ReRAM comparison: (a) LRS and HRS I–Vs; (b) median LRS and HRS read current vs. cycling. Both systems show good median window.
Fig. 2. O-ReRAM vs. M-ReRAM comparison: (a) LRS and HRS distributions; (b)
3r LRS and HRS read current vs. cycling. M-ReRAM shows positive read window down to
Fig. 3. M-ReRAM I–Vs show large (>1E4) median window with current compliances from 50 lA down to 1 lA.
Fig. 4. LRS and HRS distributions after 1 k cycles at different ICC.
Please cite this article in press as: A. Calderoni et al., Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2015.04.044
3r.
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Fig. 5. LRS read current as a function of time (at room temperature): unlike the upper tail of the distribution (+2r), the lower tail ( 2r) shows instability at low ICC.
Fig. 6. Post-bake BER is reduced as a function of ICC. Bake = 1 h, 150 °C equivalent to 10 y at 55 °C, EA = 1.5 eV.
Fig. 7. BER as a function of cycling: material and algorithm improvements.
87 88 89 90 91
(<25 lA) makes it weaker and the tail of the distribution more unstable over time. Fig. 5 shows the upper (+2r) and lower ( 2r) tails of LRS read currents as a function of time, for different current compliances. Tail bits placed with lower ICC move towards the HRS quicker than
Fig. 8. Overlay of read currents from a single pulse program and two pulses program/verify algorithm read at different times.
when they are set with higher ICC. This leads to retention Bit Error Rate (BER) being a strong function of ICC: higher ICC yields lower retention BER as shown in Fig. 6. Material optimizations led to improved read margin (2 lA at 3r), high endurance (1E6) and long retention (BER < 1E-4 after 1 h bake at 150 °C) at low current operation (40 lA). Further reduction in operating current (10 lA and below) will result in significantly increased noise and variability which will also result in reduced read margin and worse retention [4].
92
3. Programming algorithms
101
Many memory technologies rely on programming algorithms (such as a program/verify sequence in NAND) to better control the bit distributions and/or extend endurance. Program algorithms can be used to enhance intrinsic ReRAM characteristics as well. For example it has been shown [1] that a balancing between set and reset pulses in terms of bias and current compliance is key for high endurance. At high cycle counts (>100 k) the material can periodically fail to switch in either set or reset states if the ionic flux is not properly balanced through cycling [1]. A suitable programming algorithm was used to overcome this phenomenon and stabilize the endurance behavior. As a result, along with material optimizations, BER through cycling can be maintained below 1E-5 at ICC 40 lA, as shown in Fig. 7.
102
Please cite this article in press as: A. Calderoni et al., Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2015.04.044
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Fig. 9. LRS read distribution for: 1E3 bits (A), 1 bit programmed 1E3 times (B) and 1 bit read 1E3 times (C).
Fig. 10. LRS resistance as a function of ICC for O-ReRAM and M-ReRAM.
In the same way, programming algorithms might be used to increase the available read window by tightening LRS and HRS distributions. These techniques, however, have to deal with intrinsic noise components in the case of ReRAM cells. A sequence of program/verify scheme can be used to effectively tighten the initial distribution as shown in Fig. 8. Consecutive reads over time show a relaxation of the initial placement back to a wider distribution that is similar to the distribution obtained with a single pulse (Fig. 8). Hence, a better placement can be obtained only by increasing the current compliance. Fig. 9 helps to understand the root cause of this observation. The set distribution of 1E3 bits (A) is shown along with the distribution of one bit programmed 1E3 times (B) and one bit read 1E3 times (C). Distribution C and B measure read and program noise, respectively (to obtain distribution B, 10 reads where used after each program to average out read noise and obtain only program noise). Distribution A measures the combination of read, program, and cell-to-cell noise. It is clear from these distributions what is happening to the program/verify sequence in Fig. 8: placing a bit to a specific current value outside its normal tendency is not deterministic due to high program noise and even if this is done, eventually will result in smearing of the distribution due to read noise. Although programming algorithms can be effectively used to improve cell endurance, they cannot be reliably used at low ICC to tighten LRS and HRS distributions owing to ReRAM intrinsic program and read noise.
115
4. MLC
142
Another possible path to achieve high-density is MLC. The resistance of the set state is a continuum function of the current compliance for both O-ReRAM and M-ReRAM (Fig. 10), so MLC is a possibility. Although many literature reports [5,6] showed ReRAM cells placed at different read levels, several issues need to be addressed to declare MLC a viable option. Fig. 11a shows the read current distribution of four different levels (i.e. 2 bits), namely H0/L1/L2/L3, corresponding to HRS and three different LRS states obtained with increasing ICC (from 10 lA to 100 lA). Unless high current compliance is used, larger variability and
143
Fig. 11. (a) Current distributions from 4 different states: HRS and 3 LRS obtained with ICC from 10 lA to 100 lA; (b) L1 distributions after 1E3 cycles between H0 and L3.
Please cite this article in press as: A. Calderoni et al., Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2015.04.044
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Fig. 12. Comparable HRS and LRS distributions after 1 k cycles between intrinsic and fully integrated cell at 27 nm (16 Gb chip).
Fig. 13. Set and reset I–Vs of a cross-point stack with selector plus cell.
5
poor retention of the lowest LRS state (L1) are expected, as showed in Fig. 11a. Proper balance between set and reset operations is also needed to maximize endurance [1] and with MLC a given cell can be cycled with different set pulses (i.e. different states) through its life time. Balancing of the different pulses became challenging and the optimization of the program sequence is required [1,7]. Fig. 11b shows the effect of unbalanced set/reset pulses: a distribution of bits cycled 1E3 time between H0 and L3 and then placed at L1. The final distribution is very different from the reference one, cycled 1E3 times between H0 and L1. Although MLC is theoretically possible with ReRAM cell, several issues have to be overcome to properly work, especially at low current compliance.
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5. Memory array
167
5.1. 3-Terminal selectors: 1T1R
168
With the exclusion of self-rectifying devices [8], ReRAM cells typically require an access device. DRAM-like access devices have been successfully integrated at 27 nm node to enable high performance, high-density, 16 Gb M-ReRAM chip [9]. High density integration results in the use of access devices with limited drive capability due to scaling issues like contact resistance and pitch scaling [9,10]. Fig. 12 shows that comparable HRS and LRS distributions are obtained between intrinsic and fully integrated cells at 27 nm (16 Gb chip).
169
5.2. 2-Terminal selectors: cross-point
179
1T1R solutions usually limit the minimum footprint to 6F2 and a two-terminal selector is needed to stack the memory in a 4F2 crosspoint architecture. For bipolar ReRAM such the ones presented here, a bipolar selector is also required. Fig. 13 shows the I–V of a stacked bipolar selector with M-ReRAM cell. Selector leakage, threshold voltage distributions, and variability (along with cell characteristics) define the array size.
180
Fig. 14. Threshold voltage distributions for stacked M-ReRAM cells with two different selectors: (a) reference, (b) optimized to enable low-voltage operations.
Please cite this article in press as: A. Calderoni et al., Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2015.04.044
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Fig. 14 shows the threshold distributions for stacked M-ReRAM and selector with two different selectors, A and B. As the distributions indicate, depending on selector variability, the total required voltage can be significantly decreased. Using selectors with optimized leakage and variability, cross-point ReRAM appears to be feasible.
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6. Conclusions
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Several challenges in engineering a ReRAM technology for high-density applications have been presented. M-ReRAM cells have been chosen over O-ReRAM due to the high median window and low variability, both key factors in enabling a viable technology. Material and programming algorithm optimizations enable high endurance (>1E6 cycles with BER < 1E-5) and retention (10 y, 55 °C with BER < 1E-4) at 40 lA operating current. LRS and HRS distributions between intrinsic and fully integrated cell on a 16 Gb chip at 27 nm have been demonstrated to be similar. The negative impact of very low ICC on distributions, noise and retention characteristics, represents the main challenge to enable sub-10 lA reliable operations and MLC capability. Cross-point architectures could enable high-density and require a 2-terminal bipolar selector with low leakage and low variability.
Acknowledgments
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The authors gratefully acknowledge Micron’s Emerging Memory Team and Hiroyuki Fujita and Aratani Katsuhisa from SONY for the collaboration on M-ReRAM.
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References
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[1] S. Sills, S. Yasuda, J. Strand, A. Calderoni, K. Aratani, A. Johnson, N. Ramaswamy, A Copper ReRAM Cell for Storage Class Memory Applications, VLSI, 2014. [2] Y. Hirose, H. Hirose, JAP 47 (6) (1976). [3] K. Aratani, K. Ohba, T. Mizuguchi, S. Yasuda, T. Shiimoto, T. Tsushima, T. Sone, K. Endo, A. Kouchiyama, S. Sasaki, A. Maesaka, N. Yamada, H. Narisawa, Tech. Dig. IEEE Int. Elec. Dev. Meeting (2013). [4] A. Calderoni, S. Sills, N. Ramaswamy, Performance Comparison of O-based and Cu-based ReRAM for High-Density Applications, IMW, 2014. [5] W.C. Chien, K.P. Chang, Y.C. Chen, E.K. Lai, H. Mahne, Y.D. Yao, P. Lin, J. Gong, S.H. Hsieh, K.Y. Hsieh, R. Liu, C.-Y. Lu, Proc. Int. Conf. Solid State Devices Mater. (2008) 1170–1171. [6] A. Prakash, J. Park, J. Song, J. Woo, E.-J. Cha, H. Hwang, Demonstration of Low Power 3-bit Multilevel Cell Characteristics in a TaOx-Based RRAM by Stack Engineering, EDL, 2015. [7] S.-S. Sheu et al., A 4 Mb Embedded SLC Resistive-RAM Macro with 7.2 ns ReadWrite Random-Access Time and 160 ns MLC-Access Capability, ISSCC, 2011. [8] X.A. Tran et al., Self-Rectifying and Forming-Free Unipolar HfOx based-High Performance RRAM Built by Fab-Available Materials, IEDM, 2011. [9] J. Zahurak et al., Tech. Dig. IEEE Int. Electron Dev. Meeting (2014). [10] S. Sills, S. Yasuda, A. Calderoni, C. Cardon, J. Strand, K. Aratani. N. Ramaswamy, Challenges for High-Density ReRAM, VLSI, 2015 (to be published).
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Please cite this article in press as: A. Calderoni et al., Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2015.04.044
No. of Pages 6, Model 5G
13 April 2015 Microelectronic Engineering xxx (2015) xxx–xxx 1
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee 4 5 3
Engineering ReRAM for high-density applications
6
Alessandro Calderoni ⇑, Scott Sills, Chris Cardon, Emiliano Faraoni, Nirmal Ramaswamy
7
Micron Technology Inc., Boise, ID, USA
9 8 10 1 7 2 2 13 14 15 16 17 18 19 20 21 22 23 24 25 26
a r t i c l e
i n f o
Article history: Received 23 February 2015 Received in revised form 6 April 2015 Accepted 7 April 2015 Available online xxxx Keywords: Resistive memory Endurance Noise Variability Retention MLC Cross-point
a b s t r a c t Resistive random access memory (ReRAM) devices are emerging candidates for the next generation of nonvolatile high-density memory (Sills et al., 2014). The value proposition for this technology is bit alterability, high speed operation, long retention and high endurance. In addition, low-power and low-current operation is highly desirable for high-density memory systems targeting the growing mobile market. This paper presents various challenges in engineering a ReRAM cell suitable for high-density applications such as material selection, programming algorithms, noise issues and scaling path. Ó 2015 Published by Elsevier B.V.
28 29 30 31 32 33 34 35
36 37 38
1. Material selection: O-ReRAM or M-ReRAM?
39
The spectrum of materials showing non-volatile resistance switching is wide and includes several metal oxides as well as chalcogenide-based systems [2,3]. Filamentary switching between a high-resistance state (HRS) and a low-resistance state (LRS) is obtained by oxygen or metal ion movement (O-ReRAM and M-ReRAM, respectively). The reference O-ReRAM stack presented here comprises: a TiN bottom electrode (BE), an amorphous ALD HfSiOx dielectric layer and a reactive Ti top electrode; whereas the M-ReRAM stack is made by a TiN BE, an electrolyte layer and a copper ion reservoir. The BE size is 30 nm. Stable median endurance characteristics are possible for both systems up to 1E6 cycles with read window (LRS to HRS ratio) >50 and >1000 for O-ReRAM and M-ReRAM, respectively (Fig. 1). High-density applications require high read window for a large number of bits, which means that a fair assessment of different ReRAM systems can only be done by comparing variability and full distributions [4]. Read, program and cell-to-cell variability have to be carefully evaluated on the same test vehicle to compare the performance of different systems. Fig. 2a shows read distributions for the two reference systems: although the median window is wide for both systems, variability makes the read margin (difference between LRS and HRS currents
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
⇑ Corresponding author. E-mail address: [email protected] (A. Calderoni).
at 3r) much worse for O-ReRAM compared to M-ReRAM. The choice of a system with a large median window between LRS and HRS, as well as a low variability, is thus indispensable for reliable operations through cycling (Fig. 2b). For this reason, M-ReRAM has been selected over O-ReRAM as a reference material for high-density applications.
61
2. Low current operation
67
High-density memory would require low current operation because maintaining high drive capability in scaled access devices is a significant challenge. To realize the advantages of low voltage operation, programming currents need to be low (since parasitic drops across routing and drivers will be high if the programming current is high). It’s thus necessary to engineer a cell capable of operating well below 50 lA. Fig. 3 shows M-ReRAM I–Vs for a wide range of current compliance, from 50 lA down to 1 lA. The cell functions well down to currents as low as 1 lA with a large median read window (>1E4). Nevertheless this intrinsic capability is not enough to ensure reliable operation at low current. This is due to the fact that all the variability components such as read and program noise, increase at low current compliance (ICC) [4]. As ICC is decreased, the number of metal cations comprising the filament significantly reduces, leading to increased variability. Fig. 4 shows that the read margin narrows at very low compliances (<30 lA), although the median read window is >1E4. The lower number of atoms in the conductive filament at low ICC
68
http://dx.doi.org/10.1016/j.mee.2015.04.044 0167-9317/Ó 2015 Published by Elsevier B.V.
Please cite this article in press as: A. Calderoni et al., Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2015.04.044
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Fig. 1. O-ReRAM vs. M-ReRAM comparison: (a) LRS and HRS I–Vs; (b) median LRS and HRS read current vs. cycling. Both systems show good median window.
Fig. 2. O-ReRAM vs. M-ReRAM comparison: (a) LRS and HRS distributions; (b)
3r LRS and HRS read current vs. cycling. M-ReRAM shows positive read window down to
Fig. 3. M-ReRAM I–Vs show large (>1E4) median window with current compliances from 50 lA down to 1 lA.
Fig. 4. LRS and HRS distributions after 1 k cycles at different ICC.
Please cite this article in press as: A. Calderoni et al., Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2015.04.044
3r.
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Fig. 5. LRS read current as a function of time (at room temperature): unlike the upper tail of the distribution (+2r), the lower tail ( 2r) shows instability at low ICC.
Fig. 6. Post-bake BER is reduced as a function of ICC. Bake = 1 h, 150 °C equivalent to 10 y at 55 °C, EA = 1.5 eV.
Fig. 7. BER as a function of cycling: material and algorithm improvements.
87 88 89 90 91
(<25 lA) makes it weaker and the tail of the distribution more unstable over time. Fig. 5 shows the upper (+2r) and lower ( 2r) tails of LRS read currents as a function of time, for different current compliances. Tail bits placed with lower ICC move towards the HRS quicker than
Fig. 8. Overlay of read currents from a single pulse program and two pulses program/verify algorithm read at different times.
when they are set with higher ICC. This leads to retention Bit Error Rate (BER) being a strong function of ICC: higher ICC yields lower retention BER as shown in Fig. 6. Material optimizations led to improved read margin (2 lA at 3r), high endurance (1E6) and long retention (BER < 1E-4 after 1 h bake at 150 °C) at low current operation (40 lA). Further reduction in operating current (10 lA and below) will result in significantly increased noise and variability which will also result in reduced read margin and worse retention [4].
92
3. Programming algorithms
101
Many memory technologies rely on programming algorithms (such as a program/verify sequence in NAND) to better control the bit distributions and/or extend endurance. Program algorithms can be used to enhance intrinsic ReRAM characteristics as well. For example it has been shown [1] that a balancing between set and reset pulses in terms of bias and current compliance is key for high endurance. At high cycle counts (>100 k) the material can periodically fail to switch in either set or reset states if the ionic flux is not properly balanced through cycling [1]. A suitable programming algorithm was used to overcome this phenomenon and stabilize the endurance behavior. As a result, along with material optimizations, BER through cycling can be maintained below 1E-5 at ICC 40 lA, as shown in Fig. 7.
102
Please cite this article in press as: A. Calderoni et al., Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2015.04.044
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Fig. 9. LRS read distribution for: 1E3 bits (A), 1 bit programmed 1E3 times (B) and 1 bit read 1E3 times (C).
Fig. 10. LRS resistance as a function of ICC for O-ReRAM and M-ReRAM.
In the same way, programming algorithms might be used to increase the available read window by tightening LRS and HRS distributions. These techniques, however, have to deal with intrinsic noise components in the case of ReRAM cells. A sequence of program/verify scheme can be used to effectively tighten the initial distribution as shown in Fig. 8. Consecutive reads over time show a relaxation of the initial placement back to a wider distribution that is similar to the distribution obtained with a single pulse (Fig. 8). Hence, a better placement can be obtained only by increasing the current compliance. Fig. 9 helps to understand the root cause of this observation. The set distribution of 1E3 bits (A) is shown along with the distribution of one bit programmed 1E3 times (B) and one bit read 1E3 times (C). Distribution C and B measure read and program noise, respectively (to obtain distribution B, 10 reads where used after each program to average out read noise and obtain only program noise). Distribution A measures the combination of read, program, and cell-to-cell noise. It is clear from these distributions what is happening to the program/verify sequence in Fig. 8: placing a bit to a specific current value outside its normal tendency is not deterministic due to high program noise and even if this is done, eventually will result in smearing of the distribution due to read noise. Although programming algorithms can be effectively used to improve cell endurance, they cannot be reliably used at low ICC to tighten LRS and HRS distributions owing to ReRAM intrinsic program and read noise.
115
4. MLC
142
Another possible path to achieve high-density is MLC. The resistance of the set state is a continuum function of the current compliance for both O-ReRAM and M-ReRAM (Fig. 10), so MLC is a possibility. Although many literature reports [5,6] showed ReRAM cells placed at different read levels, several issues need to be addressed to declare MLC a viable option. Fig. 11a shows the read current distribution of four different levels (i.e. 2 bits), namely H0/L1/L2/L3, corresponding to HRS and three different LRS states obtained with increasing ICC (from 10 lA to 100 lA). Unless high current compliance is used, larger variability and
143
Fig. 11. (a) Current distributions from 4 different states: HRS and 3 LRS obtained with ICC from 10 lA to 100 lA; (b) L1 distributions after 1E3 cycles between H0 and L3.
Please cite this article in press as: A. Calderoni et al., Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2015.04.044
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Fig. 12. Comparable HRS and LRS distributions after 1 k cycles between intrinsic and fully integrated cell at 27 nm (16 Gb chip).
Fig. 13. Set and reset I–Vs of a cross-point stack with selector plus cell.
5
poor retention of the lowest LRS state (L1) are expected, as showed in Fig. 11a. Proper balance between set and reset operations is also needed to maximize endurance [1] and with MLC a given cell can be cycled with different set pulses (i.e. different states) through its life time. Balancing of the different pulses became challenging and the optimization of the program sequence is required [1,7]. Fig. 11b shows the effect of unbalanced set/reset pulses: a distribution of bits cycled 1E3 time between H0 and L3 and then placed at L1. The final distribution is very different from the reference one, cycled 1E3 times between H0 and L1. Although MLC is theoretically possible with ReRAM cell, several issues have to be overcome to properly work, especially at low current compliance.
153
5. Memory array
167
5.1. 3-Terminal selectors: 1T1R
168
With the exclusion of self-rectifying devices [8], ReRAM cells typically require an access device. DRAM-like access devices have been successfully integrated at 27 nm node to enable high performance, high-density, 16 Gb M-ReRAM chip [9]. High density integration results in the use of access devices with limited drive capability due to scaling issues like contact resistance and pitch scaling [9,10]. Fig. 12 shows that comparable HRS and LRS distributions are obtained between intrinsic and fully integrated cells at 27 nm (16 Gb chip).
169
5.2. 2-Terminal selectors: cross-point
179
1T1R solutions usually limit the minimum footprint to 6F2 and a two-terminal selector is needed to stack the memory in a 4F2 crosspoint architecture. For bipolar ReRAM such the ones presented here, a bipolar selector is also required. Fig. 13 shows the I–V of a stacked bipolar selector with M-ReRAM cell. Selector leakage, threshold voltage distributions, and variability (along with cell characteristics) define the array size.
180
Fig. 14. Threshold voltage distributions for stacked M-ReRAM cells with two different selectors: (a) reference, (b) optimized to enable low-voltage operations.
Please cite this article in press as: A. Calderoni et al., Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2015.04.044
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Fig. 14 shows the threshold distributions for stacked M-ReRAM and selector with two different selectors, A and B. As the distributions indicate, depending on selector variability, the total required voltage can be significantly decreased. Using selectors with optimized leakage and variability, cross-point ReRAM appears to be feasible.
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6. Conclusions
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Several challenges in engineering a ReRAM technology for high-density applications have been presented. M-ReRAM cells have been chosen over O-ReRAM due to the high median window and low variability, both key factors in enabling a viable technology. Material and programming algorithm optimizations enable high endurance (>1E6 cycles with BER < 1E-5) and retention (10 y, 55 °C with BER < 1E-4) at 40 lA operating current. LRS and HRS distributions between intrinsic and fully integrated cell on a 16 Gb chip at 27 nm have been demonstrated to be similar. The negative impact of very low ICC on distributions, noise and retention characteristics, represents the main challenge to enable sub-10 lA reliable operations and MLC capability. Cross-point architectures could enable high-density and require a 2-terminal bipolar selector with low leakage and low variability.
Acknowledgments
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The authors gratefully acknowledge Micron’s Emerging Memory Team and Hiroyuki Fujita and Aratani Katsuhisa from SONY for the collaboration on M-ReRAM.
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Please cite this article in press as: A. Calderoni et al., Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2015.04.044