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Enhancement of the saturation mobility in a ferroelectric-gated field-effect transistor by the surface planarization of ferroelectric film
Thin Solid Films 591 (2015) 1–7
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Thin Solid Films journal homepage: www.elsevier.com/locate/tsf
Enhancement of the saturation mobility in a ferroelectric-gated field-effect transistor by the surface planarization of ferroelectric film Woo Young Kim a, Gwang-Jae Jeon b, In-Ku Kang b, Hyun Bin Shim b, Hee Chul Lee b a b
Department of Mechanical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 373-1, Guseong-dong, Yuseong-gu, Daejeon 305-701, Republic of Korea Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 373-1, Guseong-dong, Yuseong-gu, Daejeon 305-701, Republic of Korea
a r t i c l e
i n f o
Article history: Received 29 August 2014 Received in revised form 10 August 2015 Accepted 12 August 2015 Available online 13 August 2015 Keywords: Ferroelectric polymer Solubility control Saturation mobility Poole–Frenkel conduction
a b s t r a c t Ferroelectricity refers to the property of a dielectric material to undergo spontaneous polarization which originates from the crystalline phase. Hence, ferroelectric materials have a certain degree of surface roughness when they are formed as a thin film. A high degree of surface roughness may cause unintended phenomena when the ferroelectric material is used in electronic devices. Specifically, the quality of subsequently deposited film could be affected by the rough surface. The present study reports that the surface roughness of ferroelectric polymer film can be reduced by a double-spin-coating method of a solution, with control of the solubility of the solution. At an identical thickness of 350 nm, double-spin-coated ferroelectric film has a root-mean-square roughness of only 3 nm, while for single-spin-coated ferroelectric film this value is approximately 16 nm. A ferroelectric-gated field-effect transistor was fabricated using the proposed double-spin-coating method, showing a maximum saturation mobility as much as sevenfold than that of a transistor fabricated with single-spin-coated ferroelectric film. The enhanced saturation mobility could be explained by the Poole–Frenkel conduction mechanism. The proposed method to reduce the surface roughness of ferroelectric film would be useful for high performance organic electronic devices, including crystalline-phase dielectric film. © 2015 Elsevier B.V. All rights reserved.
1. Introduction During the last few years, ferroelectric polymers have been attractive candidates in the field of flexible, transparent and nonvolatile electronic applications due to their superior material properties [1–4]. Specifically, their polarization switching capability enables them to store digital or analog information. Such ferroelectricity originates from their crystalline molecular structure [5], in which dipole moments do not disappeared in the absence of an external electric field. Thus, the ferroelectric material functions as a storage medium when its phase becomes crystalline. The crystalline phase of a ferroelectric polymer can be attained by manipulating various process variables, such as the composition ratio of the monomers, the annealing temperature and time, and the film thickness [6–8], or by stretching the ferroelectric polymer mechanically [9]. The large crystalline structure, however, results in a great degree of surface roughness when the ferroelectric material is used in electronic devices, as it can inadvertently affect the nonuniform electric field distribution inside the ferroelectric film and retard the switching time when polarization reversal arises [10] or an electrical short-circuit forms [11]. More importantly, for many materials, it was
E-mail address: [email protected] (W.Y. Kim).
http://dx.doi.org/10.1016/j.tsf.2015.08.021 0040-6090/© 2015 Elsevier B.V. All rights reserved.
reported that the electrical properties of subsequently deposited film can be affected by the rough interface [12–15]. The surface roughness must be carefully considered when using ferroelectric film and semiconducting film in conjunction with hybrid structure in ferroelectricgated field-effect transistors as a type of the nonvolatile memory. To avoid a rough surface morphology, some alternatives has been suggested, such as inserting a buffer polymer with an amorphous phase [16], using a top-gate structured field-effect transistor [17], blending with another polymer as a crystal-phase inhibitor [18], and filling the gaps among crystalline granules [19]. In this work, we report a double-spin-coating method compatible with solution processes for the formation of a ferroelectric film on the same ferroelectric polymer film without any type of crosslinking agent. This is realized by controlling the solubility of the ferroelectric polymer solution with a small amount of insoluble solvent. From atomic force microscopy measurements, relatively small granules of the ferroelectric polymer are used to fill the inside areas of valleys between larger crystalline mountains. This planarized surface of ferroelectric film was applied to a ferroelectric-gated field-effect transistor to enhance its electronic performance. Our results show that the smooth surface of the ferroelectric film in the ferroelectric-gated fieldeffect transistor has positive effect on the operating voltage and saturation mobility.
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W.Y. Kim et al. / Thin Solid Films 591 (2015) 1–7
2. Experiment 2.1. Principle for double-spin-coating of ferroelectric polymer
Fig. 1. Structure of the ferroelectric-gated field-effect transistor.
Double-spin-coating, in this study, means that a certain material was spin-coated to deposit it onto the same material serially. It is a key point that the double-spin-coating method may be feasible if the solution for the upper-coat of the ferroelectric film does not dissolve the under-laid ferroelectric film. For an inorganic ferroelectric material such as lead zirconate titanate (PZT), the sol–gel method is the standard for forming a thick film [20]. Until the target thickness was achieved, a series of processes (spin-coating, an initial thermal treatment to dry the solvent, and a second thermal treatment to remove the organic ingredients) were repetitively carried out using the sol–gel method. However, this successive spin-coating process cannot be applied to a ferroelectric polymer because the under-lying ferroelectric polymer is unquestionably
Fig. 2. AFM measurement results: (a) relationship between the RMS roughness and the film thickness, which was measured and averaged from 5 different regions (1 μm × 1 μm) on a sample (2 cm × 2 cm), (b) three-dimensional surface morphology of ferroelectric film created by single-spin-coating, (b 1 ) two-dimensional morphology, and (b 2 ) histogram, (c) three-dimensional surface morphology of ferroelectric film made by double-spin-coating, (c1 ) two-dimensional morphology, and (c 2 ) histogram, and (d) proposed crystalline structure model, where dave is the average thickness and Δd ave is the standard deviation of the RMS roughness.
W.Y. Kim et al. / Thin Solid Films 591 (2015) 1–7
affected by exposure to the solvent in the solution. Therefore, the solubility of the ferroelectric solution used for the upper-coat of the ferroelectric film needs to be controlled. According to the literature [21], it is known that the solubility of a solvent can be tuned by mixing some amount of an insoluble solvent into the original soluble solvent on the principle that the added insoluble solvent suppresses the dissolving power of the original soluble solvent. From our previous experiential result [22], the insoluble solvent to be added and the percentage were selected as ethyl-alcohol at a volume ratio of 20%. 2.2. Fabrication of a ferroelectric-gated field-effect transistor For the ferroelectric polymer solution, poly(vinylidene fluoride-cotrifluoroethylene) (P(VDF-TrFE), 75/25 mol%, MSI Sensors Inc.) was dissolved in 1 mL of methyl-ethyl-ketone (MEK) at various concentrations. After complete dissolution, the solution was filtered by a PTFE filter with a pore size of 0.22 μm. Nonlinear variables during the spin-coating process were fixed, in this case a spin speed of 1500 rpm and spin time of 10 s. Thus, the thickness of the ferroelectric film was controlled almost linearly by the ferroelectric polymer concentration of the solution. Under these conditions, the thickness of the ferroelectric film for 0.01 g of P(VDF-TrFE) (1 wt.% for 1 mL) was 90 nm. After spin-coating, the ferroelectric film was annealed at 130 °C on a hot plate for 1 h to remove the solvent residue and increase the crystalline β-phase. On a SiO2/Si wafer, a bottom gate of Cr/Au (10 nm/50 nm) was deposited by thermal evaporation through a shadow mask. Ferroelectric film as the gate dielectric was spin-coated using two different methods. The first is a single-spin-coating method and the second is a double-spincoating method. The total thicknesses of the ferroelectric film were identical at 350 nm. The double-spin-coated ferroelectric film was produced by spin-coating 50 nm of ferroelectric film on an under-lying ferroelectric film of 300 nm. Poly(3-hexylthiophene) (P3HT, Solaris Chem, Inc., CA) solution was prepared through a dissolution process in mono-
3
chlorobenzene for 12 h. as part of the active layer in the ferroelectricgated field-effect transistor. After spin-coating P3HT onto the ferroelectric film/gate electrode structure, the sample was thermally treated at 110 °C on a hot plate for 1 h. Finally, source and drain electrodes were deposited by thermal evaporation through a shadow mask. The channel length and channel width of the fabricated ferroelectric-gated fieldeffect transistors were 45 μm and 980 μm, respectively. The schematic of the ferroelectric-gated field-effect transistor are shown in Fig. 1. 2.3. Characterization of ferroelectric film and ferroelectric-gated field-effect transistors To identify each thickness in double-spin-coated film, the thickness of the ferroelectric film was measured using an α-step instrument (Dektak 6M, Veeco Instruments, Inc.) with a sample prepared by the following procedure. A ferroelectric polymer film was spin-coated at one part on a Si wafer, a part of which was covered with the double-spincoated film. Then, a sample with three different thicknesses was prepared. The surface morphology of each ferroelectric film sample was measured by means of atomic force microscopy (AFM, XE-100, Park Systems Corp.) The current–voltage relationships in ferroelectricgated field-effect transistors and the leakage current through gate dielectric were measured with an HP 4156 (Hewlett-Packard Co.) semiconductor parameter analyzer. To compare crystallinity of two P3HT films, XRD measurements were performed with an X-ray diffractometer (D/MAX-2500, Rigaku). 3. Results and discussion 3.1. Surface morphology of ferroelectric films Fig. 2a shows the relationships between the root-mean-square (RMS) surface roughness and the ferroelectric polymer thickness after
Fig. 3. Characterization of P3HT films: Surface morphology of P3HT measured in 10 μm × 10 μm (a) on SC-FeFET and (b) on DC-FeFET. RMS roughness values are 9.837 nm for SC-FeFET and 9.010 nm for DC-FeFET, respectively. (c) XRD results for two P3HT films. Notation, single, represents the case of SC-FeFET and double is DC-FeFET.
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W.Y. Kim et al. / Thin Solid Films 591 (2015) 1–7
fabrication with two different spin-coating methods. For the ferroelectric films made by the single-spin-coating method (SC-Fe film), the RMS roughness was nearly proportional to the film thickness. For the ferroelectric films made by the double-spin-coating method (DC-Fe film), however, the RMS roughness was nearly constant regardless of the film thickness. In 1 μm × 1 μm area, two atomic force microscopy (AFM) images of ferroelectric films with the same thickness value of 350 nm but made by the two different spin-coating methods are shown in Fig. 2b and c. The morphology of the SC-Fe film shows relatively large granules, with the size of each granule being about 200 nm (Fig. 2b1) and with a RMS roughness of approximately 16 nm. The peak-to-peak height difference is greater than 80 nm (Fig. 2b2). On the other hand, the DC-Fe film shows a nearly flat surface when depicted at the same scale with the single-spin-coating method, of which the RMS roughness is about 3 nm and the granule size is close to 20 nm (Fig. 2c1). The peak-to-peak height difference is less than 20 nm (Fig. 2c2). From the AFM images and their RMS roughness values, models for two crystalline structures of ferroelectric films can be considered, as deave ave ave ave scribed in Fig. 2d. For our cases, dave 1 is equal to d2 + d3 ; and d1 , d2 , and dave are 350 nm, 300 nm, and 50 nm, respectively. As shown in 3 Fig. 2b, dave 1 consists of large crystalline granules, making the standard deviation, Δdave 1 relatively large. However, the relatively large standard deviation, Δdave 2 of 12 nm shown in Fig. 2a is covered with a thin and
ave small crystalline layer of dave + dave has a relatively 3 . As a result, d2 3 ave small standard deviation, Δ(dave 2 + d3 ) of 3 nm, which is nearly identical to the Δdave 3 of 2 nm. These instances of surface planarization are possible because the solution of the upper-coat of the ferroelectric film did not dissolve the under-laid ferroelectric film at all. The FT-IR measurements in our previous report support this and no degradation of the molecular structure appeared during the double-spin-coating process [22].
3.2. Characterization of P3HT films Fig. 3a and b shows the AFM images of P3HT films deposited on two different ferroelectric layers, which were scanned in 10 μm × 10 μm area on the K region depicted in Fig. 1. From two morphology images, there is no big difference and their RMS roughness values are nearly identical to about 9 nm. Surface morphology in P3HT-based films depends on process parameters such as solvent, annealing temperature and annealing time [23–25]. Also the solvent for P3HT, mono-chlorobenzene, cannot dissolve P(VDF-TrFE). Thus, the reason for roughness of 9 nm is expected due to P3HT aggregation. To identify crystallinity of two ferroelectric/P3HT hybrid films, XRD measurements were performed and shown in Fig. 3c. There are two peaks, P1 and P2. P1 means the β-phase of ferroelectric films, thus
Fig. 4. Current–voltage relationships: (a)–(d) ID–VG relationships for different VD values of a SC-FeFET (black solid line) and a DC-FeFET (red solid line); VG was applied from +50 V to −50 V, and went back again. (e) A leakage current for Au/P(VDF-TrFE) 350 nm/Au. Inset shows a schematic of capacitor, which the area is 1 mm × 1 mm.
W.Y. Kim et al. / Thin Solid Films 591 (2015) 1–7
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Fig. 5. Characterization of a SC-FeFET and a DC-FeFET for different VD values, all data are calculated results by averaging each result measured from 5 devices: (a) ON and OFF current, as extracted at a VG = 0 (b) ratio of the ON current and OFF current, (c) ID0.5–VG relationship when VD = −8 V, (d) threshold voltage (VT) extracted from the ID0.5–VG relationship.
two P(VDF-TrFE) films show ferroelectricity. P2 represents (100) peak of P3HT, at which two P3HT films show meaningful difference [26]. In the P3HT film deposited on the DC-Fe film, P3HT was more crystallized. Additional (200) and (300) peaks are not revealed, which may be expected from relatively weaker intensity than (100) peak and P1 peak. As a result, surface morphology manipulation using solubility control is effective for tailoring crystallinity of semiconducting polymer. 3.3. Current–voltage relationships Using the double-spin-coating method, a ferroelectric-gated fieldeffect transistor (FeFET) was fabricated, as shown in Fig. 1. For a performance comparisons, another FeFET with ferroelectric film made by the single-spin-coating method was fabricated for the same device size and thickness. Fig. 4 shows the relationships between the drain current (ID) and the gate voltage (VG) for different drain voltages (VD), and Fig. 5 plots the performances of the two FeFETs. As shown Fig. 5a and b, the ON current (ION) of the DC-FeFET is a little larger than that of the SCFeFET. It seems that the contact resistance (RC) considerably large compared with the channel resistance (Rch) attenuated the VD dependence
of ION. However, the OFF current (IOFF) also shows a similar tendency to ION. The switching ability of the gate bias is virtually identical owing to the nearly identical ION/IOFF ratio. This can be explained by the surface roughness difference. For ION, the channel resistance of DC-FeFET will be smaller than that of the SC-FeFET. For IOFF, the bulk resistance of DCFeFET will be smaller than that of the SC-FeFET because the flat interfaces influence the crystal growth of the semiconducting polymer and the large grain size means fewer grain boundaries. Because the leakage current through dielectric is very small compared with the measured IOFF values as shown in Fig. 4e, the IOFF for a flat transistor would be reduced much more if the active layer, P3HT, can be patterned [27]. In Fig. 4, the DC-FeFET shows superior electric performance in the negative voltage range when the VG is swept from positive to negative though the ID values slightly decrease over VG of −30 V. The current decrease can be understood by strong field-assisted charge trapping into gate dielectric, and thereby gate field-shielding. While the SC-FeFET required more than −40 V for the ON state, the DC-FeFET had already reached the ON state at nearly − 30 V. Fig. 5c shows the ID1/2–VG relationship for a VD value of −8 V, which implies that the ID value of the DC-FeFET increased much more rapidly than it did for the SC-FeFET.
S D S Fig. 6. Saturation mobility (μsat) for different VD values: (a) individual saturation mobility values (μD sat, μsat) and their fitted lines, and (b) ratio of μsat and μsat.
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ID ¼ μ sat C F
W.Y. Kim et al. / Thin Solid Films 591 (2015) 1–7
W ðV G −V T Þ2 ; 2L
ð1Þ
Acknowledgments This work was supported by the Preparatory Project (N10110074) in Korea Advanced Institute of Science and Technology (KAIST).
where μsat is the saturation mobility, CF is the dielectric capacitance of the ferroelectric film, W is the channel width, L is the channel length, and VT is the threshold voltage of the field-effect transistor. Using Eq. (1), the μ sat values for two transistors are plotted in Fig. 6. The saturation mobility for DC-FeFET (μ D sat) is larger than the saturation mobility of the SC-FeFET (μ Ssat). The two transistors are fabricated with identical electrodes of Au and with identical process conditions except for the gate dielectric formation. Therefore, the RC values of the two transistors are also identical. When the transistor is turned on, the total resistance of the drain current path of RON is the sum of RC and the Rch. Therefore, the resistance difference in the ON state is derived only from the Rch difference. From the fixed channel length, a VD value of 5 V corresponds pffiffiffiffiffiffi to ED of 300 (V/m)0.5, which is in the regime of Poole–Frenkel conduction [28], pffiffiffi μ ¼ μ 0 exp γ E ;
ð2Þ
where μ 0 is the zero-field mobility, E is applied electric field, and γ is the Poole–Frenkel constant. From the proportional constants of the two mobility relationships in Fig. 5a, the γD value of the DC-FeFET is about 4.22 × 10− 4 (V/m)− 0.5 and the γS value of the SC-FeFET is close to 2.29 × 10−3 (V/m)−0.5. The physical meaning of γ is the intensity of the disorder of the materials [29]. Therefore, the degree of disorder in the SC-FeFET is much larger than it is in the DC-FeFET. The saturation S mobility ratio of μ D sat and μ sat in Fig. 6b shows a negative slope, as log pffiffiffiffiffiffi D S ðμ sat =μ sat Þ ¼ ðγ D −γ S Þ ED þ constant and because γ S is larger than γ D . In other words, Poole–Frenkel conduction increased by the strong VD contributed to the increase of μ Ssat in the SC-FeFET more than it did in the DC-FeFET, which reduces the saturation mobility D ratio of μsat /μSsat. Given the explanation of Poole–Frenkel conduction for the two transistors, it is concluded that the double-spin-coating method benefits the active layer on the ferroelectric film by forming larger crystalline structure, allowing greater saturation mobility to be achieved so that electronic device will be capable of higher performance levels. 4. Summary and conclusion In this work, a viable method to control the solubility of a solution was attempted for the fabrication of double-spin-coated crystallinephase film. Though ferroelectric film consists of a crystalline phase and has a certain degree of surface roughness, the surface of this type of film could be planarized by the double-spin-coating of a ferroelectric polymer solution at lower concentration. The main breakthrough to minimize the dissolution of the under-lying ferroelectric film was to change the solubility of the solution for the upper-coat on the ferroelectric film, which was achieved by mixing a small amount of an insoluble solvent (ethyl-alcohol) into the ferroelectric solution. The performance difference between two ferroelectric films with different surface roughness values was clearly exhibited in FeFETs. A DC-FeFET showed faster saturation mobility by as much as seven-fold compared to a SC-FeFET, which implies that the surface roughness affects the interface state between the ferroelectric film and the active layer. Additionally, the DC-FeFET required only 75% of the operating voltage of the SC-FeFET when the transistor state switches from the OFF state to the ON state. The method introduced, here, with planarized surface of crystallinephase film, can be used to raise the performance levels of electronic devices with crystalline-phase materials for better operating speeds and low power consumption levels.
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Thin Solid Films journal homepage: www.elsevier.com/locate/tsf
Enhancement of the saturation mobility in a ferroelectric-gated field-effect transistor by the surface planarization of ferroelectric film Woo Young Kim a, Gwang-Jae Jeon b, In-Ku Kang b, Hyun Bin Shim b, Hee Chul Lee b a b
Department of Mechanical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 373-1, Guseong-dong, Yuseong-gu, Daejeon 305-701, Republic of Korea Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 373-1, Guseong-dong, Yuseong-gu, Daejeon 305-701, Republic of Korea
a r t i c l e
i n f o
Article history: Received 29 August 2014 Received in revised form 10 August 2015 Accepted 12 August 2015 Available online 13 August 2015 Keywords: Ferroelectric polymer Solubility control Saturation mobility Poole–Frenkel conduction
a b s t r a c t Ferroelectricity refers to the property of a dielectric material to undergo spontaneous polarization which originates from the crystalline phase. Hence, ferroelectric materials have a certain degree of surface roughness when they are formed as a thin film. A high degree of surface roughness may cause unintended phenomena when the ferroelectric material is used in electronic devices. Specifically, the quality of subsequently deposited film could be affected by the rough surface. The present study reports that the surface roughness of ferroelectric polymer film can be reduced by a double-spin-coating method of a solution, with control of the solubility of the solution. At an identical thickness of 350 nm, double-spin-coated ferroelectric film has a root-mean-square roughness of only 3 nm, while for single-spin-coated ferroelectric film this value is approximately 16 nm. A ferroelectric-gated field-effect transistor was fabricated using the proposed double-spin-coating method, showing a maximum saturation mobility as much as sevenfold than that of a transistor fabricated with single-spin-coated ferroelectric film. The enhanced saturation mobility could be explained by the Poole–Frenkel conduction mechanism. The proposed method to reduce the surface roughness of ferroelectric film would be useful for high performance organic electronic devices, including crystalline-phase dielectric film. © 2015 Elsevier B.V. All rights reserved.
1. Introduction During the last few years, ferroelectric polymers have been attractive candidates in the field of flexible, transparent and nonvolatile electronic applications due to their superior material properties [1–4]. Specifically, their polarization switching capability enables them to store digital or analog information. Such ferroelectricity originates from their crystalline molecular structure [5], in which dipole moments do not disappeared in the absence of an external electric field. Thus, the ferroelectric material functions as a storage medium when its phase becomes crystalline. The crystalline phase of a ferroelectric polymer can be attained by manipulating various process variables, such as the composition ratio of the monomers, the annealing temperature and time, and the film thickness [6–8], or by stretching the ferroelectric polymer mechanically [9]. The large crystalline structure, however, results in a great degree of surface roughness when the ferroelectric material is used in electronic devices, as it can inadvertently affect the nonuniform electric field distribution inside the ferroelectric film and retard the switching time when polarization reversal arises [10] or an electrical short-circuit forms [11]. More importantly, for many materials, it was
E-mail address: [email protected] (W.Y. Kim).
http://dx.doi.org/10.1016/j.tsf.2015.08.021 0040-6090/© 2015 Elsevier B.V. All rights reserved.
reported that the electrical properties of subsequently deposited film can be affected by the rough interface [12–15]. The surface roughness must be carefully considered when using ferroelectric film and semiconducting film in conjunction with hybrid structure in ferroelectricgated field-effect transistors as a type of the nonvolatile memory. To avoid a rough surface morphology, some alternatives has been suggested, such as inserting a buffer polymer with an amorphous phase [16], using a top-gate structured field-effect transistor [17], blending with another polymer as a crystal-phase inhibitor [18], and filling the gaps among crystalline granules [19]. In this work, we report a double-spin-coating method compatible with solution processes for the formation of a ferroelectric film on the same ferroelectric polymer film without any type of crosslinking agent. This is realized by controlling the solubility of the ferroelectric polymer solution with a small amount of insoluble solvent. From atomic force microscopy measurements, relatively small granules of the ferroelectric polymer are used to fill the inside areas of valleys between larger crystalline mountains. This planarized surface of ferroelectric film was applied to a ferroelectric-gated field-effect transistor to enhance its electronic performance. Our results show that the smooth surface of the ferroelectric film in the ferroelectric-gated fieldeffect transistor has positive effect on the operating voltage and saturation mobility.
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2. Experiment 2.1. Principle for double-spin-coating of ferroelectric polymer
Fig. 1. Structure of the ferroelectric-gated field-effect transistor.
Double-spin-coating, in this study, means that a certain material was spin-coated to deposit it onto the same material serially. It is a key point that the double-spin-coating method may be feasible if the solution for the upper-coat of the ferroelectric film does not dissolve the under-laid ferroelectric film. For an inorganic ferroelectric material such as lead zirconate titanate (PZT), the sol–gel method is the standard for forming a thick film [20]. Until the target thickness was achieved, a series of processes (spin-coating, an initial thermal treatment to dry the solvent, and a second thermal treatment to remove the organic ingredients) were repetitively carried out using the sol–gel method. However, this successive spin-coating process cannot be applied to a ferroelectric polymer because the under-lying ferroelectric polymer is unquestionably
Fig. 2. AFM measurement results: (a) relationship between the RMS roughness and the film thickness, which was measured and averaged from 5 different regions (1 μm × 1 μm) on a sample (2 cm × 2 cm), (b) three-dimensional surface morphology of ferroelectric film created by single-spin-coating, (b 1 ) two-dimensional morphology, and (b 2 ) histogram, (c) three-dimensional surface morphology of ferroelectric film made by double-spin-coating, (c1 ) two-dimensional morphology, and (c 2 ) histogram, and (d) proposed crystalline structure model, where dave is the average thickness and Δd ave is the standard deviation of the RMS roughness.
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affected by exposure to the solvent in the solution. Therefore, the solubility of the ferroelectric solution used for the upper-coat of the ferroelectric film needs to be controlled. According to the literature [21], it is known that the solubility of a solvent can be tuned by mixing some amount of an insoluble solvent into the original soluble solvent on the principle that the added insoluble solvent suppresses the dissolving power of the original soluble solvent. From our previous experiential result [22], the insoluble solvent to be added and the percentage were selected as ethyl-alcohol at a volume ratio of 20%. 2.2. Fabrication of a ferroelectric-gated field-effect transistor For the ferroelectric polymer solution, poly(vinylidene fluoride-cotrifluoroethylene) (P(VDF-TrFE), 75/25 mol%, MSI Sensors Inc.) was dissolved in 1 mL of methyl-ethyl-ketone (MEK) at various concentrations. After complete dissolution, the solution was filtered by a PTFE filter with a pore size of 0.22 μm. Nonlinear variables during the spin-coating process were fixed, in this case a spin speed of 1500 rpm and spin time of 10 s. Thus, the thickness of the ferroelectric film was controlled almost linearly by the ferroelectric polymer concentration of the solution. Under these conditions, the thickness of the ferroelectric film for 0.01 g of P(VDF-TrFE) (1 wt.% for 1 mL) was 90 nm. After spin-coating, the ferroelectric film was annealed at 130 °C on a hot plate for 1 h to remove the solvent residue and increase the crystalline β-phase. On a SiO2/Si wafer, a bottom gate of Cr/Au (10 nm/50 nm) was deposited by thermal evaporation through a shadow mask. Ferroelectric film as the gate dielectric was spin-coated using two different methods. The first is a single-spin-coating method and the second is a double-spincoating method. The total thicknesses of the ferroelectric film were identical at 350 nm. The double-spin-coated ferroelectric film was produced by spin-coating 50 nm of ferroelectric film on an under-lying ferroelectric film of 300 nm. Poly(3-hexylthiophene) (P3HT, Solaris Chem, Inc., CA) solution was prepared through a dissolution process in mono-
3
chlorobenzene for 12 h. as part of the active layer in the ferroelectricgated field-effect transistor. After spin-coating P3HT onto the ferroelectric film/gate electrode structure, the sample was thermally treated at 110 °C on a hot plate for 1 h. Finally, source and drain electrodes were deposited by thermal evaporation through a shadow mask. The channel length and channel width of the fabricated ferroelectric-gated fieldeffect transistors were 45 μm and 980 μm, respectively. The schematic of the ferroelectric-gated field-effect transistor are shown in Fig. 1. 2.3. Characterization of ferroelectric film and ferroelectric-gated field-effect transistors To identify each thickness in double-spin-coated film, the thickness of the ferroelectric film was measured using an α-step instrument (Dektak 6M, Veeco Instruments, Inc.) with a sample prepared by the following procedure. A ferroelectric polymer film was spin-coated at one part on a Si wafer, a part of which was covered with the double-spincoated film. Then, a sample with three different thicknesses was prepared. The surface morphology of each ferroelectric film sample was measured by means of atomic force microscopy (AFM, XE-100, Park Systems Corp.) The current–voltage relationships in ferroelectricgated field-effect transistors and the leakage current through gate dielectric were measured with an HP 4156 (Hewlett-Packard Co.) semiconductor parameter analyzer. To compare crystallinity of two P3HT films, XRD measurements were performed with an X-ray diffractometer (D/MAX-2500, Rigaku). 3. Results and discussion 3.1. Surface morphology of ferroelectric films Fig. 2a shows the relationships between the root-mean-square (RMS) surface roughness and the ferroelectric polymer thickness after
Fig. 3. Characterization of P3HT films: Surface morphology of P3HT measured in 10 μm × 10 μm (a) on SC-FeFET and (b) on DC-FeFET. RMS roughness values are 9.837 nm for SC-FeFET and 9.010 nm for DC-FeFET, respectively. (c) XRD results for two P3HT films. Notation, single, represents the case of SC-FeFET and double is DC-FeFET.
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fabrication with two different spin-coating methods. For the ferroelectric films made by the single-spin-coating method (SC-Fe film), the RMS roughness was nearly proportional to the film thickness. For the ferroelectric films made by the double-spin-coating method (DC-Fe film), however, the RMS roughness was nearly constant regardless of the film thickness. In 1 μm × 1 μm area, two atomic force microscopy (AFM) images of ferroelectric films with the same thickness value of 350 nm but made by the two different spin-coating methods are shown in Fig. 2b and c. The morphology of the SC-Fe film shows relatively large granules, with the size of each granule being about 200 nm (Fig. 2b1) and with a RMS roughness of approximately 16 nm. The peak-to-peak height difference is greater than 80 nm (Fig. 2b2). On the other hand, the DC-Fe film shows a nearly flat surface when depicted at the same scale with the single-spin-coating method, of which the RMS roughness is about 3 nm and the granule size is close to 20 nm (Fig. 2c1). The peak-to-peak height difference is less than 20 nm (Fig. 2c2). From the AFM images and their RMS roughness values, models for two crystalline structures of ferroelectric films can be considered, as deave ave ave ave scribed in Fig. 2d. For our cases, dave 1 is equal to d2 + d3 ; and d1 , d2 , and dave are 350 nm, 300 nm, and 50 nm, respectively. As shown in 3 Fig. 2b, dave 1 consists of large crystalline granules, making the standard deviation, Δdave 1 relatively large. However, the relatively large standard deviation, Δdave 2 of 12 nm shown in Fig. 2a is covered with a thin and
ave small crystalline layer of dave + dave has a relatively 3 . As a result, d2 3 ave small standard deviation, Δ(dave 2 + d3 ) of 3 nm, which is nearly identical to the Δdave 3 of 2 nm. These instances of surface planarization are possible because the solution of the upper-coat of the ferroelectric film did not dissolve the under-laid ferroelectric film at all. The FT-IR measurements in our previous report support this and no degradation of the molecular structure appeared during the double-spin-coating process [22].
3.2. Characterization of P3HT films Fig. 3a and b shows the AFM images of P3HT films deposited on two different ferroelectric layers, which were scanned in 10 μm × 10 μm area on the K region depicted in Fig. 1. From two morphology images, there is no big difference and their RMS roughness values are nearly identical to about 9 nm. Surface morphology in P3HT-based films depends on process parameters such as solvent, annealing temperature and annealing time [23–25]. Also the solvent for P3HT, mono-chlorobenzene, cannot dissolve P(VDF-TrFE). Thus, the reason for roughness of 9 nm is expected due to P3HT aggregation. To identify crystallinity of two ferroelectric/P3HT hybrid films, XRD measurements were performed and shown in Fig. 3c. There are two peaks, P1 and P2. P1 means the β-phase of ferroelectric films, thus
Fig. 4. Current–voltage relationships: (a)–(d) ID–VG relationships for different VD values of a SC-FeFET (black solid line) and a DC-FeFET (red solid line); VG was applied from +50 V to −50 V, and went back again. (e) A leakage current for Au/P(VDF-TrFE) 350 nm/Au. Inset shows a schematic of capacitor, which the area is 1 mm × 1 mm.
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Fig. 5. Characterization of a SC-FeFET and a DC-FeFET for different VD values, all data are calculated results by averaging each result measured from 5 devices: (a) ON and OFF current, as extracted at a VG = 0 (b) ratio of the ON current and OFF current, (c) ID0.5–VG relationship when VD = −8 V, (d) threshold voltage (VT) extracted from the ID0.5–VG relationship.
two P(VDF-TrFE) films show ferroelectricity. P2 represents (100) peak of P3HT, at which two P3HT films show meaningful difference [26]. In the P3HT film deposited on the DC-Fe film, P3HT was more crystallized. Additional (200) and (300) peaks are not revealed, which may be expected from relatively weaker intensity than (100) peak and P1 peak. As a result, surface morphology manipulation using solubility control is effective for tailoring crystallinity of semiconducting polymer. 3.3. Current–voltage relationships Using the double-spin-coating method, a ferroelectric-gated fieldeffect transistor (FeFET) was fabricated, as shown in Fig. 1. For a performance comparisons, another FeFET with ferroelectric film made by the single-spin-coating method was fabricated for the same device size and thickness. Fig. 4 shows the relationships between the drain current (ID) and the gate voltage (VG) for different drain voltages (VD), and Fig. 5 plots the performances of the two FeFETs. As shown Fig. 5a and b, the ON current (ION) of the DC-FeFET is a little larger than that of the SCFeFET. It seems that the contact resistance (RC) considerably large compared with the channel resistance (Rch) attenuated the VD dependence
of ION. However, the OFF current (IOFF) also shows a similar tendency to ION. The switching ability of the gate bias is virtually identical owing to the nearly identical ION/IOFF ratio. This can be explained by the surface roughness difference. For ION, the channel resistance of DC-FeFET will be smaller than that of the SC-FeFET. For IOFF, the bulk resistance of DCFeFET will be smaller than that of the SC-FeFET because the flat interfaces influence the crystal growth of the semiconducting polymer and the large grain size means fewer grain boundaries. Because the leakage current through dielectric is very small compared with the measured IOFF values as shown in Fig. 4e, the IOFF for a flat transistor would be reduced much more if the active layer, P3HT, can be patterned [27]. In Fig. 4, the DC-FeFET shows superior electric performance in the negative voltage range when the VG is swept from positive to negative though the ID values slightly decrease over VG of −30 V. The current decrease can be understood by strong field-assisted charge trapping into gate dielectric, and thereby gate field-shielding. While the SC-FeFET required more than −40 V for the ON state, the DC-FeFET had already reached the ON state at nearly − 30 V. Fig. 5c shows the ID1/2–VG relationship for a VD value of −8 V, which implies that the ID value of the DC-FeFET increased much more rapidly than it did for the SC-FeFET.
S D S Fig. 6. Saturation mobility (μsat) for different VD values: (a) individual saturation mobility values (μD sat, μsat) and their fitted lines, and (b) ratio of μsat and μsat.
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ID ¼ μ sat C F
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W ðV G −V T Þ2 ; 2L
ð1Þ
Acknowledgments This work was supported by the Preparatory Project (N10110074) in Korea Advanced Institute of Science and Technology (KAIST).
where μsat is the saturation mobility, CF is the dielectric capacitance of the ferroelectric film, W is the channel width, L is the channel length, and VT is the threshold voltage of the field-effect transistor. Using Eq. (1), the μ sat values for two transistors are plotted in Fig. 6. The saturation mobility for DC-FeFET (μ D sat) is larger than the saturation mobility of the SC-FeFET (μ Ssat). The two transistors are fabricated with identical electrodes of Au and with identical process conditions except for the gate dielectric formation. Therefore, the RC values of the two transistors are also identical. When the transistor is turned on, the total resistance of the drain current path of RON is the sum of RC and the Rch. Therefore, the resistance difference in the ON state is derived only from the Rch difference. From the fixed channel length, a VD value of 5 V corresponds pffiffiffiffiffiffi to ED of 300 (V/m)0.5, which is in the regime of Poole–Frenkel conduction [28], pffiffiffi μ ¼ μ 0 exp γ E ;
ð2Þ
where μ 0 is the zero-field mobility, E is applied electric field, and γ is the Poole–Frenkel constant. From the proportional constants of the two mobility relationships in Fig. 5a, the γD value of the DC-FeFET is about 4.22 × 10− 4 (V/m)− 0.5 and the γS value of the SC-FeFET is close to 2.29 × 10−3 (V/m)−0.5. The physical meaning of γ is the intensity of the disorder of the materials [29]. Therefore, the degree of disorder in the SC-FeFET is much larger than it is in the DC-FeFET. The saturation S mobility ratio of μ D sat and μ sat in Fig. 6b shows a negative slope, as log pffiffiffiffiffiffi D S ðμ sat =μ sat Þ ¼ ðγ D −γ S Þ ED þ constant and because γ S is larger than γ D . In other words, Poole–Frenkel conduction increased by the strong VD contributed to the increase of μ Ssat in the SC-FeFET more than it did in the DC-FeFET, which reduces the saturation mobility D ratio of μsat /μSsat. Given the explanation of Poole–Frenkel conduction for the two transistors, it is concluded that the double-spin-coating method benefits the active layer on the ferroelectric film by forming larger crystalline structure, allowing greater saturation mobility to be achieved so that electronic device will be capable of higher performance levels. 4. Summary and conclusion In this work, a viable method to control the solubility of a solution was attempted for the fabrication of double-spin-coated crystallinephase film. Though ferroelectric film consists of a crystalline phase and has a certain degree of surface roughness, the surface of this type of film could be planarized by the double-spin-coating of a ferroelectric polymer solution at lower concentration. The main breakthrough to minimize the dissolution of the under-lying ferroelectric film was to change the solubility of the solution for the upper-coat on the ferroelectric film, which was achieved by mixing a small amount of an insoluble solvent (ethyl-alcohol) into the ferroelectric solution. The performance difference between two ferroelectric films with different surface roughness values was clearly exhibited in FeFETs. A DC-FeFET showed faster saturation mobility by as much as seven-fold compared to a SC-FeFET, which implies that the surface roughness affects the interface state between the ferroelectric film and the active layer. Additionally, the DC-FeFET required only 75% of the operating voltage of the SC-FeFET when the transistor state switches from the OFF state to the ON state. The method introduced, here, with planarized surface of crystallinephase film, can be used to raise the performance levels of electronic devices with crystalline-phase materials for better operating speeds and low power consumption levels.
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