- Email: [email protected]
Experimental and numerical results correlation during extreme use of power MOSFET designed for avalanche functional mode
Microelectronics Reliability 50 (2010) 1804–1809
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Experimental and numerical results correlation during extreme use of power MOSFET designed for avalanche functional mode L. Dupont a,*, J.L. Blanchard b, R. Lallemand a, G. Coquery a, J.M. Morelle b, G. Blondel c, B. Rouleau c a
LTN Laboratory, INRETS, 25 allée des Marronniers, 78000 Versailles, France VALEO CEE, 5 avenue Newton F-78180 Montigny le Bretonneux, France c VALEO VES, R&D Department, 2 rue André Boulle F-94017 Creteil, France b
a r t i c l e
i n f o
Article history: Received 30 June 2010 Accepted 19 July 2010 Available online 11 August 2010
a b s t r a c t Cost, weight and size reduction constrained designers of power electronic for micro hybrid vehicle to use power MOSFET under extreme conditions like avalanche mode. This paper shows the influence of the solder voids onto the die temperature distribution of a specifically designed power MOSFET. In the first part of this paper, a methodology is presented to perform fast dynamic temperature measurements during MOSFET avalanche (400 A–80 ls). In the second part of the paper, a comparison between experimental results and finite elements electro-thermal simulation is shown for power MOSFET operating in high conduction mode (500 A–100 ms). Finally the correlated numerical model is used to evaluate the sensitivity to solder voids of the chip temperature distribution. Ó 2010 Elsevier Ltd. All rights reserved.
1. Introduction
2. Presentation of experimental tests
Electrical or hybrid vehicles are one of the solutions that will conduct to a reduction of fossil energy consumption. The proposed vehicle system needs to start the internal combustion engine in a very short time. This function involves high electrical and thermal stresses in the semiconductors. In power electronic for micro hybrid vehicles, the cost and weight reduction objectives conducted to use power MOSFET under extreme conditions like unclamped inductive switching (UIS) and high peak power conduction mode. These new and extreme conditions of use may yield to electrical and thermal over stresses that can damage or fail power modules and power chip [1,2]. Even if the power MOSFET and power module developed by VALEO are tailored for used under these extreme conditions, the chip temperature distribution remains one of most important criteria which impact the life time to failure of power electronic [3]. This study proposes an evaluation of the MOSFET transistor temperature evolution during specific harsh conditions as avalanche and high current density conduction during short time. An infrared temperature measurement has been used to acquire the high dynamic variations of the chip temperature. The results presented in this paper introduce a correlation between an experimental campaign and a finite elements modelling. First results showing the solder voids impact on the chip temperature distribution will be also presented.
This first part relates the chip surface temperature evolution during avalanche mode. The electro-thermal test bench is developed by INRETS-LTN laboratory (Fig. 1). The base plate (heat-sink) temperature is controlled by avalanche frequency for a specific avalanche profile that is representative of the electrical stresses. The objective of this bench is to test the components in avalanche mode with a triangular current waveform. First, the current increases in the inductance L2 through the switch M1. When the current reaches the desired current we open it. Now the inductance current is flowing through the DUT and decreases due to the avalanche mode (The DUT transistor gate is always connected to the source). We adjust the supply voltage and the conduction time of switch M1 to set the maximum current and the avalanche time. When the current is coming back to zero we can measure junction temperature Tj with an electrical indirect method and to do that we have to disconnect the device from the power circuit with switch M2. The current measurement is made with a noninductive shunt (2.5 m X), voltages are directly recorded with a 12 bits high speed isolated modules. As we can see in the Fig. 2, a large number of measurement tools have been used to control electrical and thermal parameters (thermocouple (TK), infrared camera, high speed recorder. . .). Especially, an open thermocouple is located on the copper substrate, close to the device under test (DUT), in order to compare the surface temperature with the infrared (IR) temperature evaluation. This measurement is used to adjust the emissivity value of the black painting, which covers all parts of the controlled area (e = 0.95). Other thermocouples were used to control temperature
* Corresponding author. E-mail address: [email protected] (L. Dupont). 0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.07.127
L. Dupont et al. / Microelectronics Reliability 50 (2010) 1804–1809
1805
Fig. 1. Partial presentation of the UIS test bench.
Fig. 4. UIS test with synchronous acquisition chronogram.
DUT. In this case, the current injection is only controlled by the MOS transistor under test (DUT). The infrared camera (CEDIP TITANIUM 550) is used to control the surface temperature evolution during the power injection with an acquisition frequency up to 1 kHz with an integration time of 134 ls.
3. Finite elements model
Fig. 2. Test bench with thermal and electrical sensors.
around the active part. These thermocouples were located on the backside of the substrate and in the electrical connectors (Fig. 3). The temperature measurements will be used to control the test conditions and define initial conditions in thermal equilibrium for the finite elements modelling. Due to the high dynamic Unclamped Inductive Switching (UIS) phenomena (80 ls), the temperature evaluation by infrared camera is based on so-called ‘‘sampling technique” (repetitive acquisitions realised during multiple UIS tests with a 100 ns shifting delay) of the start infrared acquisition time. A post treatment is realised in order to recompose the real surface temperature evolution during UIS test. The high speed infrared camera (CEDIP TITANIUM 550) is used in trig mode with an integration time adapted to temperature variation during the test after thermal equilibrium (Fig. 4). For the high power conduction campaign, the electrical test bench has been limited to a current source connected to the
Electrical Connectors
Chip location
Fig. 3. Location of thermocouples on the back side (red points: open TK – green points: closed TK). (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
The simulations are carried out with a FEM (finite element model), enabling to accurately represent the module geometry, with a special mention to the bonding shape. However, the salient feature of the 3D model is to deal with a non-linear transient 2-physics simulation, the electrical and thermal fields being concurrently computed. This is much more accurate than the simplified methodology based on the reduced model of a volume heat source for modelling the heat dissipation by joule effect. In our calculation, the joule effect only takes place where the current flows that the related heat generation is automatically adjusted according to the electrical resistivity of the materials. The whole simulation is performed within ANSYS 12.0. The thermal and electrical properties of materials are respectively listed in Tables 1 and 2, with the location of their use, as detailed in Figs. 5 and 6. The silicon electrical resistivity, which plays a central role in the simulation, is actually modelled in such a way that the resistance across the die thickness follows the temperature-dependent RDSon variation measured by the die manufacturer. The boundary conditions which lead the module electrical behaviour consist of the ground reference tension at the phase connection and of a prescribed current at the plus connection, through nodal couplings respectively located at the periphery of the holes where the connecting wires are screwed (Fig. 5). By contrast, the thermal boundary conditions are only made up of an imposed temperature (23 °C) on the radiator back face. The dices that are not thermally coupled are excluded from the model, for reducing the mesh size. Regarding the mesh, consistently with the focus placed on the phenomena taking place in the die stack, a fine hexahedron-dominant one is employed for it. The model, including 532,422 nodes and 245,811 elements, is finally processed through an APDL (ANSYS Parametric Design Language) script to specify the time strategy and the initial uniform temperature, 23 °C, as provided by the experimental measurements. On completion of the simulation, the post-processing of the tension maps enables to check that the tension drops across the various parts of the module are consistent with the experimental measurements, special attention being paid to the bonding and VDS ones. This latter has been found to be in accordance with the maximum RDSon value measured by the manufacturer and no further adjustment was required.
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L. Dupont et al. / Microelectronics Reliability 50 (2010) 1804–1809
Table 1 Material thermal properties. Material (properties at 25 °C)
Density (kg m 3)
Thermal cond. (W m 1 K 1)
Specific heat (J kg 1 K 1)
Aluminium Grease Aluminium Adhesive Copper Braze Invar Silicon Aluminium Aluminium
2700 2000 2700 2710 8960 11,100 8125 2330 2700 2710
120 0.42 148 1.9 390 32.7 14.7 148 200 230
1300 700 870 700 380 150 385 710 910 910
(radiator) (backplate)
(layer) (bonding)
Table 2 Material electrical resistivity. Material
T (°C)
r (X m)
T (°C)
r (X m)
Copper Braze Invar Silicon
0 25 25 40 175 0
1.384 10 8 1.9 10 7 8.2 10 7 1.32 10 4 2.69 10 4 2.412 10 8
1000
9.384 10
Aluminium
8
Fig. 6. Electrical waveforms acquire during the UIS test.
1.66 10 4 2.94 10 4 1.366 10 7
25 200 900
4. Temperature evaluation during avalanche mode The electrical measurements (IDS, VDS, Vbonding) of the avalanche test were presented in Fig. 6. The infrared camera trigger command is presented at the first acquisition step in the same figure. The first results of dynamic temperature evaluation by infrared measurements has been realised on test vehicles with and without voids in the solder. Due to the confidentiality aspects of this study, temperatures were presented in a relative unit (T/Tmaximum.). Fig. 7 depicts the typical temperature evolution during the avalanche test on power module M3944 (without void) before and after the post-processing of the infrared camera data. The analytical expression of the temperature rise during avalanche is close to experimental results (analytical: 36.6 K – experimental: 35.1 K) [4,5]. However, the time where the maximum temperature is reached is larger than the half time of the avalanche duration. A new methodology is currently investigated to control the influence of the top chip layers (metallization, painting thickness. . .), which impact the thermal impedance. Similarly, a fast indirect measurement by the body diode is developed to correlate dynamic infrared temperature measurements.
Backplate
Imposed tension
Fig. 7. Evolution of the temperature during the avalanche.
Chip
A-A
Leadframes Adhesive
Grease Fig. 8. M3944 – infrared temperature distribution (relative unit) in case of no void.
Imposed current
Radiator Fig. 5. Global model view.
The following figures compare the temperature distribution (in relative unit) at the maximum avalanche temperature. The Figs. 8 and 9 present the temperature distribution for modules without and with voids, respectively, in the chip solder.
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L. Dupont et al. / Microelectronics Reliability 50 (2010) 1804–1809
Chip
A-A
Fig. 11. Power injection acquisition chronogram. Fig. 9. RX47 – infrared temperature distribution (relative unit) in case of void.
Chip
B-B
Fig. 12. M3390 – infrared temperature distribution (relative unit) at the end of the power injection. Fig. 10. Infrared temperature profile in avalanche mode.
As can be seen from this comparison the voids do seem not to impact the temperature distribution during UIS test. This distribution is characterised by a relatively homogenous temperature map. In this mode of experiment, the wires contribute to cool down the chip top, as illustrated in Fig. 10 where the location of profile AA is given in Fig. 8).
5. Comparison of FEM and experimental results during high power conduction The study above has been made for 80 ls long avalanche mode. In this paragraph, we focus now on 100 ms long conduction mode. The test bench used for short time high power injection is similar to the UIS test bench with large simplifications beside the instrumentations. The power MOSFET is used to perform the square power injection of 500 A during 100 ms. In order to avoid an excessive temperature rise, the power injection duty cycle is limited to 1% (Fig. 11). Fig. 12 shows the temperature distribution (relative unit) at the end of the power injection (t0 + 100 ms) for the module M3390 without void in the chip solder. The maximum temperature is reached in the wire bonding due to the self-heating caused by the 500 A current level. The temperature distribution computed by simulation (Fig. 13) is fully consistent with the experimental measurements in Fig. 12. These results contribute to control the validity of the methodology developed for the temperature measurements by infrared camera.
Fig. 13. Simulation – temperature distribution at the end of the power injection.
Indeed, the concurrent electrical–thermal simulations carried out on the finite element model give results very close to experimental values (Fig. 14). The slight remaining discrepancy can be explained by the simplification of the simulated current waveform induced lower power dissipation in the chip. The impact of solder void on the chip temperature distribution has been analysed for a case study corresponding to a very big void, corresponding to a size around 5% of the die area. Fig. 15 shows the temperature distribution at the end of the power injection for an assembly with a solder void. The next figure gives the IR temperature distribution of the temperature along the black line BB defined in Fig. 16. For the module RX74 a local temperature rise takes place at the location where a void is detected by X-ray analysis.
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L. Dupont et al. / Microelectronics Reliability 50 (2010) 1804–1809
Bonding
Chip Void
Solder
Fig. 17. RX74 – evaluation of the solder void and the wire bonding attach to the chip metallization by micro-section.
Fig. 14. Electrical measurements evaluated by simulation.
However, no damage can be detected at the interface with the chip metallization. 6. Conclusion
Chip
B-B
Fig. 15. RX74 – infrared temperature distribution (relative unit) at the end of the power injection and RX analysis.
The ability to use a power MOSFET under very harsh conditions implies a good understanding of the main damaging factors such as the temperature distribution and hot spot temperature of semiconductors. This paper is an introduction of the experimental and numerical tools that have been used in this perspective. For the UIS test conditions, the evaluation of a high dynamic temperature variation leads to results in close agreement with analytical approximations. In this mode, the experimental results seem to confirm the low impact onto chip temperature of void in the chip solder joints. Nevertheless, in view of the difficulties of the temperature measurement by infrared camera, it would be quite useful to get complementary data with other methodologies not limited to the surface temperature measurement. As a matter of fact, a new test bench is being developed in order to propose in the future a comparison of IR temperature with the indirect method like body diode characteristics. This methodology has the advantage to evaluate the temperature in the silicon. An improved methodology for temperature measurement from infrared camera acquisition is also under development. In the case of high power short time conduction mode, the close agreements between experimental and numerical studies demonstrate the ability of multi-physical modelling for process design improvement. The confrontation of numerical results with dice damage is currently under study. A very encouraging result is actually that the size and location of the solder voids can be monitored and controlled to drastically reduce their possible effects on the die temperature distribution. Acknowledgments We wish to thank VALEO for their help in the power module setup, especially for the specific development of power modules with large solder void that were necessary to fulfil the purpose of this study. References
Fig. 16. Infrared temperature profile in high power injection.
In order to validate the void location in the module RX74 assembly, a micro-section was done (Fig. 17). This result confirms the presence of a void in the chip solder under the wire bonding.
[1] Ciappa M. Selected failure mechanisms of modern power modules. Microelectron Reliab 2002;42. [2] Saint-Eve F, Lefebvre S, Khatir Z. Reliability of COOLMOSTM under extremely hard repetitive electrical working conditions. In: IEEE ISPSD 03. Cambridge UK; April 2003.
L. Dupont et al. / Microelectronics Reliability 50 (2010) 1804–1809 [3] Bernoux B, Escoffier R, Jalbaud P, Dorkel JM. Source electrode evolution of a low voltage power MOSFET under avalanche cycling. Microelectron Reliab 2009;49:1341–5. [4] McGloin J, Sdrulla D. Estimating the temperature rise of power MOSFETs during the UIS test. In: Proceeding of APEC; 1992. p. 448–53.
1809
[5] Salem TE, Ibitayo D, Geil B. Validation of infrared camera thermal measurements on high-voltage power electronic components. IEEE Trans Instrum Measure 2007;56(5):1973–8.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Experimental and numerical results correlation during extreme use of power MOSFET designed for avalanche functional mode L. Dupont a,*, J.L. Blanchard b, R. Lallemand a, G. Coquery a, J.M. Morelle b, G. Blondel c, B. Rouleau c a
LTN Laboratory, INRETS, 25 allée des Marronniers, 78000 Versailles, France VALEO CEE, 5 avenue Newton F-78180 Montigny le Bretonneux, France c VALEO VES, R&D Department, 2 rue André Boulle F-94017 Creteil, France b
a r t i c l e
i n f o
Article history: Received 30 June 2010 Accepted 19 July 2010 Available online 11 August 2010
a b s t r a c t Cost, weight and size reduction constrained designers of power electronic for micro hybrid vehicle to use power MOSFET under extreme conditions like avalanche mode. This paper shows the influence of the solder voids onto the die temperature distribution of a specifically designed power MOSFET. In the first part of this paper, a methodology is presented to perform fast dynamic temperature measurements during MOSFET avalanche (400 A–80 ls). In the second part of the paper, a comparison between experimental results and finite elements electro-thermal simulation is shown for power MOSFET operating in high conduction mode (500 A–100 ms). Finally the correlated numerical model is used to evaluate the sensitivity to solder voids of the chip temperature distribution. Ó 2010 Elsevier Ltd. All rights reserved.
1. Introduction
2. Presentation of experimental tests
Electrical or hybrid vehicles are one of the solutions that will conduct to a reduction of fossil energy consumption. The proposed vehicle system needs to start the internal combustion engine in a very short time. This function involves high electrical and thermal stresses in the semiconductors. In power electronic for micro hybrid vehicles, the cost and weight reduction objectives conducted to use power MOSFET under extreme conditions like unclamped inductive switching (UIS) and high peak power conduction mode. These new and extreme conditions of use may yield to electrical and thermal over stresses that can damage or fail power modules and power chip [1,2]. Even if the power MOSFET and power module developed by VALEO are tailored for used under these extreme conditions, the chip temperature distribution remains one of most important criteria which impact the life time to failure of power electronic [3]. This study proposes an evaluation of the MOSFET transistor temperature evolution during specific harsh conditions as avalanche and high current density conduction during short time. An infrared temperature measurement has been used to acquire the high dynamic variations of the chip temperature. The results presented in this paper introduce a correlation between an experimental campaign and a finite elements modelling. First results showing the solder voids impact on the chip temperature distribution will be also presented.
This first part relates the chip surface temperature evolution during avalanche mode. The electro-thermal test bench is developed by INRETS-LTN laboratory (Fig. 1). The base plate (heat-sink) temperature is controlled by avalanche frequency for a specific avalanche profile that is representative of the electrical stresses. The objective of this bench is to test the components in avalanche mode with a triangular current waveform. First, the current increases in the inductance L2 through the switch M1. When the current reaches the desired current we open it. Now the inductance current is flowing through the DUT and decreases due to the avalanche mode (The DUT transistor gate is always connected to the source). We adjust the supply voltage and the conduction time of switch M1 to set the maximum current and the avalanche time. When the current is coming back to zero we can measure junction temperature Tj with an electrical indirect method and to do that we have to disconnect the device from the power circuit with switch M2. The current measurement is made with a noninductive shunt (2.5 m X), voltages are directly recorded with a 12 bits high speed isolated modules. As we can see in the Fig. 2, a large number of measurement tools have been used to control electrical and thermal parameters (thermocouple (TK), infrared camera, high speed recorder. . .). Especially, an open thermocouple is located on the copper substrate, close to the device under test (DUT), in order to compare the surface temperature with the infrared (IR) temperature evaluation. This measurement is used to adjust the emissivity value of the black painting, which covers all parts of the controlled area (e = 0.95). Other thermocouples were used to control temperature
* Corresponding author. E-mail address: [email protected] (L. Dupont). 0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.07.127
L. Dupont et al. / Microelectronics Reliability 50 (2010) 1804–1809
1805
Fig. 1. Partial presentation of the UIS test bench.
Fig. 4. UIS test with synchronous acquisition chronogram.
DUT. In this case, the current injection is only controlled by the MOS transistor under test (DUT). The infrared camera (CEDIP TITANIUM 550) is used to control the surface temperature evolution during the power injection with an acquisition frequency up to 1 kHz with an integration time of 134 ls.
3. Finite elements model
Fig. 2. Test bench with thermal and electrical sensors.
around the active part. These thermocouples were located on the backside of the substrate and in the electrical connectors (Fig. 3). The temperature measurements will be used to control the test conditions and define initial conditions in thermal equilibrium for the finite elements modelling. Due to the high dynamic Unclamped Inductive Switching (UIS) phenomena (80 ls), the temperature evaluation by infrared camera is based on so-called ‘‘sampling technique” (repetitive acquisitions realised during multiple UIS tests with a 100 ns shifting delay) of the start infrared acquisition time. A post treatment is realised in order to recompose the real surface temperature evolution during UIS test. The high speed infrared camera (CEDIP TITANIUM 550) is used in trig mode with an integration time adapted to temperature variation during the test after thermal equilibrium (Fig. 4). For the high power conduction campaign, the electrical test bench has been limited to a current source connected to the
Electrical Connectors
Chip location
Fig. 3. Location of thermocouples on the back side (red points: open TK – green points: closed TK). (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
The simulations are carried out with a FEM (finite element model), enabling to accurately represent the module geometry, with a special mention to the bonding shape. However, the salient feature of the 3D model is to deal with a non-linear transient 2-physics simulation, the electrical and thermal fields being concurrently computed. This is much more accurate than the simplified methodology based on the reduced model of a volume heat source for modelling the heat dissipation by joule effect. In our calculation, the joule effect only takes place where the current flows that the related heat generation is automatically adjusted according to the electrical resistivity of the materials. The whole simulation is performed within ANSYS 12.0. The thermal and electrical properties of materials are respectively listed in Tables 1 and 2, with the location of their use, as detailed in Figs. 5 and 6. The silicon electrical resistivity, which plays a central role in the simulation, is actually modelled in such a way that the resistance across the die thickness follows the temperature-dependent RDSon variation measured by the die manufacturer. The boundary conditions which lead the module electrical behaviour consist of the ground reference tension at the phase connection and of a prescribed current at the plus connection, through nodal couplings respectively located at the periphery of the holes where the connecting wires are screwed (Fig. 5). By contrast, the thermal boundary conditions are only made up of an imposed temperature (23 °C) on the radiator back face. The dices that are not thermally coupled are excluded from the model, for reducing the mesh size. Regarding the mesh, consistently with the focus placed on the phenomena taking place in the die stack, a fine hexahedron-dominant one is employed for it. The model, including 532,422 nodes and 245,811 elements, is finally processed through an APDL (ANSYS Parametric Design Language) script to specify the time strategy and the initial uniform temperature, 23 °C, as provided by the experimental measurements. On completion of the simulation, the post-processing of the tension maps enables to check that the tension drops across the various parts of the module are consistent with the experimental measurements, special attention being paid to the bonding and VDS ones. This latter has been found to be in accordance with the maximum RDSon value measured by the manufacturer and no further adjustment was required.
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L. Dupont et al. / Microelectronics Reliability 50 (2010) 1804–1809
Table 1 Material thermal properties. Material (properties at 25 °C)
Density (kg m 3)
Thermal cond. (W m 1 K 1)
Specific heat (J kg 1 K 1)
Aluminium Grease Aluminium Adhesive Copper Braze Invar Silicon Aluminium Aluminium
2700 2000 2700 2710 8960 11,100 8125 2330 2700 2710
120 0.42 148 1.9 390 32.7 14.7 148 200 230
1300 700 870 700 380 150 385 710 910 910
(radiator) (backplate)
(layer) (bonding)
Table 2 Material electrical resistivity. Material
T (°C)
r (X m)
T (°C)
r (X m)
Copper Braze Invar Silicon
0 25 25 40 175 0
1.384 10 8 1.9 10 7 8.2 10 7 1.32 10 4 2.69 10 4 2.412 10 8
1000
9.384 10
Aluminium
8
Fig. 6. Electrical waveforms acquire during the UIS test.
1.66 10 4 2.94 10 4 1.366 10 7
25 200 900
4. Temperature evaluation during avalanche mode The electrical measurements (IDS, VDS, Vbonding) of the avalanche test were presented in Fig. 6. The infrared camera trigger command is presented at the first acquisition step in the same figure. The first results of dynamic temperature evaluation by infrared measurements has been realised on test vehicles with and without voids in the solder. Due to the confidentiality aspects of this study, temperatures were presented in a relative unit (T/Tmaximum.). Fig. 7 depicts the typical temperature evolution during the avalanche test on power module M3944 (without void) before and after the post-processing of the infrared camera data. The analytical expression of the temperature rise during avalanche is close to experimental results (analytical: 36.6 K – experimental: 35.1 K) [4,5]. However, the time where the maximum temperature is reached is larger than the half time of the avalanche duration. A new methodology is currently investigated to control the influence of the top chip layers (metallization, painting thickness. . .), which impact the thermal impedance. Similarly, a fast indirect measurement by the body diode is developed to correlate dynamic infrared temperature measurements.
Backplate
Imposed tension
Fig. 7. Evolution of the temperature during the avalanche.
Chip
A-A
Leadframes Adhesive
Grease Fig. 8. M3944 – infrared temperature distribution (relative unit) in case of no void.
Imposed current
Radiator Fig. 5. Global model view.
The following figures compare the temperature distribution (in relative unit) at the maximum avalanche temperature. The Figs. 8 and 9 present the temperature distribution for modules without and with voids, respectively, in the chip solder.
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L. Dupont et al. / Microelectronics Reliability 50 (2010) 1804–1809
Chip
A-A
Fig. 11. Power injection acquisition chronogram. Fig. 9. RX47 – infrared temperature distribution (relative unit) in case of void.
Chip
B-B
Fig. 12. M3390 – infrared temperature distribution (relative unit) at the end of the power injection. Fig. 10. Infrared temperature profile in avalanche mode.
As can be seen from this comparison the voids do seem not to impact the temperature distribution during UIS test. This distribution is characterised by a relatively homogenous temperature map. In this mode of experiment, the wires contribute to cool down the chip top, as illustrated in Fig. 10 where the location of profile AA is given in Fig. 8).
5. Comparison of FEM and experimental results during high power conduction The study above has been made for 80 ls long avalanche mode. In this paragraph, we focus now on 100 ms long conduction mode. The test bench used for short time high power injection is similar to the UIS test bench with large simplifications beside the instrumentations. The power MOSFET is used to perform the square power injection of 500 A during 100 ms. In order to avoid an excessive temperature rise, the power injection duty cycle is limited to 1% (Fig. 11). Fig. 12 shows the temperature distribution (relative unit) at the end of the power injection (t0 + 100 ms) for the module M3390 without void in the chip solder. The maximum temperature is reached in the wire bonding due to the self-heating caused by the 500 A current level. The temperature distribution computed by simulation (Fig. 13) is fully consistent with the experimental measurements in Fig. 12. These results contribute to control the validity of the methodology developed for the temperature measurements by infrared camera.
Fig. 13. Simulation – temperature distribution at the end of the power injection.
Indeed, the concurrent electrical–thermal simulations carried out on the finite element model give results very close to experimental values (Fig. 14). The slight remaining discrepancy can be explained by the simplification of the simulated current waveform induced lower power dissipation in the chip. The impact of solder void on the chip temperature distribution has been analysed for a case study corresponding to a very big void, corresponding to a size around 5% of the die area. Fig. 15 shows the temperature distribution at the end of the power injection for an assembly with a solder void. The next figure gives the IR temperature distribution of the temperature along the black line BB defined in Fig. 16. For the module RX74 a local temperature rise takes place at the location where a void is detected by X-ray analysis.
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L. Dupont et al. / Microelectronics Reliability 50 (2010) 1804–1809
Bonding
Chip Void
Solder
Fig. 17. RX74 – evaluation of the solder void and the wire bonding attach to the chip metallization by micro-section.
Fig. 14. Electrical measurements evaluated by simulation.
However, no damage can be detected at the interface with the chip metallization. 6. Conclusion
Chip
B-B
Fig. 15. RX74 – infrared temperature distribution (relative unit) at the end of the power injection and RX analysis.
The ability to use a power MOSFET under very harsh conditions implies a good understanding of the main damaging factors such as the temperature distribution and hot spot temperature of semiconductors. This paper is an introduction of the experimental and numerical tools that have been used in this perspective. For the UIS test conditions, the evaluation of a high dynamic temperature variation leads to results in close agreement with analytical approximations. In this mode, the experimental results seem to confirm the low impact onto chip temperature of void in the chip solder joints. Nevertheless, in view of the difficulties of the temperature measurement by infrared camera, it would be quite useful to get complementary data with other methodologies not limited to the surface temperature measurement. As a matter of fact, a new test bench is being developed in order to propose in the future a comparison of IR temperature with the indirect method like body diode characteristics. This methodology has the advantage to evaluate the temperature in the silicon. An improved methodology for temperature measurement from infrared camera acquisition is also under development. In the case of high power short time conduction mode, the close agreements between experimental and numerical studies demonstrate the ability of multi-physical modelling for process design improvement. The confrontation of numerical results with dice damage is currently under study. A very encouraging result is actually that the size and location of the solder voids can be monitored and controlled to drastically reduce their possible effects on the die temperature distribution. Acknowledgments We wish to thank VALEO for their help in the power module setup, especially for the specific development of power modules with large solder void that were necessary to fulfil the purpose of this study. References
Fig. 16. Infrared temperature profile in high power injection.
In order to validate the void location in the module RX74 assembly, a micro-section was done (Fig. 17). This result confirms the presence of a void in the chip solder under the wire bonding.
[1] Ciappa M. Selected failure mechanisms of modern power modules. Microelectron Reliab 2002;42. [2] Saint-Eve F, Lefebvre S, Khatir Z. Reliability of COOLMOSTM under extremely hard repetitive electrical working conditions. In: IEEE ISPSD 03. Cambridge UK; April 2003.
L. Dupont et al. / Microelectronics Reliability 50 (2010) 1804–1809 [3] Bernoux B, Escoffier R, Jalbaud P, Dorkel JM. Source electrode evolution of a low voltage power MOSFET under avalanche cycling. Microelectron Reliab 2009;49:1341–5. [4] McGloin J, Sdrulla D. Estimating the temperature rise of power MOSFETs during the UIS test. In: Proceeding of APEC; 1992. p. 448–53.
1809
[5] Salem TE, Ibitayo D, Geil B. Validation of infrared camera thermal measurements on high-voltage power electronic components. IEEE Trans Instrum Measure 2007;56(5):1973–8.