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Fabrication of indium bumps for hybrid infrared focal plane array applications
Infrared Physics & Technology 45 (2004) 143–151 www.elsevier.com/locate/infrared
Fabrication of indium bumps for hybrid infrared focal plane array applications Jutao Jiang a, Stanley Tsao a, Thomas OÕSullivan a, Manijeh Razeghi Gail J. Brown b
a,*
,
a
b
Department of Electrical and Computer Engineering, Center for Quantum Devices, Northwestern University, 2220 North Campus Drive, Cook Hall, Room 4051, Evanston, IL 60208, USA Air Force Research Laboratory, Materials and Manufacturing, Directorate, AFRL/MLPS, Wright-Patterson AFB, OH 45433-7707, USA Received 6 April 2003
Abstract Hybrid infrared focal plane arrays (FPAs) have found many applications. In hybrid IR FPAs, FPA and Si read out integrated circuits (ROICs) are bonded together with indium bumps by flip-chip bonding. Taller and higher uniformity indium bumps are always being pursued in FPA fabrication. In this paper, two indium bump fabrication processes based on evaporation and electroplating techniques are developed. Issues related to each fabrication technique are addressed in detail. The evaporation technique is based on a unique positive lithography process. The electroplating method achieves taller indium bumps with a high aspect ratio by a unique ‘‘multi-stack’’ technique. This technique could potentially benefit the fabrication of multi-color FPAs. Finally, a proposed low-cost indium bump fabrication technique, the ‘‘bump transfer’’, is given as a future technology for hybrid IR FPA fabrication. 2003 Elsevier B.V. All rights reserved. Keywords: Indium; Bump; Infrared; Focal plane array; Electroplating; Evaporation; Lift-off
1. Introduction Infrared focal plane arrays (FPA) have achieved many applications in different fields including military, environmental, civil, industrial, and medical [1–3]. There is a growing need for very large format FPAs [4]. For those very large format hybrid in*
Corresponding author. Tel.: +1-847-491-7251; fax: +1-847467-1817. E-mail addresses: [email protected], [email protected] (M. Razeghi). URL: http://cqd.ece.northwestern.edu.
frared FPAs based on HgCdTe detectors or quantum well infrared photodetectors (QWIPs), flipchip bonding technology becomes almost inevitable because they need connections between every single pixel to a silicon based read out integrated circuit (ROIC) [5]. Flip-chip interconnection offers a number of advantages over the more widely used wire bonding technique. The advantages include high I/O density and short interconnect distance between chip and substrate, leading to high device performance and miniature products [6]. Indium has become the most important mating material for infrared FPAs due to the facts that it
1350-4495/$ - see front matter 2003 Elsevier B.V. All rights reserved. doi:10.1016/j.infrared.2003.08.002
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stays ductile at liquid helium temperature, is easy to work with, and simply forms a good bond at room temperature. A primary concern for flip-chip bonding is minimizing fatigue in the indium bumps. Due to the coefficient of thermal expansion (CTE) mismatch between most semiconductor substrates (e.g. InP and GaAs) and Si substrate, indium bumps for most infrared FPAs experience stress from the thermal cycling between 300 and 77 K that occurs during normal detector operation. These thermal cycles produce relative displacement between the detector and the Si ROIC resulting in shear stress at the interfaces between the indium bumps and metal pads (see Fig. 1). The displacement indium bumps experience during thermal cycles is represented as: DL ¼ L0 DT ðkFPA kSi Þ
ð1Þ
where L0 is the distance from the indium joint to the center point of FPA hybrid, which we can treat as a neutral point where the ROIC and FPA substrate do not contract relative to each other. kFPA and kSi are the CTE of the FPA substrate and Si, respectively. DT is the temperature change. The shear stress produced by this displacement is represented as: c¼
DL L0 DT ðkFPA kSi Þ ¼ hsolder hsolder
ð2Þ
where c is the tangential displacement of indium joint, which is DL per unit joint height hsolder . If the
Fig. 1. Schematic of thermal strain experienced by an indium bump.
FPA hybrid is cooled down to 77 K during each imaging session and then allowed to return to room temperature after usage, the indium joint will experience a cyclic shear strain and hence a cyclic shear stress. After many cycles, say Nf , there is a chance of joint failure, termed as fatigue. This cycle number Nf depends on the magnitude of joint shear strain. Flip-chip bonding reliability is related to its fatigue life, which is represented as [7]: 2 1 Dc 1 Nf ¼ ð0:65h=LDaDT Þ2 ð3Þ 2 0:65 2 As shown, the solder joint fatigue is directly proportional to the square of the solder joint height and inversely proportional to the square of the L0 , the mismatch of CTE, and the temperature change that the FPA hybrid experiences DT . For a specific infrared FPA, the temperature change DT and effective L0 are fixed. So increasing bump height and decreasing thermal expansion mismatch are the feasible solutions for increasing reliability. To decrease thermal expansion mismatch, FPA substrate thinning and removal methods have been developed [8]. To increase bump height, larger area indium bump methods have been utilized. After reflow, the bump height will increase due to the surface tension of the indium bump [9]. But this method does not work for very large format FPAs due to the very small pitch size. Another very important reason for increasing bump height is to dispense underfill into the gap between the FPA detectors and the ROIC because the minimum distance should be larger than twice the fillet size (about 2–4 lm) for most commercially available underfill material [10]. Underfill is based on an epoxy material system and can protect the indium joint from the environment and reduce stresses on the indium joint, thus increasing the reliability of FPA hybrids. Underfill also provides the necessary mechanical strength for the FPA substrate thinning process mentioned above. Taller indium bumps also reduce the stringent requirement for parallelism between the FPA and ROIC chip during flip-chip bonding and tolerate more nonuniformity of indium bump height across the FPA. For very large format (larger than 640 · 480) infrared FPAs, the pitch size is usually less than 30 lm, and the size of the detector pixel is even
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smaller. To bond these FPAs with ROIC, indium bumps with very high aspect ratios (>1) are needed. Currently, two primary methods exist for indium bump fabrication: evaporation and electroplating [11]. Two types of bump evaporation techniques are widely used: IBMÕs C4 process and lift-off. In IBMÕs C4 process, a metal mask (typically molybdenum) with holes is used to pattern the wafer for bump evaporation [12]. The metal is deposited through the holes onto the wafer during the evaporation. Lift-off bump evaporation is similar to the standard metal contact lift-off process except thicker photoresist is generally used. The evaporation method is relatively expensive due to the high-cost equipment and waste of source material. The electroplated bump method (also called UV-LIGA) is a cost effective, flexible, and reliable bump fabrication technology. It has been used in the microelectronics industry for many years [13–15]. To make tall bumps, very thick photoresist (PR) lithography (>20 lm) based on expensive stepper systems is usually involved. Very strict process control on PR spinning and UV exposure is required [16]. Even with these measures, it is still very difficult to control the profile for very small features. In this paper, both lift-off evaporation and electroplating techniques used for indium bump fabrication are developed. All of the photolithography is performed on a common contact mode Karl Suss MJB3 mask aligner. The indium evaporation technique is based on a unique positive lithography process. To achieve taller, high aspect ratio indium bumps, a new ‘‘multi-stack’’ indium bump fabrication method based on electroplating is also developed. Finally, a proposed ‘‘bump transfer’’ technique will be introduced. This technique has many potential advantages compared to both conventional indium evaporation and electroplating methods.
2. Indium bump evaporation technique Evaporated indium bumps rely on the standard lift-off technique. The key for lift-off is the formation of a photoresist undercut profile. The easiest method to achieve an undercut profile is to
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use negative photoresist and a clear field photomask (bump area is covered with chromium on the mask). Another popular method is the so called ‘‘image reversal’’. Image reversal was first introduced as a technique that creates a negative acting positive resist. This allows the user to be able to keep the repeatability and resolution often associated with positive resist. Most image reversal processes follow six-steps: coating, soft-baking, pattern exposure, post-exposure bake, flood exposure, and developing. In this paper, a unique lithography method is developed to achieve a very good undercut profile using normal positive resist and a dark field photomask (bump area is transparent on the chromium mask). A schematic of the fabrication steps is shown in Fig. 2. In the figure, only one detector pixel with top metal contact is illustrated. The details are given below step by step. 1. The first layer of photoresist is spun onto the sample. To achieve taller indium bumps, thick positive photoresist AZ P4620 is used in this work. With spin speed at 2000 rpm, 10 lm thick resist can be achieved with a single coat. After spinning, the sample is softbaked for 10 min at 96 C. 2. Flood exposure is performed for the AZ P4620 resist. The UV dosage is 3200 mJ/cm2 (measured at h-line 405 nm). Before the flood exposure, the sample is left in the air for at least 30 min to further remove any solvent from the resist. If too much solvent is left inside the thick photoresist, bubbles will form during the UV flood exposure (due to the heat generated inside the resist by UV light). After this step, the whole layer of AZ P4620 resist achieves a very high dissolution rate inside the developer (AZ 400K in this work) and therefore, a develop-enhanced resist bottom layer is formed. 3. The second layer of photoresist (positive resist AZ 4330) is spun onto the sample. After spinning, the sample is softbaked for 50 s at 96 C. 4. Photolithography is performed on a Karl Suss MJB 3 contact mode mask aligner with a dark field photomask. The exposure dose (150 mJ/ cm2 ) is chosen so that only the top resist layer is fully exposed.
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UV
Fig. 2. Schematic of evaporated indium bump fabrication processing based on positive lithography.
5. Before the resist developing, the sample is soaked in chlorobenzene for 5 m. Chlorobenzene soaking is used to form a develop-inhibited resist top layer. The absorption of the chlorobenzene solvent into the resist results in the extraction of novolak and in turn the unexposed surface region exhibits a reduced develop rate [17–19]. 6. The sample is developed in AZ 400K developer. Due to the combination of a develop-enhanced bottom resist layer and a develop-inhibited resist top layer, very good undercut profiles are created in this double layer of positive resist (shown in Fig. 3). Before any metal evaporation, an O2 plasma cleaning (ashing) is performed on the sample to remove any possible resist residue at the bottom of the resist openings. 7. Three metal layers-Ti/Pt/Au are deposited onto the sample by using an electron-beam evaporator. These metal layers are used as under-bumpmetallurgy (UBM), also known as ball limiting metallurgy (BLM). In solder bump processing, UBM is used to anchor the solder bump to the infrared detector pixels. UBM usually con-
sists of three layers of metal: adhesion layer (Ti), solder diffusion barrier (Pt), and solder wettable layer (Au). 8. Right after UBM evaporation, indium is deposited onto the sample via a thermal evaporator. The sample is water-cooled during the evaporation to avoid excessive heating-up of the photoresist. Some photoresist residue was observed after lift-off for those samples where no water-cooling was applied during the indium evaporation. Another reason for watercooling samples is to achieve well-defined indium bumps. During the long indium evaporation process, the sample could be heated well above indiumÕs melting point of 157 C. In that case, the evaporated indium is in the liquid state and might spread inside the resist mold. 9. Lift-off is performed with AZ 400T stripper. The stripper is heated up to 80 C during the lift-off process. Indium bump reflow can be performed at 200 C inside a hydrogen atmosphere for 20 m. From the authorÕs experience, indium reflow is not absolutely necessary for infrared FPA application.
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Fig. 3. Undercut profile achieved with double positive resist layer.
The above indium bump evaporation method has been used for the fabrication of a QWIP FPA [20]. In our indium bump evaporation method, by adjusting the bottom and top resist thickness, indium bumps as tall as 10 lm can be achieved. The advantage of this unique indium lift-off method is its high resolution since only positive resists are involved. The high resolution is maintained despite the thick layer of resist because only the thin top layer of resist actually defines the pattern. It is the combination of flood exposure, double layered resist, and chlorobenzene soaking creates the strong undercut profile that gives the method its advantages. The techniqueÕs relative simplicity does not require expensive high precision equipment, but still achieves reliable results. Aside from bump creation, the resist preparation technique can be used for metal lift-off in cases where an appropriate photomask for negative lithography is unavailable.
3. Indium bump electroplating technique Electroplating is a popular alternative to the evaporation process because of its overall lower cost. It has been widely used in the integrated circuit (IC) industry for flip-chip bonding applications in which the pitch and bump size are relatively large (100 lm). However, electroplating has not been widely used for fabrication of indium bumps for hybrid infrared FPAs. This may be because of the very small pitch and bump size
necessary for most FPAs and the non-uniformity of bump height in electroplated bumps. The nonuniformity is due to the non-uniform electroplating current density across the wafer. In this paper, we will show that the electroplating method can in fact be used to fabricate small indium bumps with acceptable bump height uniformity for FPA fabrication. The fabrication steps are shown in Fig. 4. Again, only one detector pixel is illustrated in this schematic. The details of this process are given below step by step. 1. After infrared detector fabrication, a dielectric passivation layer is deposited on to the sample by plasma enhanced chemical vapor deposition (PECVD). Passivation material selection is carried out with the goal of minimizing absorption in the detection wavelength range of the infrared detector [21]. Passivation is necessary for electroplated bump fabrication since a blanket metal current path layer will be deposited on the whole surface of sample later. Without a passivation layer, some detector pixels will be shorted by the metal current path layer even though this metal layer is to be removed at the end of bump processing. 2. Contact holes are etched on top of each detector pixel through the passivation layer. This can be done with standard lithography and dry etching techniques. 3. A blanket UBM metal layer is deposited on to the whole sample surface with an electron-beam evaporator. The UBM consists of Ti/Pt/Au. In
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AZ P4620 Passivation layer
(1)
(4)
(7)
Indium bump Contact hole
(2)
(5)
(8)
UBM layer
(3)
(6)
Fig. 4. Schematic of electroplated indium bump fabrication processing.
addition to providing an anchoring function, as in the case of our indium bump evaporation technique, the UBM metal layer here also serves as the current path necessary for the electroplating process. 4. Thick resist AZ P4620 is spun and patterned. The resist thickness is 10 lm. O2 plasma cleaning is performed after resist developing. 5. Indium electroplating is performed inside an indium sulfamate plating bath (supplied by Arconium Corp.) at room temperature. The anode is a pure indium slab. No agitation is applied during the plating. The FPA wafer (square shaped in this work) is connected to the cathode by one of its corners by stripping the photoresist off. An Agilent E3642A DC power supply is used to supply the plating current. To improve bump height uniformity, two measures are taken. First, a small plating current is used. Second, the plating current is applied at each of the four corners of the wafer in sequence so that non-uniformity of current density related to cathode location can be balanced. It was also observed that the largest bump height non-uniformity occurs near the edges of the wafer, so high uniform indium
bumps in central region of wafer can still be achieved after plating. 6. After indium plating, resist is stripped off with AZ 400T stripper. 7. UBM layer is etched off by dry etching. This is performed in an electron cyclotron resonance reactive ion etching (ECR-RIE) reactor with CF4 /H2 gases. 8. Indium bump reflow is performed inside a furnace under H2 atmosphere. Indium bumps as tall as 10 lm have been fabricated with the above electroplating method. The pitch of the indium bumps was 25 lm. As shown in Eq. (2), taller indium bumps always enhance the infrared hybrid FPAÕs long-term reliability. In order to achieve tall indium bumps in small pitch FPAs (e.g. high aspect ratio bumps), a simple technique, the ‘‘multi-stack’’ bump method, was developed based on the above electroplating bump technique. Immediately after the first indium bump plating, another thick resist layer AZ P4620 is spun onto the sample. After resist patterning and developing (Fig. 5a), a second indium electroplating is performed (Fig. 5b). After resist removal (Fig. 5c) and bump reflow (Fig. 5d), 28 lm tall indium bumps with an as-
J. Jiang et al. / Infrared Physics & Technology 45 (2004) 143–151
(a)
(b)
(c)
(d)
Fig. 5. Schematic of ‘‘multi-stack’’ indium bump electroplating technique. Variable height (shown here) and diameter bumps can be fabricated on the same chip with this technique.
pect ratio of 2 was achieved (see Fig. 6). Theoretically, this technique can be repeated more than twice to create even higher aspect ratio bumps. A major potential advantage of this
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‘‘multi-stack’’ indium bump technique is that it can be used to fabricate variable height (illustrated in Fig. 5) and diameter indium bumps on the same FPA. This capability may be useful for multi-color infrared FPA fabrication and some MEMS applications. In most multi-color FPAs, each pixel has more than one indium bump in order to read out signals simultaneously from each active region [22]. All indium bumps are made on the top of each FPA pixel so that the bumps can have the same top level, which is important for reliable flip-chip bonding. Extra metal interconnections are required to connect each active region to the top of the pixel. This requires extra metallization steps and reduces the real estate that can be used for light coupling grating fabrication. With the ‘‘multi-stack’’ indium bump technique, variable height indium bumps can be fabricated directly at the level of each active region such that the tops of all the indium bumps are still at the same level.
Fig. 6. Side views of indium bumps before and after reflow. (a) Single-stacked bump before reflow; (b) single-stacked bump after reflow, the diameter of the reflowed bump is 11 lm and its aspect ratio is 1; (c) double-stacked bump before reflow; (d) double-stacked bump after reflow, the bump height is 28 lm, the maximum diameter is 14 lm, and the aspect ratio is 2.
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4. A new approach for indium bump fabrication In this section, a new approach for indium bump fabrication is given in order to overcome the drawbacks of both evaporation and electroplating techniques. The major drawback of indium bump evaporation is its high cost due to expensive equipment and expensive wasted indium from excess deposition. For indium bump electroplating, the major drawback is the requirement of depositing and removing a current path metal layer. For hybrid infrared FPA fabrication, flip-chip bonding is the one indispensable step. In the following, a new indium bump fabrication technique is proposed, but no experimentation has been performed yet. The schematic of this process is shown in Fig. 7. 1. Electroplating current path metal layer is deposited on a ‘‘dummy’’ substrate. The key to this step is choosing the right type of metal to form the bonding layer between the ‘‘dummy’’ substrate and the indium bumps. This metal should not oxidize easily. Additionally, this metal should not be wettable to indium (or have a low wettability to indium). Another possible option is to use a conductive ‘‘dummy’’ wafer with low wettability to indium. In this case, an extra bonding layer for the indium bumps is unnecessary. 2. After thick resist patterning and developing, indium plating is performed on the dummy subDummy wafer (1)
(2)
FPA wafer (3) (4)
(5) Fig. 7. Schematic of ‘‘bump transfer’’ technique for low-cost indium bump fabrication.
strate. Indium bump height is controlled by the resist thickness. To achieve high aspect ratio indium bumps or variable height indium bumps, the ‘‘multi-stack’’ technique introduced above can be used. 3. Detector array is fabricated with standard lithography and etching technique. Ohmic contacts are made on top of each detector pixel with either lift-off or etch back technique. The top layer metal contact should use a material which has very good wettability to indium, such as Au. 4. Flip-chip bonding aligner can be used to transfer the indium bumps from the dummy substrate to the FPA substrate. Both the dummy substrate and the FPA substrate need to be heated above indiumÕs melting point under inert atmosphere (such as N2 ). After fine alignment of the flip-chip bonding aligner, a small bonding pressure will be applied first. While keeping the high temperature for both substrates, the vacuum chunk that holds the dummy substrate will be lifted up, pulling the dummy substrate away from the detector array. Due to the large difference of indium bonding energy between the metal on the dummy substrate and the metal on the FPA substrate (e.g. Au), the indium bumps will be transferred from the dummy substrate to the detector array. 5. During the final indium bump reflow, due to the self-alignment, indium bumps will aligned perfectly with ohmic contact on top of each detector pixel. The above indium bump fabrication is similar to the microball mounting method [23], in which premade microsolder balls are mounted on the PBGA package or CSP substrate with a multi-hold vacuum chunk. In that method, microsolder balls are made by melting metal pieces previously prepared to a constant weight with ball size range from 35 to 100 lm. In our indium bump transfer method, much smaller indium bumps (<10 lm) are premade with electroplating. The advantage of our indium bump transfer technique is that the fabrication of the indium bumps and the FPA are separated. The dummy transfer wafer can also be re-used for bump electroplating.
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5. Conclusions In summary, indium bump fabrication based on both evaporation and electroplating method is developed in this paper. Our indium evaporation method is based on a unique positive lithography process and can achieve high resolutions. Our electroplating method can produce acceptably uniform indium bumps suitable for IR FPA applications. This electroplating method can also be extended to produce high aspect ratio indium bumps or even variable height and diameter indium bumps by a new ‘‘multi-stack’’ technique. The fabrication of multi-color infrared FPAs can potentially benefit greatly from this ‘‘multi-stack’’ method. Finally, to further simplify indium bump fabrication and reduce its cost, a promising indium bump transfer technique is proposed in this paper. This technique can be easily adapted to other industry flip-chip bonding applications. References [1] C.A. Kukkonen, S.D. Gunapala, S.V. Bandara, J.K. Liu, J. LIorens, Proc. SPIE 3698 (1999) 706. [2] H. Schneider, M. Walther, C. Sch€ onbein, R. Rehm, J. Fleissner, W. Pleteschen, J. Braunstein, P. Koidl, G. Weimann, J. Ziegler, W. Cabanski, Physica E 7 (2000) 101. [3] S.D. Gunapala, S.V. Bandara, A. Singh, J.K. Liu, S.B. Rafol, E.M. Luong, J.M. Mumolo, N.Q. Tran, J.D. Vincent, C.A. Shott, J. Long, P.D. LeVan, Proc. SPIE 3698 (1999) 687. [4] K. Vural, L.J. Kozlowski, D.E. Cooper, C.A. Chen, G.L. Bostrup, C. Cabelli, J.M. Arias, J. Bajaj, K.W. Hodapp, D.N. Hall, W.E. Kleinhans, G.G. Price, J.A. Pinter, Proc. SPIE 3698 (1999) 24. [5] J. Jiang, C. Jelen, M. Razeghi, G.J. Brown, IEEE Photonics Technol. Lett. 14 (2002) 372.
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[6] J.H. Lau (Ed.), Flip Chip Technologies, McGraw-Hill, New York, 1996. [7] M.J. Varnau, S. Yeh, Flip Chip/BGA Workshop, Binghamton, NY, October 1996. [8] S.D. Gunapala, S.V. Bandara, A. Singh, J.K. Liu, S.B. Rafol, E.M. Luong, J.M. Mumolo, N.Q. Tran, J.D. Vincent, C.A. Shott, J. Long, P.D. LeVan, IEEE Trans. Electron Devices 47 (2000) 963. [9] Young-Ho Kim, Jong-Hwa Choi, Kang-Sik Choi, Hee Chul Lee, Choong-Ki Kim, Proc. SPIE 3061 (1997) 60. [10] J.H. Lau, C. Chang, IEEE Trans. Components Packag. Technol., Part A 22 (1999) 111. [11] J.H. Lau, Low Cost Flip-Chip Technologies for DCA, WLCSP, and PBGA Assemblies, McGraw-Hill, New York, 2000. [12] J. Griffin, Electron. Packag. Prod. 37 (1997) 55. [13] Todd Flynn, Christopher W. Argento, Jim OÕBrien, Proc. SPIE 3906 (1999) 8. [14] A.B. Frazier, M.G. Allen, J. Microelectromech. Syst. 2 (87) (1993) 87. [15] Edward K. Yung, Iwona Turlik, IEEE Trans. Components Hybrids Manufact. Technol. 14 (1991) 549. [16] Warren W. Flack, Sylvia White, Bradley Todd, Proc. SPIE 3678 (1999) 49. [17] Marc J. Madou, Fundamentals of Microfabrication: The Science of Miniaturization, CRC Press, New York, 2002 (Chapter 1). [18] B.J. Canavello, M. Hatzakis, J.M. Shaw, IBM J. Res. Develop. 24 (1980) 452. [19] G.G. Collins, C.W. Halsted, IBM J. Res. Develop. 26 (1982) 596. [20] J. Jiang, K. Mi, R. McClintock, M. Razeghi, G.J. Brown, C. Jelen, Demonstration of 256 · 256 focal plane array based on Al-free GalnAs/InP quantum well infrared photodetectors, IEEE Photonics Technol. Lett. 15 (2003) 1273. [21] N.C. Das, K.K. Choi, IEEE Trans. Electron Devices 47 (2000) 653. [22] A. Rogalski, J. Appl. Phys. 93 (2003) 4355. [23] K. Shimokawa, E. Hashino, Y. Ohzeki, K. Tatsumi, in: Proceedings of 48 Electronic Components and Technology Conference, 1998, p. 1472.
Fabrication of indium bumps for hybrid infrared focal plane array applications Jutao Jiang a, Stanley Tsao a, Thomas OÕSullivan a, Manijeh Razeghi Gail J. Brown b
a,*
,
a
b
Department of Electrical and Computer Engineering, Center for Quantum Devices, Northwestern University, 2220 North Campus Drive, Cook Hall, Room 4051, Evanston, IL 60208, USA Air Force Research Laboratory, Materials and Manufacturing, Directorate, AFRL/MLPS, Wright-Patterson AFB, OH 45433-7707, USA Received 6 April 2003
Abstract Hybrid infrared focal plane arrays (FPAs) have found many applications. In hybrid IR FPAs, FPA and Si read out integrated circuits (ROICs) are bonded together with indium bumps by flip-chip bonding. Taller and higher uniformity indium bumps are always being pursued in FPA fabrication. In this paper, two indium bump fabrication processes based on evaporation and electroplating techniques are developed. Issues related to each fabrication technique are addressed in detail. The evaporation technique is based on a unique positive lithography process. The electroplating method achieves taller indium bumps with a high aspect ratio by a unique ‘‘multi-stack’’ technique. This technique could potentially benefit the fabrication of multi-color FPAs. Finally, a proposed low-cost indium bump fabrication technique, the ‘‘bump transfer’’, is given as a future technology for hybrid IR FPA fabrication. 2003 Elsevier B.V. All rights reserved. Keywords: Indium; Bump; Infrared; Focal plane array; Electroplating; Evaporation; Lift-off
1. Introduction Infrared focal plane arrays (FPA) have achieved many applications in different fields including military, environmental, civil, industrial, and medical [1–3]. There is a growing need for very large format FPAs [4]. For those very large format hybrid in*
Corresponding author. Tel.: +1-847-491-7251; fax: +1-847467-1817. E-mail addresses: [email protected], [email protected] (M. Razeghi). URL: http://cqd.ece.northwestern.edu.
frared FPAs based on HgCdTe detectors or quantum well infrared photodetectors (QWIPs), flipchip bonding technology becomes almost inevitable because they need connections between every single pixel to a silicon based read out integrated circuit (ROIC) [5]. Flip-chip interconnection offers a number of advantages over the more widely used wire bonding technique. The advantages include high I/O density and short interconnect distance between chip and substrate, leading to high device performance and miniature products [6]. Indium has become the most important mating material for infrared FPAs due to the facts that it
1350-4495/$ - see front matter 2003 Elsevier B.V. All rights reserved. doi:10.1016/j.infrared.2003.08.002
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stays ductile at liquid helium temperature, is easy to work with, and simply forms a good bond at room temperature. A primary concern for flip-chip bonding is minimizing fatigue in the indium bumps. Due to the coefficient of thermal expansion (CTE) mismatch between most semiconductor substrates (e.g. InP and GaAs) and Si substrate, indium bumps for most infrared FPAs experience stress from the thermal cycling between 300 and 77 K that occurs during normal detector operation. These thermal cycles produce relative displacement between the detector and the Si ROIC resulting in shear stress at the interfaces between the indium bumps and metal pads (see Fig. 1). The displacement indium bumps experience during thermal cycles is represented as: DL ¼ L0 DT ðkFPA kSi Þ
ð1Þ
where L0 is the distance from the indium joint to the center point of FPA hybrid, which we can treat as a neutral point where the ROIC and FPA substrate do not contract relative to each other. kFPA and kSi are the CTE of the FPA substrate and Si, respectively. DT is the temperature change. The shear stress produced by this displacement is represented as: c¼
DL L0 DT ðkFPA kSi Þ ¼ hsolder hsolder
ð2Þ
where c is the tangential displacement of indium joint, which is DL per unit joint height hsolder . If the
Fig. 1. Schematic of thermal strain experienced by an indium bump.
FPA hybrid is cooled down to 77 K during each imaging session and then allowed to return to room temperature after usage, the indium joint will experience a cyclic shear strain and hence a cyclic shear stress. After many cycles, say Nf , there is a chance of joint failure, termed as fatigue. This cycle number Nf depends on the magnitude of joint shear strain. Flip-chip bonding reliability is related to its fatigue life, which is represented as [7]: 2 1 Dc 1 Nf ¼ ð0:65h=LDaDT Þ2 ð3Þ 2 0:65 2 As shown, the solder joint fatigue is directly proportional to the square of the solder joint height and inversely proportional to the square of the L0 , the mismatch of CTE, and the temperature change that the FPA hybrid experiences DT . For a specific infrared FPA, the temperature change DT and effective L0 are fixed. So increasing bump height and decreasing thermal expansion mismatch are the feasible solutions for increasing reliability. To decrease thermal expansion mismatch, FPA substrate thinning and removal methods have been developed [8]. To increase bump height, larger area indium bump methods have been utilized. After reflow, the bump height will increase due to the surface tension of the indium bump [9]. But this method does not work for very large format FPAs due to the very small pitch size. Another very important reason for increasing bump height is to dispense underfill into the gap between the FPA detectors and the ROIC because the minimum distance should be larger than twice the fillet size (about 2–4 lm) for most commercially available underfill material [10]. Underfill is based on an epoxy material system and can protect the indium joint from the environment and reduce stresses on the indium joint, thus increasing the reliability of FPA hybrids. Underfill also provides the necessary mechanical strength for the FPA substrate thinning process mentioned above. Taller indium bumps also reduce the stringent requirement for parallelism between the FPA and ROIC chip during flip-chip bonding and tolerate more nonuniformity of indium bump height across the FPA. For very large format (larger than 640 · 480) infrared FPAs, the pitch size is usually less than 30 lm, and the size of the detector pixel is even
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smaller. To bond these FPAs with ROIC, indium bumps with very high aspect ratios (>1) are needed. Currently, two primary methods exist for indium bump fabrication: evaporation and electroplating [11]. Two types of bump evaporation techniques are widely used: IBMÕs C4 process and lift-off. In IBMÕs C4 process, a metal mask (typically molybdenum) with holes is used to pattern the wafer for bump evaporation [12]. The metal is deposited through the holes onto the wafer during the evaporation. Lift-off bump evaporation is similar to the standard metal contact lift-off process except thicker photoresist is generally used. The evaporation method is relatively expensive due to the high-cost equipment and waste of source material. The electroplated bump method (also called UV-LIGA) is a cost effective, flexible, and reliable bump fabrication technology. It has been used in the microelectronics industry for many years [13–15]. To make tall bumps, very thick photoresist (PR) lithography (>20 lm) based on expensive stepper systems is usually involved. Very strict process control on PR spinning and UV exposure is required [16]. Even with these measures, it is still very difficult to control the profile for very small features. In this paper, both lift-off evaporation and electroplating techniques used for indium bump fabrication are developed. All of the photolithography is performed on a common contact mode Karl Suss MJB3 mask aligner. The indium evaporation technique is based on a unique positive lithography process. To achieve taller, high aspect ratio indium bumps, a new ‘‘multi-stack’’ indium bump fabrication method based on electroplating is also developed. Finally, a proposed ‘‘bump transfer’’ technique will be introduced. This technique has many potential advantages compared to both conventional indium evaporation and electroplating methods.
2. Indium bump evaporation technique Evaporated indium bumps rely on the standard lift-off technique. The key for lift-off is the formation of a photoresist undercut profile. The easiest method to achieve an undercut profile is to
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use negative photoresist and a clear field photomask (bump area is covered with chromium on the mask). Another popular method is the so called ‘‘image reversal’’. Image reversal was first introduced as a technique that creates a negative acting positive resist. This allows the user to be able to keep the repeatability and resolution often associated with positive resist. Most image reversal processes follow six-steps: coating, soft-baking, pattern exposure, post-exposure bake, flood exposure, and developing. In this paper, a unique lithography method is developed to achieve a very good undercut profile using normal positive resist and a dark field photomask (bump area is transparent on the chromium mask). A schematic of the fabrication steps is shown in Fig. 2. In the figure, only one detector pixel with top metal contact is illustrated. The details are given below step by step. 1. The first layer of photoresist is spun onto the sample. To achieve taller indium bumps, thick positive photoresist AZ P4620 is used in this work. With spin speed at 2000 rpm, 10 lm thick resist can be achieved with a single coat. After spinning, the sample is softbaked for 10 min at 96 C. 2. Flood exposure is performed for the AZ P4620 resist. The UV dosage is 3200 mJ/cm2 (measured at h-line 405 nm). Before the flood exposure, the sample is left in the air for at least 30 min to further remove any solvent from the resist. If too much solvent is left inside the thick photoresist, bubbles will form during the UV flood exposure (due to the heat generated inside the resist by UV light). After this step, the whole layer of AZ P4620 resist achieves a very high dissolution rate inside the developer (AZ 400K in this work) and therefore, a develop-enhanced resist bottom layer is formed. 3. The second layer of photoresist (positive resist AZ 4330) is spun onto the sample. After spinning, the sample is softbaked for 50 s at 96 C. 4. Photolithography is performed on a Karl Suss MJB 3 contact mode mask aligner with a dark field photomask. The exposure dose (150 mJ/ cm2 ) is chosen so that only the top resist layer is fully exposed.
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UV
Fig. 2. Schematic of evaporated indium bump fabrication processing based on positive lithography.
5. Before the resist developing, the sample is soaked in chlorobenzene for 5 m. Chlorobenzene soaking is used to form a develop-inhibited resist top layer. The absorption of the chlorobenzene solvent into the resist results in the extraction of novolak and in turn the unexposed surface region exhibits a reduced develop rate [17–19]. 6. The sample is developed in AZ 400K developer. Due to the combination of a develop-enhanced bottom resist layer and a develop-inhibited resist top layer, very good undercut profiles are created in this double layer of positive resist (shown in Fig. 3). Before any metal evaporation, an O2 plasma cleaning (ashing) is performed on the sample to remove any possible resist residue at the bottom of the resist openings. 7. Three metal layers-Ti/Pt/Au are deposited onto the sample by using an electron-beam evaporator. These metal layers are used as under-bumpmetallurgy (UBM), also known as ball limiting metallurgy (BLM). In solder bump processing, UBM is used to anchor the solder bump to the infrared detector pixels. UBM usually con-
sists of three layers of metal: adhesion layer (Ti), solder diffusion barrier (Pt), and solder wettable layer (Au). 8. Right after UBM evaporation, indium is deposited onto the sample via a thermal evaporator. The sample is water-cooled during the evaporation to avoid excessive heating-up of the photoresist. Some photoresist residue was observed after lift-off for those samples where no water-cooling was applied during the indium evaporation. Another reason for watercooling samples is to achieve well-defined indium bumps. During the long indium evaporation process, the sample could be heated well above indiumÕs melting point of 157 C. In that case, the evaporated indium is in the liquid state and might spread inside the resist mold. 9. Lift-off is performed with AZ 400T stripper. The stripper is heated up to 80 C during the lift-off process. Indium bump reflow can be performed at 200 C inside a hydrogen atmosphere for 20 m. From the authorÕs experience, indium reflow is not absolutely necessary for infrared FPA application.
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Fig. 3. Undercut profile achieved with double positive resist layer.
The above indium bump evaporation method has been used for the fabrication of a QWIP FPA [20]. In our indium bump evaporation method, by adjusting the bottom and top resist thickness, indium bumps as tall as 10 lm can be achieved. The advantage of this unique indium lift-off method is its high resolution since only positive resists are involved. The high resolution is maintained despite the thick layer of resist because only the thin top layer of resist actually defines the pattern. It is the combination of flood exposure, double layered resist, and chlorobenzene soaking creates the strong undercut profile that gives the method its advantages. The techniqueÕs relative simplicity does not require expensive high precision equipment, but still achieves reliable results. Aside from bump creation, the resist preparation technique can be used for metal lift-off in cases where an appropriate photomask for negative lithography is unavailable.
3. Indium bump electroplating technique Electroplating is a popular alternative to the evaporation process because of its overall lower cost. It has been widely used in the integrated circuit (IC) industry for flip-chip bonding applications in which the pitch and bump size are relatively large (100 lm). However, electroplating has not been widely used for fabrication of indium bumps for hybrid infrared FPAs. This may be because of the very small pitch and bump size
necessary for most FPAs and the non-uniformity of bump height in electroplated bumps. The nonuniformity is due to the non-uniform electroplating current density across the wafer. In this paper, we will show that the electroplating method can in fact be used to fabricate small indium bumps with acceptable bump height uniformity for FPA fabrication. The fabrication steps are shown in Fig. 4. Again, only one detector pixel is illustrated in this schematic. The details of this process are given below step by step. 1. After infrared detector fabrication, a dielectric passivation layer is deposited on to the sample by plasma enhanced chemical vapor deposition (PECVD). Passivation material selection is carried out with the goal of minimizing absorption in the detection wavelength range of the infrared detector [21]. Passivation is necessary for electroplated bump fabrication since a blanket metal current path layer will be deposited on the whole surface of sample later. Without a passivation layer, some detector pixels will be shorted by the metal current path layer even though this metal layer is to be removed at the end of bump processing. 2. Contact holes are etched on top of each detector pixel through the passivation layer. This can be done with standard lithography and dry etching techniques. 3. A blanket UBM metal layer is deposited on to the whole sample surface with an electron-beam evaporator. The UBM consists of Ti/Pt/Au. In
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AZ P4620 Passivation layer
(1)
(4)
(7)
Indium bump Contact hole
(2)
(5)
(8)
UBM layer
(3)
(6)
Fig. 4. Schematic of electroplated indium bump fabrication processing.
addition to providing an anchoring function, as in the case of our indium bump evaporation technique, the UBM metal layer here also serves as the current path necessary for the electroplating process. 4. Thick resist AZ P4620 is spun and patterned. The resist thickness is 10 lm. O2 plasma cleaning is performed after resist developing. 5. Indium electroplating is performed inside an indium sulfamate plating bath (supplied by Arconium Corp.) at room temperature. The anode is a pure indium slab. No agitation is applied during the plating. The FPA wafer (square shaped in this work) is connected to the cathode by one of its corners by stripping the photoresist off. An Agilent E3642A DC power supply is used to supply the plating current. To improve bump height uniformity, two measures are taken. First, a small plating current is used. Second, the plating current is applied at each of the four corners of the wafer in sequence so that non-uniformity of current density related to cathode location can be balanced. It was also observed that the largest bump height non-uniformity occurs near the edges of the wafer, so high uniform indium
bumps in central region of wafer can still be achieved after plating. 6. After indium plating, resist is stripped off with AZ 400T stripper. 7. UBM layer is etched off by dry etching. This is performed in an electron cyclotron resonance reactive ion etching (ECR-RIE) reactor with CF4 /H2 gases. 8. Indium bump reflow is performed inside a furnace under H2 atmosphere. Indium bumps as tall as 10 lm have been fabricated with the above electroplating method. The pitch of the indium bumps was 25 lm. As shown in Eq. (2), taller indium bumps always enhance the infrared hybrid FPAÕs long-term reliability. In order to achieve tall indium bumps in small pitch FPAs (e.g. high aspect ratio bumps), a simple technique, the ‘‘multi-stack’’ bump method, was developed based on the above electroplating bump technique. Immediately after the first indium bump plating, another thick resist layer AZ P4620 is spun onto the sample. After resist patterning and developing (Fig. 5a), a second indium electroplating is performed (Fig. 5b). After resist removal (Fig. 5c) and bump reflow (Fig. 5d), 28 lm tall indium bumps with an as-
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(a)
(b)
(c)
(d)
Fig. 5. Schematic of ‘‘multi-stack’’ indium bump electroplating technique. Variable height (shown here) and diameter bumps can be fabricated on the same chip with this technique.
pect ratio of 2 was achieved (see Fig. 6). Theoretically, this technique can be repeated more than twice to create even higher aspect ratio bumps. A major potential advantage of this
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‘‘multi-stack’’ indium bump technique is that it can be used to fabricate variable height (illustrated in Fig. 5) and diameter indium bumps on the same FPA. This capability may be useful for multi-color infrared FPA fabrication and some MEMS applications. In most multi-color FPAs, each pixel has more than one indium bump in order to read out signals simultaneously from each active region [22]. All indium bumps are made on the top of each FPA pixel so that the bumps can have the same top level, which is important for reliable flip-chip bonding. Extra metal interconnections are required to connect each active region to the top of the pixel. This requires extra metallization steps and reduces the real estate that can be used for light coupling grating fabrication. With the ‘‘multi-stack’’ indium bump technique, variable height indium bumps can be fabricated directly at the level of each active region such that the tops of all the indium bumps are still at the same level.
Fig. 6. Side views of indium bumps before and after reflow. (a) Single-stacked bump before reflow; (b) single-stacked bump after reflow, the diameter of the reflowed bump is 11 lm and its aspect ratio is 1; (c) double-stacked bump before reflow; (d) double-stacked bump after reflow, the bump height is 28 lm, the maximum diameter is 14 lm, and the aspect ratio is 2.
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4. A new approach for indium bump fabrication In this section, a new approach for indium bump fabrication is given in order to overcome the drawbacks of both evaporation and electroplating techniques. The major drawback of indium bump evaporation is its high cost due to expensive equipment and expensive wasted indium from excess deposition. For indium bump electroplating, the major drawback is the requirement of depositing and removing a current path metal layer. For hybrid infrared FPA fabrication, flip-chip bonding is the one indispensable step. In the following, a new indium bump fabrication technique is proposed, but no experimentation has been performed yet. The schematic of this process is shown in Fig. 7. 1. Electroplating current path metal layer is deposited on a ‘‘dummy’’ substrate. The key to this step is choosing the right type of metal to form the bonding layer between the ‘‘dummy’’ substrate and the indium bumps. This metal should not oxidize easily. Additionally, this metal should not be wettable to indium (or have a low wettability to indium). Another possible option is to use a conductive ‘‘dummy’’ wafer with low wettability to indium. In this case, an extra bonding layer for the indium bumps is unnecessary. 2. After thick resist patterning and developing, indium plating is performed on the dummy subDummy wafer (1)
(2)
FPA wafer (3) (4)
(5) Fig. 7. Schematic of ‘‘bump transfer’’ technique for low-cost indium bump fabrication.
strate. Indium bump height is controlled by the resist thickness. To achieve high aspect ratio indium bumps or variable height indium bumps, the ‘‘multi-stack’’ technique introduced above can be used. 3. Detector array is fabricated with standard lithography and etching technique. Ohmic contacts are made on top of each detector pixel with either lift-off or etch back technique. The top layer metal contact should use a material which has very good wettability to indium, such as Au. 4. Flip-chip bonding aligner can be used to transfer the indium bumps from the dummy substrate to the FPA substrate. Both the dummy substrate and the FPA substrate need to be heated above indiumÕs melting point under inert atmosphere (such as N2 ). After fine alignment of the flip-chip bonding aligner, a small bonding pressure will be applied first. While keeping the high temperature for both substrates, the vacuum chunk that holds the dummy substrate will be lifted up, pulling the dummy substrate away from the detector array. Due to the large difference of indium bonding energy between the metal on the dummy substrate and the metal on the FPA substrate (e.g. Au), the indium bumps will be transferred from the dummy substrate to the detector array. 5. During the final indium bump reflow, due to the self-alignment, indium bumps will aligned perfectly with ohmic contact on top of each detector pixel. The above indium bump fabrication is similar to the microball mounting method [23], in which premade microsolder balls are mounted on the PBGA package or CSP substrate with a multi-hold vacuum chunk. In that method, microsolder balls are made by melting metal pieces previously prepared to a constant weight with ball size range from 35 to 100 lm. In our indium bump transfer method, much smaller indium bumps (<10 lm) are premade with electroplating. The advantage of our indium bump transfer technique is that the fabrication of the indium bumps and the FPA are separated. The dummy transfer wafer can also be re-used for bump electroplating.
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5. Conclusions In summary, indium bump fabrication based on both evaporation and electroplating method is developed in this paper. Our indium evaporation method is based on a unique positive lithography process and can achieve high resolutions. Our electroplating method can produce acceptably uniform indium bumps suitable for IR FPA applications. This electroplating method can also be extended to produce high aspect ratio indium bumps or even variable height and diameter indium bumps by a new ‘‘multi-stack’’ technique. The fabrication of multi-color infrared FPAs can potentially benefit greatly from this ‘‘multi-stack’’ method. Finally, to further simplify indium bump fabrication and reduce its cost, a promising indium bump transfer technique is proposed in this paper. This technique can be easily adapted to other industry flip-chip bonding applications. References [1] C.A. Kukkonen, S.D. Gunapala, S.V. Bandara, J.K. Liu, J. LIorens, Proc. SPIE 3698 (1999) 706. [2] H. Schneider, M. Walther, C. Sch€ onbein, R. Rehm, J. Fleissner, W. Pleteschen, J. Braunstein, P. Koidl, G. Weimann, J. Ziegler, W. Cabanski, Physica E 7 (2000) 101. [3] S.D. Gunapala, S.V. Bandara, A. Singh, J.K. Liu, S.B. Rafol, E.M. Luong, J.M. Mumolo, N.Q. Tran, J.D. Vincent, C.A. Shott, J. Long, P.D. LeVan, Proc. SPIE 3698 (1999) 687. [4] K. Vural, L.J. Kozlowski, D.E. Cooper, C.A. Chen, G.L. Bostrup, C. Cabelli, J.M. Arias, J. Bajaj, K.W. Hodapp, D.N. Hall, W.E. Kleinhans, G.G. Price, J.A. Pinter, Proc. SPIE 3698 (1999) 24. [5] J. Jiang, C. Jelen, M. Razeghi, G.J. Brown, IEEE Photonics Technol. Lett. 14 (2002) 372.
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