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Formation of ordered pore arrays at the nanoscale by electrochemical etching of n-type silicon
Superlattices and Microstructures 36 (2004) 245–253 www.elsevier.com/locate/superlattices
Formation of ordered pore arrays at the nanoscale by electrochemical etching of n-type silicon X. Badela,∗, R.T. Rajendra Kumarb, P. Kleimannc, J. Linnrosa a Department of Microelectronics and Information Technology, Royal Institute of Technology, Electrum 229,
16440 Kista, Sweden b Atomic Physics Division, Stockholm University, Alba Nova, Roslagstullsbacken 21, 10691 Stockholm, Sweden c LENAC, Université Claude Bernard Lyon-I, 43 bd. du 11 Nov. 1918, 69622 Villeurbanne, France
Available online 15 September 2004
Abstract Electrochemical etching has been studied to structure n-type silicon substrates at the nanoscale. In this work, well-ordered pore arrays with diameters in the range of 150–500 nm and depths up to 50 µm have been fabricated. The pores were successfully formed by anodic etching in (100)oriented n-type silicon wafers of low-resistivity, typically 1 cm, using aqueous hydrofluoric acid solutions. The lithographic step was performed in a thermally grown oxide using a stepper and dry oxide etching technique. Two types of oxide openings and pitch sizes were tested. The smallest oxide opening realised at this stage was 0.5 µm for a pitch of 1 µm. Stable pore formation was obtained and the smallest pore size obtained was about 200 nm with an aspect ratio close to 100. © 2004 Elsevier Ltd. All rights reserved.
1. Introduction Since the discovery of a critical polishing current limiting porous silicon formation to the electropolishing regime [1], silicon electrochemical etching (EE) in hydrofluoric acid solutions (HF) has been developed to form a wide range of structures. Random porous silicon with diameters varying from 1 nm to several µm, or well-organized structures like ∗ Corresponding author. Tel.: +46 8 790 43 53; fax: +46 875 27782.
E-mail address: [email protected] (X. Badel). 0749-6036/$ - see front matter © 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.spmi.2004.08.037
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Fig. 1. Photo-electrochemical etching setup.
pore and pillar arrays were fabricated [2–5]. Both n- and p-type silicon wafers can be etched and several models have been presented, suggesting that electrons shall be injected from the electrolyte into silicon [6–9]. Thus, etching occurs readily in p-type silicon [6] while positive charge carriers have to be generated by external means in n-type silicon [7,10]. In the case of highly-doped n-type silicon, charge transfer can be ascribed to electrical breakdown [9]. For each type of etching, depending on the type and doping of silicon (thus the size of the structures), a new model was presented. Yet, no model has been commonly recognized to account for the whole variety of pore formation. The interest of the present study is on the formation of uniformly spaced pore arrays at the nanoscale, using n-type silicon and backside illumination to photo-generate the carriers needed in the chemical reaction (Fig. 1). In this case, the etching anisotropy may be explained by pore wall passivation via the space charge region. In this model, the electrolyte/silicon interface is considered as a reverse-biased Schottky junction, i.e. with a depleted region at the silicon surface. In the case of a pre-patterned surface, with inverted pyramids for instance, the electric field of the space charge region (SCR) deviates the photo-generated holes to the top of the pyramids where the reaction occurs [7]. It is also believed that the current at the pore tip is equal to the critical polishing current for stable formation of pores. All EE parameters must be well-adjusted in order to obtain these stable conditions. So far, the reported pore diameter ranged from about 500 nm to 100 µm [11,12]. In this paper, we present the formation of pore arrays with diameter of about 200 nm and aspect ratios close to 100. The initial openings are about 500–700 nm large with a pore pitch in the µm range, thus requiring a stepper to perform the lithography. EE enables to considerably reduce the pore diameter from 700 to 200 nm. These pore arrays may find applications as photonic crystals [13], as templates to form arrays of nanotubes [14] and possibly as other new types of devices. The compatibility of EE to silicon technology and the possibility
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Fig. 2. a: Top view of type A sample before EE (the inset shows the cross-section). The dark cross seen in the middle of every circular oxide opening originates from the facets of the inverted pyramids. b: Top view after EE.
of post-treatments (such as oxidation or doping [15]) make these silicon pore arrays very attractive. 2. Experimental Experiments were performed in (100)-oriented n-type silicon wafers of different resistivities (0.1–1 cm, 1–1.5 cm and 20–40 cm). However, the best results were obtained in 0.1–1 and 1–1.5 cm wafers, which were therefore used to study the effect of the EE parameters. First a 250-nm thick oxide was thermally grown at 1000 ◦ C for 10 min. After removal of the oxide at the back side, the front side oxide was used as a photolithographic mask for patterning the surface. A stepper, whose spatial resolution is 500 nm, was used to perform the lithography. Two types of pore arrays are presented here. Type A has pore openings of 700 nm with a pitch of 1.4 µm while type B has pore openings of 500 nm with a pitch of 1 µm. The oxide was etched by reactive ion etching using a CF4 plasma. After stripping the resist, the patterned oxide was finally used as a mask to form inverted pyramids in silicon by KOH etching, as shown in Fig. 2a. Due to EE in HF, the oxide is removed and the pore opening looks like a square, which is the image of the pyramid base (Fig. 2b).
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Electrochemical etching was performed in a cell allowing illumination of the sample backside (Fig. 1). The front side of the sample was always kept in the dark during etching. The electrolyte was prepared by adding hydrofluoric acid to a solution of ethanol and deionized water (1:3). For all experiments the HF concentration was 5.45 wt%. The patterned side of the sample was in contact with the solution. The contact to the sample backside was performed with a metallic ring covered by InGa liquid to ensure a good ohmic contact. The current density was controlled by regulating the illumination intensity of a 20 W halogen lamp. The optimization and the influence of the EE parameters will be discussed in the next section. After EE, the samples were cleaved in order to observe their cross-sections. However, it was particularly difficult to obtain a cut where one single pore could entirely be seen from top to bottom. First, optical microscopy was used to examine the quality of the etching and the global pore shape. Then, scanning electron microscopy (SEM) was used to obtain more details about the structure, such as the pore diameter and the pore depth. Two SEM’s were used: a JEOL JSM-820 and a RAITH150, enabling imaging at the nanoscale. 3. Results-discussion As already mentioned, three resistivities were tested to form the pore arrays of type A and B. Good results were obtained with the 0.1–1 and 1–1.5 cm wafers. Etching of the 20–40 cm samples resulted in large pores, which did not necessarily grow at the predefined pits. Indeed, the space charge region width at 1 V in the 0.1–1, 1–1.5 and 20–40 cm wafers are 130–500 nm, 500–700 nm and 2.5–3.5 µm respectively [16]. Thus, for the 20–40 cm the SCR width is much larger than half the distance between two pores. As the pit size and the pore pitch are too small as compared to the SCR width, the photo-generated holes may be less focussed at the top of the inverted pyramids. However, at lower resistivities (around 1 cm), stable formation of pores is obtained. In the case of the 0.1–1 cm wafers, pores grow normally at the predefined positions but branching (formation of transversal pores due to etching of the pore walls) is observed as a consequence of the too narrow SCR. Fig. 3 shows a pore array of type A formed in a 1–1.5 cm sample under stable conditions. The pores are about 18 µm deep for a diameter near 200 nm, thus with an aspect ratio of 90. The bias of the reference electrode was 0.8 V and the current density was kept at 0.5 mA cm−2 by regulating the lamp power. Assuming that all photo-generated holes are consumed at the pore tips, the current flowing in each pore is about 10 pA, leading to a polishing current of 31 mA cm−2 . The sample was etched during 30 min, yielding an etch rate of 0.6 µm min−1 (a typical value for macropore formation [3]). As can be seen in Fig. 3, the pores tend to get smaller at the bottom with a diameter decreasing from 250 (top) to 150 nm (bottom). Longer etching times were tested in order to get higher aspect ratios. The pores became deeper but the diameters were enlarged at the top and were even thinner at the bottom. For instance, a 1 h etching resulted in a pore depth of about 30 µm and a pore diameter varying from 400 nm at the top to 100–150 nm at the bottom. As the radius of curvature of the pore tips decreases while etching, the electric field at the tip increases and the condition of electrical breakdown (depending on
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Fig. 3. Pore arrays formed under stable conditions in a 1–1.5 cm sample (30 min, 0.8 V, 0.5 mA cm−2 , 5.45 wt%, controlled illumination of a 20 W halogen lamp). a: Gobal view, b: top of the pores, c: pores at half depth, d: bottom of the pores.
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the doping concentration and the radius of curvature) is reached [9]. Charge transfer at the electrolyte/silicon interface is then governed by tunnelling or avalanche multiplication [17], resulting in rather high current density without illumination. This is observed experimentally as the light source turns off at a certain depth and the current starts increasing even though the regulation is set to 0.5 mA cm−2 (constant bias of 0.8 V). As the breakdown voltage is doping dependent, scaling with the depletion width, this phenomenon occurs after 50 min for the 0.1–1 cm wafers and after 75 min for the 1–1.5 cm ones. In a few trials etching was continued at a constant current by regulating the bias but no good pore arrays were obtained. The etch rate was found to decrease with pore depth (or time). A 30, 45 and 60 min long experiments resulted in 15–20, 20–25 and about 30 µm deep pores, respectively. The corresponding average etch rates are then 0.6, 0.55 and 0.5 µm min−1 . This decrease may be due to the participation of photo-generated holes in the pore wall dissolution instead of the pore growth, or may also be due to a limited transport of the electrolyte species into the pores, thus decreasing the critical polishing current. Another experiment, where the current density was first kept constant at 0.5 mA cm−2 and then increased linearly from 0.5 to 0.75 mA cm−2 , was performed in order to accommodate for the decrease of the pore diameter with depth. This type of regulation results in larger pores (∼400 nm) but enables to etch longer (thus deeper) since the radius of the pore tip is now sufficiently large to avoid electrical breakdown. Even though the regulation is not perfectly calibrated yet, it shows that pores as deep as 45–50 µm can be obtained, resulting in aspect ratios above 100. Pores of type B structures were formed with the same parameters except for the current density, which was increased to 0.75 mA cm−2 to account for the change in geometry. Stable formation was obtained. A series of samples was etched to study the dependence of pore formation on applied bias. As opposed to pore formation at the micrometer-scale, where the pore section evolves from a round-shape to a star-like shape [3], no effect could be seen in the top views of these samples. However, as can be seen in Fig. 4a and b, the cross-sectional views indicate a large dependence of the pore shape on applied bias. When a too low bias is applied, the pores are large, shallow and not straight (Fig. 4a). One of the reasons might be that a too low bias does not concentrate all the photo-generated holes to the pore tips. On the other hand, if the applied bias is too high, rather straight pores are formed (still at the predefined positions) but the pore walls are damaged (Fig. 4b). The pore walls are probably etched due to electrical breakdown [9]. In the 1–1.5 cm samples, stable formation was obtained for applied bias varying from 0.8 to 1.5 V while pore wall breakdown appeared at 3 V and above. As can be seen in the inset of Fig. 4a, a thin layer is present on the pore walls. The pore walls are apparently covered with microporous silicon, which could be removed after a short etch in warm KOH. This porous silicon coating could also be removed by oxidation of the layer followed by etching in a hydrofluoric acid solution. The current density is also a critical parameter to adjust. Indeed, when the current density is too high, the reaction is mass-transport limited in the electrolyte and all the holes are not consumed at the pore tips [7]. As a result, part of these holes diffuse in the pore walls and large pores are obtained (Fig. 5a). The current density could be decreased down
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Fig. 4. Dependence of pore formation on applied bias (1–1.5 cm, type A). a: Etching at low bias (30 min, 0.5 V, 0.5 mA cm−2 , 5.45 wt%), b: etching at high bias (30 min, 5 V, 0.5 mA cm−2 , 5.45 wt%).
to 0.25 mA cm−2 and still stable formation of pores was obtained. Experiments of 30 min performed at 0.5, 0.35, 0.25 and 0.15 mA cm−2 showed that the pore depth decreased from 18 µm to a few µm only. Indeed, the decrease of the current density reduces the pore diameter; thus, electrical breakdown conditions are obtained earlier and some of the experiments could not be carried out during 30 min. For instance, under constant current regulation at 0.25 mA cm−2 the illumination intensity is turned off after 27 min. As a result, the pores are 150 nm large and 8–10 µm deep, as shown in Fig. 5b. Etching of non-patterned silicon substrates with a resistivity of 0.1–1 cm indicates that pores as small as 100–150 nm with a pitch of a few hundreds of nm may be fabricated. The formation of well-ordered pore arrays of such dimensions would then require advanced lithographic techniques such as e-beam lithography or nano-imprint [18]. 4. Conclusions Formation of well-ordered pore arrays at the nanoscale has been achieved with diameters as small as 200 nm and aspect ratios close to 100. Such pores were formed by photo-electrochemical etching of n-type silicon with a resistivity of about 1 cm. The applied bias, the current density and the HF concentration were 0.8 V, 0.5 mA cm−2 and 5.45 wt%, respectively. Further reduction of the pore diameter may be achieved by
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Fig. 5. Dependence of pore formation on current density. a: Etching at 1 mA cm−2 (30 min, 0.8 V, 5.45 wt%), b: etching at 0.25 mA cm−2 (30 min, 0.8 V, 5.45 wt%).
starting from smaller pore openings; thus, requiring more advanced photolithographic techniques. Acknowledgments The authors would like to thank the Swedish Council for Strategic Research (SSF) and the European Commission supporting the ‘3D-RID’ project for financial support. Special thanks are also directed to Robert Juhasz, for helping with SEM imaging. References [1] D.R. Turner, J. Electrochem. Soc. 105 (1958) 402. [2] R.L. Smith, J.D. Collins, J. Appl. Phys. 71 (8) (1992) R1.
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[3] V. Lehmann, H. Föll, J. Electrochem. Soc. 137 (2) (1990) 653. [4] P. Kleimann, J. Linnros, R. Juhasz, Appl. Phys. Lett. 79 (11) (2001) 1727. [5] E.J. Teo, M.B.H. Breese, E.P. Tavernier, A.A. Bettiol, F. Watt, M.H. Liu, D.J. Blackwood, Appl. Phys. Lett. 84 (16) (2004) 3202. [6] A. Vyatkin, V. Starkov, J. Electrochem. Soc. 149 (1) (2002) G70. [7] V. Lehmann, J. Electrochem. Soc. 140 (10) (1993) 2836. [8] J. Carstensen, M. Christophersen, H. Föll, Mater. Sci. Eng. B 69–70 (2000) 23. [9] V. Lehmann, R. Stengl, A. Luigart, Mater. Sci. Eng. B 69–70 (2000) 11. [10] X. Badel, J. Linnros, P. Kleimann, Electrochem. Solid State Lett. 6 (6) (2003) C79. [11] H. Föll, M. Christophersen, J. Carstensen, G. Hasse, Mater. Sci. Eng. R 39 (2002) 93. [12] P. Kleimann, J. Linnros, C.S. Petersson, Mater. Sci. Eng. B 69–70 (2000) 29. [13] J. Schilling, F. Muller, S. Matthias, R.B. Wehrspohn, U. Gösele, K. Busch, Appl. Phys. Lett. 78 (9) (2001) 1180. [14] F.D. Morisson, L. Ramsay, J.F. Scott, J. Phys.: Condens. Matter 15 (2003) L527. [15] X. Badel, J. Linnros, M.S. Janson, J. Österman, Nucl. Instrum. Methods A 509 (2003) 96. [16] V. Lehmann, Electrochemistry of Silicon, Wiley-VCH Verlag GmbH, 2002, Silicon conversion table. [17] X.G. Zhang, Electrochemistry of Silicon and Its Oxide, Kluwer Academic/Plenum Publishers, New York, 2001, p. 27. [18] Y. Chen, A. Lebib, S. Li, A. Pépin, D. Peyrade, M. Natali, E. Cambril, Eur. Phys. J. AP. 12 (2000) 223.
Formation of ordered pore arrays at the nanoscale by electrochemical etching of n-type silicon X. Badela,∗, R.T. Rajendra Kumarb, P. Kleimannc, J. Linnrosa a Department of Microelectronics and Information Technology, Royal Institute of Technology, Electrum 229,
16440 Kista, Sweden b Atomic Physics Division, Stockholm University, Alba Nova, Roslagstullsbacken 21, 10691 Stockholm, Sweden c LENAC, Université Claude Bernard Lyon-I, 43 bd. du 11 Nov. 1918, 69622 Villeurbanne, France
Available online 15 September 2004
Abstract Electrochemical etching has been studied to structure n-type silicon substrates at the nanoscale. In this work, well-ordered pore arrays with diameters in the range of 150–500 nm and depths up to 50 µm have been fabricated. The pores were successfully formed by anodic etching in (100)oriented n-type silicon wafers of low-resistivity, typically 1 cm, using aqueous hydrofluoric acid solutions. The lithographic step was performed in a thermally grown oxide using a stepper and dry oxide etching technique. Two types of oxide openings and pitch sizes were tested. The smallest oxide opening realised at this stage was 0.5 µm for a pitch of 1 µm. Stable pore formation was obtained and the smallest pore size obtained was about 200 nm with an aspect ratio close to 100. © 2004 Elsevier Ltd. All rights reserved.
1. Introduction Since the discovery of a critical polishing current limiting porous silicon formation to the electropolishing regime [1], silicon electrochemical etching (EE) in hydrofluoric acid solutions (HF) has been developed to form a wide range of structures. Random porous silicon with diameters varying from 1 nm to several µm, or well-organized structures like ∗ Corresponding author. Tel.: +46 8 790 43 53; fax: +46 875 27782.
E-mail address: [email protected] (X. Badel). 0749-6036/$ - see front matter © 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.spmi.2004.08.037
246
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Fig. 1. Photo-electrochemical etching setup.
pore and pillar arrays were fabricated [2–5]. Both n- and p-type silicon wafers can be etched and several models have been presented, suggesting that electrons shall be injected from the electrolyte into silicon [6–9]. Thus, etching occurs readily in p-type silicon [6] while positive charge carriers have to be generated by external means in n-type silicon [7,10]. In the case of highly-doped n-type silicon, charge transfer can be ascribed to electrical breakdown [9]. For each type of etching, depending on the type and doping of silicon (thus the size of the structures), a new model was presented. Yet, no model has been commonly recognized to account for the whole variety of pore formation. The interest of the present study is on the formation of uniformly spaced pore arrays at the nanoscale, using n-type silicon and backside illumination to photo-generate the carriers needed in the chemical reaction (Fig. 1). In this case, the etching anisotropy may be explained by pore wall passivation via the space charge region. In this model, the electrolyte/silicon interface is considered as a reverse-biased Schottky junction, i.e. with a depleted region at the silicon surface. In the case of a pre-patterned surface, with inverted pyramids for instance, the electric field of the space charge region (SCR) deviates the photo-generated holes to the top of the pyramids where the reaction occurs [7]. It is also believed that the current at the pore tip is equal to the critical polishing current for stable formation of pores. All EE parameters must be well-adjusted in order to obtain these stable conditions. So far, the reported pore diameter ranged from about 500 nm to 100 µm [11,12]. In this paper, we present the formation of pore arrays with diameter of about 200 nm and aspect ratios close to 100. The initial openings are about 500–700 nm large with a pore pitch in the µm range, thus requiring a stepper to perform the lithography. EE enables to considerably reduce the pore diameter from 700 to 200 nm. These pore arrays may find applications as photonic crystals [13], as templates to form arrays of nanotubes [14] and possibly as other new types of devices. The compatibility of EE to silicon technology and the possibility
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247
Fig. 2. a: Top view of type A sample before EE (the inset shows the cross-section). The dark cross seen in the middle of every circular oxide opening originates from the facets of the inverted pyramids. b: Top view after EE.
of post-treatments (such as oxidation or doping [15]) make these silicon pore arrays very attractive. 2. Experimental Experiments were performed in (100)-oriented n-type silicon wafers of different resistivities (0.1–1 cm, 1–1.5 cm and 20–40 cm). However, the best results were obtained in 0.1–1 and 1–1.5 cm wafers, which were therefore used to study the effect of the EE parameters. First a 250-nm thick oxide was thermally grown at 1000 ◦ C for 10 min. After removal of the oxide at the back side, the front side oxide was used as a photolithographic mask for patterning the surface. A stepper, whose spatial resolution is 500 nm, was used to perform the lithography. Two types of pore arrays are presented here. Type A has pore openings of 700 nm with a pitch of 1.4 µm while type B has pore openings of 500 nm with a pitch of 1 µm. The oxide was etched by reactive ion etching using a CF4 plasma. After stripping the resist, the patterned oxide was finally used as a mask to form inverted pyramids in silicon by KOH etching, as shown in Fig. 2a. Due to EE in HF, the oxide is removed and the pore opening looks like a square, which is the image of the pyramid base (Fig. 2b).
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Electrochemical etching was performed in a cell allowing illumination of the sample backside (Fig. 1). The front side of the sample was always kept in the dark during etching. The electrolyte was prepared by adding hydrofluoric acid to a solution of ethanol and deionized water (1:3). For all experiments the HF concentration was 5.45 wt%. The patterned side of the sample was in contact with the solution. The contact to the sample backside was performed with a metallic ring covered by InGa liquid to ensure a good ohmic contact. The current density was controlled by regulating the illumination intensity of a 20 W halogen lamp. The optimization and the influence of the EE parameters will be discussed in the next section. After EE, the samples were cleaved in order to observe their cross-sections. However, it was particularly difficult to obtain a cut where one single pore could entirely be seen from top to bottom. First, optical microscopy was used to examine the quality of the etching and the global pore shape. Then, scanning electron microscopy (SEM) was used to obtain more details about the structure, such as the pore diameter and the pore depth. Two SEM’s were used: a JEOL JSM-820 and a RAITH150, enabling imaging at the nanoscale. 3. Results-discussion As already mentioned, three resistivities were tested to form the pore arrays of type A and B. Good results were obtained with the 0.1–1 and 1–1.5 cm wafers. Etching of the 20–40 cm samples resulted in large pores, which did not necessarily grow at the predefined pits. Indeed, the space charge region width at 1 V in the 0.1–1, 1–1.5 and 20–40 cm wafers are 130–500 nm, 500–700 nm and 2.5–3.5 µm respectively [16]. Thus, for the 20–40 cm the SCR width is much larger than half the distance between two pores. As the pit size and the pore pitch are too small as compared to the SCR width, the photo-generated holes may be less focussed at the top of the inverted pyramids. However, at lower resistivities (around 1 cm), stable formation of pores is obtained. In the case of the 0.1–1 cm wafers, pores grow normally at the predefined positions but branching (formation of transversal pores due to etching of the pore walls) is observed as a consequence of the too narrow SCR. Fig. 3 shows a pore array of type A formed in a 1–1.5 cm sample under stable conditions. The pores are about 18 µm deep for a diameter near 200 nm, thus with an aspect ratio of 90. The bias of the reference electrode was 0.8 V and the current density was kept at 0.5 mA cm−2 by regulating the lamp power. Assuming that all photo-generated holes are consumed at the pore tips, the current flowing in each pore is about 10 pA, leading to a polishing current of 31 mA cm−2 . The sample was etched during 30 min, yielding an etch rate of 0.6 µm min−1 (a typical value for macropore formation [3]). As can be seen in Fig. 3, the pores tend to get smaller at the bottom with a diameter decreasing from 250 (top) to 150 nm (bottom). Longer etching times were tested in order to get higher aspect ratios. The pores became deeper but the diameters were enlarged at the top and were even thinner at the bottom. For instance, a 1 h etching resulted in a pore depth of about 30 µm and a pore diameter varying from 400 nm at the top to 100–150 nm at the bottom. As the radius of curvature of the pore tips decreases while etching, the electric field at the tip increases and the condition of electrical breakdown (depending on
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249
Fig. 3. Pore arrays formed under stable conditions in a 1–1.5 cm sample (30 min, 0.8 V, 0.5 mA cm−2 , 5.45 wt%, controlled illumination of a 20 W halogen lamp). a: Gobal view, b: top of the pores, c: pores at half depth, d: bottom of the pores.
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the doping concentration and the radius of curvature) is reached [9]. Charge transfer at the electrolyte/silicon interface is then governed by tunnelling or avalanche multiplication [17], resulting in rather high current density without illumination. This is observed experimentally as the light source turns off at a certain depth and the current starts increasing even though the regulation is set to 0.5 mA cm−2 (constant bias of 0.8 V). As the breakdown voltage is doping dependent, scaling with the depletion width, this phenomenon occurs after 50 min for the 0.1–1 cm wafers and after 75 min for the 1–1.5 cm ones. In a few trials etching was continued at a constant current by regulating the bias but no good pore arrays were obtained. The etch rate was found to decrease with pore depth (or time). A 30, 45 and 60 min long experiments resulted in 15–20, 20–25 and about 30 µm deep pores, respectively. The corresponding average etch rates are then 0.6, 0.55 and 0.5 µm min−1 . This decrease may be due to the participation of photo-generated holes in the pore wall dissolution instead of the pore growth, or may also be due to a limited transport of the electrolyte species into the pores, thus decreasing the critical polishing current. Another experiment, where the current density was first kept constant at 0.5 mA cm−2 and then increased linearly from 0.5 to 0.75 mA cm−2 , was performed in order to accommodate for the decrease of the pore diameter with depth. This type of regulation results in larger pores (∼400 nm) but enables to etch longer (thus deeper) since the radius of the pore tip is now sufficiently large to avoid electrical breakdown. Even though the regulation is not perfectly calibrated yet, it shows that pores as deep as 45–50 µm can be obtained, resulting in aspect ratios above 100. Pores of type B structures were formed with the same parameters except for the current density, which was increased to 0.75 mA cm−2 to account for the change in geometry. Stable formation was obtained. A series of samples was etched to study the dependence of pore formation on applied bias. As opposed to pore formation at the micrometer-scale, where the pore section evolves from a round-shape to a star-like shape [3], no effect could be seen in the top views of these samples. However, as can be seen in Fig. 4a and b, the cross-sectional views indicate a large dependence of the pore shape on applied bias. When a too low bias is applied, the pores are large, shallow and not straight (Fig. 4a). One of the reasons might be that a too low bias does not concentrate all the photo-generated holes to the pore tips. On the other hand, if the applied bias is too high, rather straight pores are formed (still at the predefined positions) but the pore walls are damaged (Fig. 4b). The pore walls are probably etched due to electrical breakdown [9]. In the 1–1.5 cm samples, stable formation was obtained for applied bias varying from 0.8 to 1.5 V while pore wall breakdown appeared at 3 V and above. As can be seen in the inset of Fig. 4a, a thin layer is present on the pore walls. The pore walls are apparently covered with microporous silicon, which could be removed after a short etch in warm KOH. This porous silicon coating could also be removed by oxidation of the layer followed by etching in a hydrofluoric acid solution. The current density is also a critical parameter to adjust. Indeed, when the current density is too high, the reaction is mass-transport limited in the electrolyte and all the holes are not consumed at the pore tips [7]. As a result, part of these holes diffuse in the pore walls and large pores are obtained (Fig. 5a). The current density could be decreased down
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251
Fig. 4. Dependence of pore formation on applied bias (1–1.5 cm, type A). a: Etching at low bias (30 min, 0.5 V, 0.5 mA cm−2 , 5.45 wt%), b: etching at high bias (30 min, 5 V, 0.5 mA cm−2 , 5.45 wt%).
to 0.25 mA cm−2 and still stable formation of pores was obtained. Experiments of 30 min performed at 0.5, 0.35, 0.25 and 0.15 mA cm−2 showed that the pore depth decreased from 18 µm to a few µm only. Indeed, the decrease of the current density reduces the pore diameter; thus, electrical breakdown conditions are obtained earlier and some of the experiments could not be carried out during 30 min. For instance, under constant current regulation at 0.25 mA cm−2 the illumination intensity is turned off after 27 min. As a result, the pores are 150 nm large and 8–10 µm deep, as shown in Fig. 5b. Etching of non-patterned silicon substrates with a resistivity of 0.1–1 cm indicates that pores as small as 100–150 nm with a pitch of a few hundreds of nm may be fabricated. The formation of well-ordered pore arrays of such dimensions would then require advanced lithographic techniques such as e-beam lithography or nano-imprint [18]. 4. Conclusions Formation of well-ordered pore arrays at the nanoscale has been achieved with diameters as small as 200 nm and aspect ratios close to 100. Such pores were formed by photo-electrochemical etching of n-type silicon with a resistivity of about 1 cm. The applied bias, the current density and the HF concentration were 0.8 V, 0.5 mA cm−2 and 5.45 wt%, respectively. Further reduction of the pore diameter may be achieved by
252
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Fig. 5. Dependence of pore formation on current density. a: Etching at 1 mA cm−2 (30 min, 0.8 V, 5.45 wt%), b: etching at 0.25 mA cm−2 (30 min, 0.8 V, 5.45 wt%).
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