FPGA implementation of IFFT architecture with enhanced pruning algorithm for low power application

Microprocessors and Microsystems 71 (2019) 102840

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Microprocessors and Microsystems journal homepage: www.elsevier.com/locate/micpro

FPGA implementation of IFFT architecture with enhanced pruning algorithm for low power application Abraham Chavacheril Geevarghese a,∗, Madheswaran Muthusamy b a

Department of Electronics and Communication Engineering, Muthayammal Engineering College, Rasipuram - 637408, Tamilnadu, India Centre for Research in Signal and Image Processing, Department of Electronics and Communication Engineering, Muthayammal Engineering College, Rasipuram - 537408, Tamilnadu, India

b

a r t i c l e

i n f o

Article history: Received 31 January 2019 Revised 28 May 2019 Accepted 24 June 2019 Available online 25 June 2019 Keywords: Enhanced pruned algorithm (EPA) Field-programmable gate array (FPGA) Orthogonal frequency division multiplexing (OFDM) Quadrature amplitude modulation (QAM) Filter-bank multi-carrier with offset quadrature amplitude modulation (FBMC/OQAM) Inverse Fast Fourier Transform (IFFT)

a b s t r a c t The improved architecture of IFFT is developed and presented in this paper. Number of arithmetic operation is more in the normal working of conventional Inverse Fast Fourier Transform. An enhanced pruning algorithm is utilized to reduce the number of arithmetic operations in the IFFT architecture. The performance of the improved IFFT architecture is estimated to find its suitability for the low power Wireless communication system. It is implemented in 8-point IFFT architecture using decimation in frequency algorithm using hardware description language. It is implemented in XC7z020clg484-1 from Zynq-70 0 0 family with a frequency of 220 MHz. It is found that the improved IFFT architecture reduces maximum of 40% of the arithmetic operations, which reduces the power consumption by maximum of 10%. Hence the improved IFFT architecture can be used in the signal processing units in wireless application. © 2019 Published by Elsevier B.V.

1. Introduction The developments in the field of wireless communication technology are introducing more challenges and opportunities for the researchers in the recent days. The continuous growth of internet traffic which demands for high transmission rates motivates for the design of various wireless networks. OQAM transmitter is found to play an important role in the wireless communication system to meet the challenges of the future systems. This paper aims to reduce the power and complexity of Inverse Fast Fourier Transform block at wireless communication system. The advancements in VLSI design and signal processing enhances the energy efficiency and reduction in the design complexity in the transmitter. Razavi et al. [1] reported the capacity of OFDM/OQAM with isotropic orthogonal transfer algorithm (IOTA) through information theoretic analysis. The spectral efficiency of developed OFDM/OQAM and conventional OFDM were evaluated. Complexity of the system has to be decreased. Jin et al. [2] presented a design of conjugated transmission scheme for FBMC/OQAM systems with interference cancellation. The intrinsic imaginary interference including the in∗

Corresponding author. E-mail addresses: [email protected] (A.C. Geevarghese), [email protected] (M. Muthusamy). https://doi.org/10.1016/j.micpro.2019.06.010 0141-9331/© 2019 Published by Elsevier B.V.

trinsic inter-symbol and inter-carrier interference were eliminated at the receiver side through linear signal processing operation. The extra linear combination diversity gains were obtained for improving the systematic performance of FBMC/OQAM. The time and frequency localized prototype filter for Offset Quadrature Amplitude Modulation (FBMC/OQAM) with better spectral shape and mobility support was reported by Nadal et al. [3]. The filter exhibited better robustness to several types of channel impairments compared to state-of the-art prototype filters and OFDM modulation. Femenias et al. [4] presented a comprehensive comparison of OFDM and FBMC/OQAM modulation formats in terms of practical network indicators. Extensive numerical results demonstrated the advantages of FBMC/OQAM over OFDM with increased spectral efficiency. A latest method for the channel estimation technique for the OQAM based filter bank multi-carrier (FBMC/OQAM) systems was also presented by Choi et al. [5]. The pilot signals utilized this intrinsic interference for the channel estimation and the reduced complexity and improved power efficiency was seen compared to the conventional auxiliary pilot method. Nguyen et al. [6] presented the frequency sampling equalizer used for the chromatic dispersion compensation where an adaptive maximum likelihood estimator was utilized for the phase noise compensation. The trade-off analysis was also made between chromatic dispersion and phase noise compensation. This was

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illustrated in the case of a terrestrial long-haul FBMC/OQAM transmission system, with 400-kHz laser line-width and a 1000-km optical link. Aminjavaheri et al [7] reported an asymptotic study of the performance of filter bank multicarrier in the context of massive multi-input multi-output. An efficient equalization method presented for the arbitrarily large signal to interference plus noise ratio (SINR) values by increasing the number of base stations (BS) antennas. Caus and Perez-Neira [8] explained the joint design of MIMO precoding and decoding matrices for FBMC/OQAM. The bit error rate was improved than the existing MIMO-FBMC/OQAM Scheme. Hu et al. [9] reported a decomposition design of complex training sequence for an efficient estimation of channel in multiple input Multiple-output filter bank multicarrier (MIMO– FBMC) communications using offset quadrature amplitude modulation (OQAM). Simulation results were validated. Maheswari et al. [10] presented the performance analysis of multicarrier filter bank system with non-linear high power amplifiers for 5 G networks. The impact of non-linear distortion effects were considered in FBMC–OQAM system when the signal is passed through a high power amplifier. Gomes et al. [11] reported the performance and evaluation of FS-FBMC against OFDM for high data rate applications at 60 GHz. An orthogonal frequency division multiplexing (OFDM) model was developed to standardized by IEEE 802.15.3c for 60 GHz efficient data-rate applications. Fuhrwerk and Peissing [12] presented the capacity gains for Single and Multiuser channel adaptive waveforms in FBMC/OQAM systems. The cell- and user-specific channel adaptive waveforms provided a low-complexity system design, which was capable of fighting the interference problem for systems without a cyclic prefix. Nadal et al. [13] explained a lowcomplexity pipelined architecture for FBMC/OQAM Transmitter. A novel pipelined hardware architecture of the transmitter capable of supporting several filter lengths and targeting low complexity was designed. The typical FBMC/OQAM and OFDM implementations were compared. Nam et al. [14] reported a filter bank multicarrier system with two prototype filters for QAM symbols transmission and reception. The transmitter was implemented with individual filtering for even and odd-numbered sub-carrier symbols. The signal-to-interference power ratio and the bit error rate (BER) were evaluated for FBMC/QAM. Moon et al. [15] explained Peak-to-Average-PowerRatio(PAPR) reduction in the FBMC–OQAM System via SegmentBased Optimization. Reduction of power in FBMC/OQAM was numerically evaluated using simulations. Wang et al. [16] presented Hybrid Peak to Average Power Reduction Scheme for FBMC/OQAM Systems based on multi data block partial transmit sequence and tone reservation methods. Multi data scheme provided 0.2 dB peak to average power reduction performance than hybrid power transmit sequence transmit sequence in the simulation results. Chang [17] presented an efficient VLSI architecture of a pipeline fast Fourier transform (FFT) processor capable of producing the normal output order sequence. The normal output order sequence was generated by a sequence conversion method. The power efficient hardware was generated with less number of adders. Power and complexity need to be decreased. Madheswaran et al. [18] reported the power reduction in OQAM transmitter architecture using modified IFFT. The performance of the modified IFFT design and efficiency of the architecture was verified and compared using the hardware description language. Nguyena et al. [19] reported an FFT processor is designed based on the radix 2 decimation in frequency algorithm FPGA. To improve the throughput and reduce the latency in the operation of FFT a modified parallel double path delay commutator architecture radix-2 with continuous dual-input and dual-output streams is proposed. This FFT processor was implemented on a Xilinx Virtex-7 FPGA. The performance of the de-

vice is analyzed in terms of throughput, speed, precision, hardware complexity, and resource utilization. Earlier Hu and Wan [20] reported a novel generic Fast Fourier Transform pruning technique called traced FFT pruning method. The computational complexity and power consumption were compared with traced FFT and conventional FFT. Nadal et al. [21] illustrated the complete design and prototyping flow from algorithm specification to on-board validation and demonstration. The performance of the developed system was compared to the state of art OFDM based system. In this paper pruned IFFT algorithm is enhanced and is evaluated to find the possible application in OQAM transmitter. Pruning method and complexity are needed to be improved. Hu and Wan explained a traced FFT pruning method which saves the computational complexity and power consumption [22]. The average numbers of butterflies are executed in input and output bins of an FFT. This method is extended to arbitrary radix FFT pruning. This input pruning TFFTP to biological sequence is aligned. Salaskar et al. reported a study of an FFT core for various wireless modem, is designed and implemented [23]. The optimization and conversion of C code to hardware is analyzed. The resulting hardware is optimized to IP core available in Xilinx FPGA in terms of hardware requirements. This paper explains the default implementation by Vivado TM HLS which minimizes the resource consumption. It gives high latency and minimal parallelism which generates good results, but need more improvement in power consumption. Sood et al. reported an OFDM transceiver chip is designed by HDL [24]. It is a high level implementation of FFT with high performance which is implemented for OFDM demodulator. The presented work is carried out on Xilinx 14.2 software and functionally checked by Modelsim 10.1b software. These works can be used for Wimax and Wireless with fast computations. The high band width capabilities of OFDM have an advantage on wireless products with many types of networking systems. Dandach and Siohan reported the modulator for the Filter Bank Multi Carrier system with less complexity than the traditional one [25]. IFFTs implemented for the FBMC modulator is a pruned circuit. It gives the advantages to the complex conjugation relations formulating the outputs for the IFFT stage. Relations depend on the delay parameters. When it is even values, IFFT will take the real value as the input. For odd values, there is complex conjugation relation between even and odd indices of the IFFT output. Complexity is higher in this presented method. VLSI implementation of FFT for OFDM applications concentrates on the trivial multiplications in the input stage of IFFT unit and it is replaced by the pass logic which is presented by Arunachalam and Raj [26]. This paper explains about the input stage of DIF-FFT for 8 to 128 points designed with pass logic and multipliers. The number of slices was reduced by 9% and the total power by 6.5% for 64 point FFT in FPGA. It consumed 28% less power and 27% less gates in the same implementation in ASIC. The complexity of the presented technique is high. Minimum bit resolution map of full parallel pipelined FFT/IFFT architectures stage dependent in real time optical orthogonal division multiplexing transceivers as reported by Zhang et al. [27], explains extensive numerical explorations of full parallel pipelined FFT/IFFT. The high accuracy and validity of identified bit resolution map is experimentally verified in FPGA based platforms. The identified bit resolution maps offer an effective approach of selecting minimum bit resolutions for the various FFT/IFFT stages. Accuracy is more in this presented method, but the power consumed is little higher. 2. Enhanced pruned algorithm (EPA) for IFFT The block diagram of FBMC/OQAM is given in Fig. 1. This method of transmission is able to achieve full time/frequency efficiency through the use of Offset Quadrature Amplitude

A.C. Geevarghese and M. Muthusamy / Microprocessors and Microsystems 71 (2019) 102840

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Fig. 1. Block diagram of FBMC/OQAM.

Modulation. Maximum QAM samples are modulated based on the number of active sub-carriers and unused carriers are set to zero. PPN is poly phase network. Polyphase network reconstructs the odd samples from the calculated even samples. In order to reduce the computational complexity, the output indices of the enhanced pruned algorithm with IFFT are applied together with a decimation-in time (DIT) algorithm [28]. The basic computation part of IFFT was done by butterfly method. These arithmetic operators are used for complex computation and twiddle factor calculation. A general N point FFT computes O(N log N) number of operations. The conventional IFFT algorithms were not an efficient method for unwanted operations on zero input values. In general, the system demands operation with high speed and low power consumption for all combination of inputs. Efficiency of the Inverse Fast Fourier Transform technique can be increased by designing the conventional IFFT with enhanced pruning algorithm which is proposed in this paper. The speed of the IFFT is increased by removing few operations of output whose input and output values are zero. Those operations are deprecated for the corresponding inputs in the process of pruning. In the pruning algorithms, the basic concept is used to determine the index of the butterflies to be chosen for computations and those to be discarded. Applications with specific zero-input or zero-output pattern distributions are mostly working with these algorithms. These pruning techniques were added to filter bank system in OQAM transmitter for reducing the operating power and complexity of the system. The N-point Inverse Fast Fourier Transform with 0 ≤ n ≤ N − 1 is given by

x (n ) =

N−1 1  X (k )e j2π kn/N N

(1)

k=0

=

N/2−1 1  X (k )WN−kn N

(2)

m=0

The kernel WN−kn with

{k, n ∈ Z|0 ≤ k, n ≤ N − 1} WN−kn

=e

(3)

− j (2π /N )kn

The Eq. (2) can be decomposed into two sums:

x (n ) =

N/2−1 N/2−1 1  1  X (2m )WN−2mn + X (2m + 1 )WN−n(2m+1) N N m=0

(4)

m=0

Basic butterfly unit for the radix-2 IFFT algorithm is given in Fig. 2. A and B are the inputs and X and Y are outputs of 2-radix IFFT algorithm. The twiddle factor is Wn. The outputs are,

X = A + BWn

(5)

Y = B − BWn

(6)

Fig. 2. Butterfly diagram of radix-2 IFFT.

Fig. 3. Butterfly diagram of 8-point radix-2 IFFT.

Jamil reported algorithms for conversion of complex numbers into complex binary number system (CBNS). Both real and imaginary parts are represented in binary system [22]. Walter Penney presented a binary system for complex numbers. Real and imaginary parts are separated in computer operations when it works with complex numbers as usually and combine them for the final operation [29]. An 8 point radix-2 IFFT butterfly diagram is given in Fig. 3. Frequency domain on the left hand side and time domain at the right hand side of the butterfly diagram. The added result of the dynamic component from charging and discharging the capacitance and static component from the leakage current is comes as the total power consumption.

Ptotal = Pdynamic + Pstatic = ar fcCLV 2 DD + Io f f VDD

(7)

CL load capacitance, VDD supply voltage, Ioff leakage current, fc is the clock frequency and ar is the switching probability called activity ratio. Dynamic power dissipation occurs only when the circuit is in the working mode. i.e. the circuit is executing some task on a set of data. In this paper, an enhanced pruning method is proposed to reduce the dynamic power by reducing the number of switching operations. Number of adders used in each stage of computation is 4. Number of subtractors and multipliers also used in the each stage is 4. Total number of adders, subtractors and multipliers in total stages of operation is 12. Maximum number of computations can be performed by one adder is 4. Maximum number of computations that can be performed by the four adders in the first stage of computation is 16. Maximum number of computation that can be performed by the subtractor and multiplier in each stage is also 16.

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Maximum number of addition operation in the whole 8 point IFFT system is 48. In partial pruning algorithm, whenever the inputs and outputs go to zero, operations for the respective inputs were omitted [20]. The outputs of the nodes are zero, the corresponding input of the dual node pair is zero. The signal flow will automatically follow the next node by avoiding the current operation. So, unnecessary complex calculations are avoided by stopping such unwanted operations by the operators. The total number of complex multiplication and additions are reduced by this partial pruning method. In partial pruning method, number of addition operations is reduced to 12 from actual 16. Likewise number of multiplications and subtractions are also reduced to 12 in each stage. The total number of operations in 8 point IFFT is reduced to 108 from 144. Maximum 36 number of operation are avoided based on the partial pruning method. By omitting the number of operations, power consumption also reduced. Steps followed for Enhanced pruning operation with Subtractor operator in IFFT:Step1: Start Step2: Get input values of 8 point IFFT. Step3: Verify the operation A Step4: If the operation A output is ‘1’ goes to step 5, for ‘0’ go to step 6 Step5: Performing arithmetic operations in the current stage. Step6: Generate output values of the stage 1 and given those values as input to the stage 2. Step7: Verify the operation B Step8: If the operation B output is ‘1’ goes to step 5, for ‘0’ go to step 10 Step9: Performing arithmetic operations in the stage 2. Step10: Generate output values of the stage 2 and given those values as input to the Stage 3. Step11: Verify the operation C Step12: If the operation C output is ‘1’ goes to step 5, for ‘0’ go to step 14 Step13: Performing arithmetic operations in the current stage. Step14: Generate output values of the stage 3 Step 15: Stop Enhanced pruned algorithm for subtractor operator is explained in the flow chart as shown in the Fig. 4. Input values of the IFFT are XORed with an appropriate inputs to check, whether the output is zero or one. If the output of XOR operation is ‘0’, the arithmetic operation for subtractor is bypassed. If the output of XOR operation is ‘1’, the subtractor operation is performed. The outputs after the first stage (0) goes to the next stage (1) where similar operations are carried out for subtractor operator based on the XOR outputs. The output from the stage (1) are passed to the final stage (2) where XOR operation are once again carried out to check ‘0’ or ‘1’ output. After similar operations as explained above in stage (0) the final output of 8 point IFFT is taken. List of verifying conditions are given in the Table 1. When the output of the nodes are zero if the corresponding input of the dual node pair is zero or one, the signal flow will goes to the next node by avoiding the current operation. Like subtraction operators, addition operations are also bypassed by the adder operator for the particular input combination. Addition operations are bypassed for the input combination (0, 0). Adder operator is working with other combination of inputs. Minimum number of additions is reduced to 12 from actual number of operations 16. Operation of multiplier is avoided for the input combination (0, 0). The minimum number of multiplication operations is reduced to 12 from 16 numbers of operations. Minimum number of operations that can be performed during the first stage of 8 point IFFT is 32. Actual number of operations performed with conventional

Fig. 4. Flow chart of enhanced pruned algorithm for subtractor operator in IFFT.

Table 1 List of verifying operations for enhanced pruned algorithm for subtractor operation. Operation

Condition

Operation A

X(0) xor X(4) = 0 or 1 X (1) xor X(5) = 0 or 1 X (2) xor X(6) = 0 or 1 X(3) xor X(7) = 0 or 1

Operation B

g00 g01 g04 g05

xor xor xor xor

g02 g03 g06 g07

= 0 or 1 = 0 or 1 = 0 or 1 = 0 or 1

Operation C

g10 g11 g12 g13

xor xor xor xor

g14 g15 g16 g17

= = = =

0 0 0 0

or or or or

1 1 1 1

IFFT is 48. So, maximum of 16 number of operations are reduced from the actual number of operations using the proposed method. Operation of adder is omitted for the input combination (0, 0) in the second stage of operation. Minimum number of additional operations can be reduced to 12 from actual 16. Two subtraction operations are reduced for the input combination (0, 0) and (1, 1). Minimum number of subtraction operations can be reduced to 8 from 16 during the second stage of operations using the proposed pruning method. Multiplication operation is omitted for the input

A.C. Geevarghese and M. Muthusamy / Microprocessors and Microsystems 71 (2019) 102840

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Fig. 5. Enhanced pruning structure with 8 point IFFT for the input X(k) = “0 0 0 0 0 0 0 0”.

Fig. 6. Enhanced pruned 8 point IFFT architecture for the input X(k) = “0 0 0 0 0 0 01”.

combination (0, 0). Minimum number of multiplication operations can be reduced to 12. Enhanced pruning structure for 8 point IFFT is given in Fig. 5 with input X (k) be “0 0 0 0 0 0 0 0”, all arithmetic operations are bypassed. This pruning operation takes place in all the stages of 8 point IFFT for the corresponding input values. So, this is explained in equation number (15). Here, number of one’s are zero and number of zero’s are eight. 36 number of operations are avoided as per the proposed pruning algorithm. Let X(k) be “0 0 0 0 0 0 01”. Pruning operation is done in 8 point IFFT based on the proposed pruning method. In this combination of inputs seven zeros and one one’s are there. 14 number of operations are executed with the corresponding input data. This can be calculated by the equation no. (14). Total 22 number of operations are excluded for this particular number of inputs. Enhanced pruning algorithm as applied to the input is given in the Fig. 6 which is briefly as

follows. In the first stage of operations, doted lines comprising of squares and rectangles indicates the pruning operation which is going to bypass. These operators include multipliers, adders and subtractors. 3. Analytical study of complexity Maximum number of operations for the enhanced pruned IFFT can be calculated based on the number of one’s and zero’s. Total number of operations in the proposed 8 point IFFT is stated in terms of F(number of one’s, number of zero’s). Number of operations using enhanced pruned IFFT can be determined from the Table 2. For 8 point IFFT, few inputs are shown and given in table out of 256 combinations of inputs.

F (8, 0 ) = 20[X7 X6 X5 X4 X3 X2 X1 X0 ]

(8)

6

A.C. Geevarghese and M. Muthusamy / Microprocessors and Microsystems 71 (2019) 102840 Table 2 Number of operations performed for selected input using Enhanced pruned IFFT algorithm. Input Data X7 X6 X5 X4 X3 X2 X1 X0

Number of operations

00000000 01111111 10111111 11011111 11101111 11110111 11111011 11111101 11111110 11111111

0 29 25 26 23 29 23 29 33 20

⎡

⎤

⎢

⎥

X¯ 7 X¯ 6 X¯ 3 X¯ 1 + X¯ 7 X¯ 6 X¯ 2 X¯ 0 + X¯ 7 X¯ 5 X¯ 4 X¯ 1 + X¯ 7 X¯ 5 X¯ 3 X¯ 0 + X¯ 7 X¯ 4 X¯ 3 X¯ 1

+ 28⎣ + X¯ 6 X¯ 4 X¯ 2 X¯ 1 + X¯ 6 X¯ 4 X¯ 2 X¯ 0 + X¯ 7 X¯ 5 X¯ 4 X¯ 1 + X¯ 7 X¯ 5 X¯ 4 X¯ 2 + X¯ 7 X¯ 6 X¯ 2 X¯ 0 ⎦



+ X¯ 7 X¯ 6 X¯ 4 X¯ 2

+ 24 X¯ 5 X¯ 4 X¯ 3 X¯ 0 + X¯ 7 X¯ 4 X¯ 3 X¯ 2 + X¯ 7 X¯ 2 X¯ 1 X¯ 0 + X¯ 6 X¯ 4 X¯ 3 X¯ 1 + X¯ 7 X¯ 6 X¯ 4 X¯ 1







+ X¯ 5 X¯ 4 X¯ 1 X¯ 1 + 29



+ X¯ 6 X¯ 4 X¯ 3 X¯ 2 + X¯ 6 X¯ 2 X¯ 1 X¯ 0 + X¯ 5 X¯ 4 X¯ 2 X¯ 0 + X¯ 4 X¯ 2 X¯ 1 X¯ 0















+ X¯ 5 X¯ 4 X¯ 3 X¯ 2 + 31 X¯ 6 X¯ 5 X¯ 3 X¯ 1 + X¯ 6 X¯ 4 X¯ 3 X¯ 0 + X¯ 4 X¯ 3 X¯ 2 X¯ 0 + X¯ 4 X¯ 3 X¯ 1 X¯ 0



 

 

+ 26 X5 + 33 X0

(9)

(12)

Eq. (12) is used to find the maximum number operations for the input data, which carries four number of ones and four number of zeros.



F (5, 3 ) = 24 X¯ 2 X¯ 1 X¯ 0 + X¯ 4 X¯ 3 X¯ 0 + X¯ 6 X¯ 5 X¯ 2 + X¯7 X¯3 X¯ 2







+ 23 X¯ 3 X¯ 1 X¯ 0 + X¯ 4 X¯ 3 X¯1 + X¯ 6 X¯ 1 X¯ 0 + X¯ 7 X¯ 5 X¯ 1 + X¯ 7 X¯6 X¯3

F (6, 2 ) = 30 X¯ 7 X¯ 6 + X¯ 7 X¯ 4 + X¯ 7 X¯ 0 + 21 X¯ 7 X¯ 5 + X¯ 5 X¯ 1 + X¯ 2 X¯ 0

+ 28 X¯ 3 X¯ 2 X¯ 1 + X¯5 X¯ 4 X¯ 3 + X¯ 6 X¯ 4 X¯ 1 + X¯ 7 X¯4 X¯1 + X¯ 7 X¯ 5 X¯ 0 + X¯ 7 X¯ 5 X¯ 2



















+ 20 X¯ 7 X¯ 3 + X¯ 4 X¯ 2 + 32 X¯ 7 X¯ 2 + X¯ 4 X¯ 1 + X¯ 3 X¯ 2 + X¯ 3 X¯ 0 + X¯ 1 X¯ 0





+ 28 X¯ 7 X¯ 1 + X¯ 4 X¯ 3 + 25 X¯ 6 X¯ 5 + 19 X¯ 6 X¯ 4































F (5, 3 ) = 28 X¯ 7 X¯ 6 X¯ 5 + X¯ 7 X¯ 5 X¯ 0 + X¯ 6 X¯ 5 X¯ 0 + X¯ 5 X¯ 4 X¯ 3 + X¯ 4 X¯ 3 X¯ 0







+ 25 X¯ 7 X¯ 6 X¯ 4 + X¯ 7 X¯ 6 X¯ 3 + X¯ 7 X¯ 5 X¯ 4 + X¯ 7 X¯ 3 X¯ 1 + X¯ 7 X¯ 3 X¯ 0 + X¯ 5 X¯ 4 X¯ 0 + 31 X¯ 7 X¯ 6 X¯ 1 + X¯ 6 X¯ 5 X¯ 3 + X¯ 5 X¯ 3 X¯ 2 + X¯ 5 X¯ 3 X¯ 0 + X¯ 5 X¯ 2 X¯ 0 + X¯ 4 X¯ 3 X¯ 1 + 32 X¯ 7 X¯ 6 X¯ 0 + X¯ 7 X¯ 4 X¯ 2 + X¯ 7 X¯ 1 X¯ 0 + X¯ 3 X¯ 1 X¯ 0 + X¯ 2 X¯ 16 X¯ 0













+ X¯ 3 X¯ 2 X¯ 0 + 20 X¯ 7 X¯ 5 X¯ 1 + 23 X¯ 7 X¯ 4 X¯ 3 + X¯ 6 X¯ 5 X¯ 4 + X¯ 5 X¯ 4 X¯ 1























+ 21 X¯ 7 X¯ 3 X¯ 2 + 29 X¯ 6 X¯ 4 X¯ 3 + X¯ 5 X¯ 3 X¯ 1 + X¯ 4 X¯ 3 X¯ 1 + 19 X¯ 6 X¯ 4 X¯ 2 + 33 X¯ 6 X¯ 3 X¯ 0 + X¯ 3 X¯ 2 X¯ 1 + 22 X¯ 6 X¯ 2 X¯



Eq. (11) is used to find the maximum number operations for the input data, which carries five number of ones and three number of zeros.



F (4, 4 ) = 22M X¯ 7 X¯ 6 X¯ 5 X¯ 4 + X¯ 5 X¯ 4 X¯ 2 X¯ 1 + X¯ 7 X¯ 3 X¯ 2 X¯ 0 + X¯ 6 X¯ 3 X¯ 2 X¯ 1 + X¯ 5 X¯ 2 X¯ 1 X¯ 0 + 26M X¯ 7 X¯ 6 X¯ 5 X¯ 3 + X¯ 7 X¯ 6 X¯ 5 X¯ 0 + X¯ 6 X¯ 5 X¯ 4 X¯ 2 + X¯ 7 X¯ 6 X¯ 4 X¯ 1 + X¯ 7 X¯ 3 X¯ 1 X¯ 0







+ 21M X¯ 7 X¯ 6 X¯ 5 X¯ 2 + X¯ 6 X¯ 5 X¯ 4 X¯ 3 + X¯ 5 X¯ 4 X¯ 2 X¯ 1 + 27M X¯ 7 X¯ 6 X¯ 5 X¯ 0 + X¯ 7 X¯ 6 X¯ 4 X¯ 0 + X¯ 7 X¯ 6 X¯ 1 X¯ 0 + X¯ 7 X¯ 5 X¯ 1 X¯ 0 + X¯ 7 X¯ 3 X¯ 2 X¯ 1 + X¯ 4 X¯ 3 X¯ 2 X¯ 1







+ 20M X¯ 7 X¯ 6 X¯ 4 X¯ 3 + X¯ 6 X¯ 5 X¯ 4 X¯ 1 + X¯ 5 X¯ 4 X¯ 3 X¯ 0 + 12M X¯ 7 X¯ 6 X¯ 3 X¯ 2







+ 29 X¯ 5 X¯ 3 X¯ 2 + X¯5 X¯ 4 X¯ 2 + X¯ 7 X¯ 6 X¯ 4 + X¯ 7 X¯6 X¯5 + 31 X¯ 7 X¯ 4 X¯ 2 + X¯ 6 X¯ 3 X¯ 0















+ 14 X¯ 6 X¯ 2 X¯ 0 + 18 X¯ 6 X¯ 4 X¯2 + X¯ 6 X¯ 3 X¯ 0 + 32 X¯ 6 X¯ 5 X¯ 3 + 17 X¯ 7 X¯ 3 X¯ 1







+ 25 X¯ 6 X¯ 2 X¯ 1 + X¯7 X¯ 4 X¯ 0 + X¯ 6 X¯ 3 X¯ 1 + 19 X¯ 6 X¯4 X¯ 0







(13)

The maximum number of operations of which input data carries three number of ones and five number of zeros can be determined from Eq. (13).

F (2, 6 ) = 20[X1 X0 ] + 14[X2 X0 + X6 X4 ] + 24[X3 X2 ] + 22[X2 X1 + X3 X0 ] + 16[X3 X1 ] + 17[X4 X2 ] + [X4 X0 + X5 X1 ]



(14)

Equation number (14) states the maximum number of operation that can be performed when the input value includes two number of ones and six number of zeros.



(11)









+ 23[X6 X1 + X7 X0 ] + 10[X6 X2 ] + 15[X7 X1 ] + 12[X7 X3 ]







+ 25[X5 X2 + X6 X3 X7 X3 ] + 19[X5 X3 + X7 X5 ] + 13[X6 X0 ]

+ 30 X¯ 7 X¯ 4 X¯ 1 + X¯ 7 X¯ 2 X¯ 1 + X¯ 6 X¯ 4 X¯ 1 + X¯ 6 X¯ 3 X¯ 1 + X¯ 6 X¯ 1 X¯ 0 + X¯ 5 X¯ 4 X¯ 2 + 27 X¯ 7 X¯ 4 X¯ 0 + X¯ 6 X¯ 3 X¯ 2 + X¯ 5 X¯ 1 X¯ 0 + X¯ 4 X¯ 3 X¯ 2 + X¯ 4 X¯ 1 X¯ 0



+ 21[X4 X1 + X5 X0 ] + 26[X4 X3 + X6 X5 + X5 X4 + X7 X6 ]



+ 24 X¯ 7 X¯ 5 X¯ 3 + X¯ 6 X¯ 3 X¯ 0 + X¯ 4 X¯ 2 X¯ 1 + 34 X¯ 7 X¯ 6 X¯ 2 + X¯ 7 X¯ 2 X¯ 0













+ 21 +X¯5 X¯ 2 X¯ 0 + X¯ 5 X¯ 4 X¯ 1 + X¯ 6 X¯ 3 X¯2 + X¯ 6 X¯ 5 X¯ 1 + X¯ 7 X¯ 1 X¯ 0

Equation number (10) states the maximum number of operations that can be performed when the input value includes six number of ones and two number of zeros.







 (10)









+ 26 X¯ 7 X¯ 6 X¯ 2 + X¯ 6 X¯ 5 X¯ 2 + X¯ 6 X¯ 5 X¯ 1 + X¯ 6 X¯ 2 X¯ 1 + X¯ 5 X¯ 2 X¯ 1



+ 22 +X¯5 X¯ 1 X¯ 0 + X¯ 5 X¯ 2 X¯ 1 + X¯ 5 X¯ 3 X¯ 1 + X¯ 6 X¯ 2 X¯ 1 + X¯ 7 X¯ 4 X¯ 3 + X¯7 X¯ 5 X¯ 3

+ 23 X¯ 6 X¯ 0 + 27 X¯ 5 X¯ 4 + X¯ 3 X¯ 1 + 22 X¯ 4 X¯ 3 + 15 X¯ 5 X¯ 0 + 33 X¯ 2 X¯ 1



+ 27 +X¯7 X¯ 2 X¯ 0 + X¯ 4 X¯ 2 X¯ 1 + 30 X¯ 4 X¯3 X¯1 + X¯ 6 X¯ 4 X¯ 3







+ X¯ 7 X¯ 6 X¯ 0 + X¯ 7 X¯ 6 X¯ 1 + 20 X¯ 4 X¯ 1 X¯ 0 + X¯6 X¯ 5 X¯ 0 + 9 X¯ 4 X¯2 X¯ 0



+ 29 X¯ 6 X¯ 3 + X¯ 5 X¯ 2 + X¯ 5 X¯ 0 + 17 X¯ 6 X¯ 2 + 31 X¯ 6 X¯ 1



+ 26 X¯ 3 X¯ 2 X¯ 0 + X¯ 5 X¯ 3 X¯0 + X¯5 X¯ 4 X¯ 0 + X¯ 6 X¯ 5 X¯ 4 + X¯ 7 X¯ 5 X¯ 4 + X¯ 7 X¯ 6 X¯ 2









The maximum number of operations of which input data carries seven number of ones and one number of zero as shown in the Table 2 can be determined from Eq. (9).







+ 32 X¯ 5 X¯ 3 X¯ 2 X¯ 1 + X¯ 6 X¯ 5 X¯ 3 X¯ 0 + X¯ 6 X¯ 5 X¯ 2 X¯ 0 + 25 X¯ 6 X¯ 5 X¯ 4 X¯ 0 + X¯ 6 X¯ 5 X¯ 1 X¯ 0

F (7, 1 ) = 29 X7 + X3 + X1 + 23 X4 + X2 + 25 X6

 



+ 8 X¯ 7 X¯ 5 X¯ 3 X¯ 1 + 30 X¯ 5 X¯ 4 X¯ 1 X¯ 0 + X¯ 7 X¯ 4 X¯ 2 X¯ 1 + 14 X¯ 7 X¯ 4 X¯ 3 X¯ 0 + X¯ 6 X¯ 5 X¯ 2 X¯ 1

Eq. (8) explains maximum number operations for the input data, which carries eight number of ones and zero number of zeros as shown in the Table 2.



¯ ¯ ¯ ¯ X7 X5 X3 X2 + X¯ 7 X¯ 5 X¯ 2 X¯ 1 + X¯ 7 X¯ 5 X¯ 1 X¯ 0 + X¯ 6 X¯ 5 X¯ 2 X¯ 0









+ 19 X¯ 7 X¯ 5 X¯ 4 X¯ 3 + X¯ 7 X¯ 5 X¯ 4 X¯ 0 + 23 X¯ 7 X¯ 5 X¯ 4 X¯ 2 + X¯ 7 X¯ 4 X¯ 1 X¯ 0 + X¯ 6 X¯ 5 X¯ 4 X¯ 2

+ 34 X¯ 3 X¯ 2 X¯ 1 X¯ 0







F (1, 7 ) = 14X0 + 18X1 + 12X2 + 20X3 + 14X4 + 19X5 + 17X6 + 21X7 (15) The maximum number of operations for which the input data consists of one number of one and seven number of zeros is given in the Eq. (15).

F ( 0, 8 ) = 0

(16)

The maximum number of operations for which the input data consists of zero number ones and eight number of zeros is zero as shown in the Table 2 can be determined from Eq. (16). Complexity comparison based on the analytical study is done in Table 3. IFFT size of M represents 512 and q taps per polyphase network in FBMC/OQAM transmitter. Expressions are written based

A.C. Geevarghese and M. Muthusamy / Microprocessors and Microsystems 71 (2019) 102840

Table 5 Comparison of number of operations in different type of IFFT per various order of IFFT.

Table 3 Complexity Comparison based on Analytical Study. Operation

IFFT [13]

Adders Multipliers

10[log4(M/2)]+4q-4 4[log4(M/2)]+4q

7

Enhanced pruned IFFT method (Proposed)

Order of IFFT

4[log4(M/2)]+4q 3[log4(M/2)]+q

Number of operations Conventional IFFT Partial pruned IFFT Enhanced pruned IFFT

8 16 32 64

on the number of adders and multipliers. These expressions are compared with the operators which are used in the proposed method and the method used in the reference paper. Complexity expression for adders is reduced to half than that of previous technique. Complexity of the multiplier is also reduced. Hence it is observed that total complexity of FBMC/OQAM is reduced by using enhanced pruned IFFT method.

144 384 960 2304

108 288 720 1728

96 248 604 1504

Table 6 Comparison of power consumption. Transmitter Architecture

Power (mW)

Conventional IFFT [13] IFFT using Enhanced Pruned Algorithm (Proposed)

88 78

4. Results and discussion Various 8 point IFFTs are compared in Table 4. Number of operations in addition, subtraction and multiplication is explained in three stages of operation using butterfly diagram. 16 numbers of operations are performed for addition, subtraction and multiplication in conventional IFFT in the first stage. Likewise total of 48 operations are performed in each stage of IFFT. Total of 144 number of operations are performed in the conventional IFFT. In partial pruning operation 48 number of operations in each stage is reduced to 36. So, total operations in three stages are reduced to 108. 40 number of operations are reduced in partial pruning IFFT operation than conventional IFFT. Number of operations in the Enhanced pruned IFFT is reduced to 32 from 48 during the first stage of operation than conventional IFFT. Number of operations are reduced to 32 in the remaining stages of Enhanced pruned IFFT. Total number of operation in the enhanced IFFT is reduced to 96. It is the minimum number of operations in the IFFT with enhanced pruned algorithm. Comparison between the different number of operations of proposed technique with conventional and partial pruned IFFT in different order IFFT is given in Table 5. Total of 144 operations are performed in 8 point IFFT. Number of operation in the partial pruned IFFT in 16 order IFFT is 288. An operation in the proposed technique is reduced to 248. 136 operations are reduced in the proposed technique than conventional IFFT in 16 point IFFT. Maximum of 40% operations are reduced in the proposed technique than conventional IFFT in all order of IFFT. Power consumption for the proposed algorithm with the IFFT is 78 mW. The architecture of the Enhanced pruned IFFTs of these transmitters have been designed in VHDL and synthesized targeting the XC7z020clg484-1 from Zynq-70 0 0 family. Generated results are summarized in Table 5. These results are based on the IFFT size of 512. The complexity will be relatively negligible when the proposed IFFT size is increased. Overall power reduction is done by proposed IFFT with conventional IFFT.

The transmitters are implemented on the ZedBoard using the approach given in [11]. Power consumption generated for the proposed technique is given in the Table 5. Power consumed for the conventional IFFT was 88 mW [13]. Proposed logic generates very less complexity with utilization compared to the last technique which was developed for the IFFT in FBMC/OQAM transmitter. The utilization report was generated by the tool which is used to design the system. Utilization report states that the proposed IFFT used a better number of buffers and I/Os in the device. Proposed algorithm is designed based on the controlled use of the number of operators. Clock frequency used in the proposed algorithm is 220 MHz. Total power consumed for the proposed algorithm is 78 mW as shown in Table 6. Output wave form for the proposed algorithm with 8 point IFFT is given in the Fig. 7, which is generated by the XC7z020clg484-1 device for the proposed algorithm. The proposed algorithm is implemented using hardware description language. So, these wave form values are generated after less number of addition, subtraction and multiplication operations in the device. IFFT design is one of the major parts in the design of FBMC/OQAM transmitter. By reducing the power and complexity of this design, the overall performance of FBMC/OQAM will increase. Overall power consumption will be reduced in the FBMC/OQAM transmitter by this IFFT with the enhanced pruned algorithm. Speed of the system is also increased by reducing the propagation delay between the blocks by bypassing or omitting the number of operators by the enhanced pruned algorithm used in the IFFT design. Output wave form for the proposed algorithm with 8 point IFFT is given in the Fig. 7, which is generated by the XC7z020clg4841 device for the proposed algorithm. The proposed algorithm is implemented using hardware description language. So, these wave form values are generated after less number of addition, subtraction and multiplication operations in the device. IFFT design is one of the major parts in the design of FBMC/OQAM transmitter. By re-

Table 4 Comparison of number of operations in various 8-point IFFT. Stages of IFFT

Operations

Conventional IFFT

Partial pruned IFFT

Enhanced pruned IFFT

Stage 1

Additions Subtractions Multiplications

16 16 16

12 12 12

12 8 12

Stage 2

Additions Subtractions Multiplications

16 16 16

12 12 12

12 8 12

Stage 3

Additions Subtractions Multiplications

16 16 16

12 12 12

12 8 12

8

A.C. Geevarghese and M. Muthusamy / Microprocessors and Microsystems 71 (2019) 102840

Fig. 7. Output waveform of 8-point IFFT using enhanced pruned algorithm.

ducing the power and complexity of this design, the overall performance of FBMC/OQAM will increase. Overall power consumption will be reduced in the FBMC/OQAM transmitter by this IFFT with the enhanced pruned algorithm. Speed of the system is also increased by reducing the propagation delay between the blocks by bypassing or omitting the number of operators by the enhanced pruned algorithm used in the IFFT design. 5. Conclusion In this work, an enhanced pruned algorithm for the FPGA implementation of Inverse Fast Fourier Transform is proposed. These enhanced pruned IFFTs reduce the complexity in the architecture. Number of arithmetical operators in IFFTs was reduced by maximum of 40% using this enhanced pruned algorithm. For comparison purpose, conventional IFFT and some pruned IFFTs have been considered from the previous work. Analytical studies of IFFTs using these algorithms were demonstrated with reduction in complexity and power consumption. Analytical and implementation results for the proposed architecture have demonstrated the reduction in complexity and power consumption which are compared. Power consumption of proposed algorithm is reduced by a maximum of 10% of the conventional IFFT design. These algorithms were implemented using VHDL in XC7z020clg484-1 from Zynq-70 0 0 family with maximum clock frequency of 220 MHz. Behavioral approach of design always leads to reduce the complexity in the design and increase the speed of operation also. Power reports and utilization statements are generated by implementing in the targeting device XC7z020clg484-1 from Zynq-70 0 0 family. Conflict of interest There is no conflict of interest. Supplementary materials Supplementary material associated with this article can be found, in the online version, at doi:10.1016/j.micpro.2019.06.010.

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Abraham C G received B.E. in Electronics and Communication Engineering from Mohammed Sathak Engineering College during 2004 and M.E. in VLSI Design from Karunya University, Tamilnadu, India during 2009. Now he is a Research Scholar in Anna University, Tamilnadu, India. Presently, he is the full time research scholar of Anna University, India.

Dr. M. Madheswaran received PhD degree in Electronics Engineering from IIT, Varanasi, India, in 1999. Earlier, he obtained BE degree from Madurai Kamaraj University, Tamilnadu in 1990 and ME degree from Birla Institute of Technology, Mesra, Ranchi, Inida in 1992, both in Electronics and Communicatrion Engineering. He has authored over 180 research publications in International and National Journals. His areas of interest are theoretical modelling and simulation of nanoelectronics devices, image processing and biosignal processing. He was awarded the Young Scientist Fellowship (YSF) by the State Council for Science and Technology, Tamilnadu, in 1994 and Senior Research Fellowship (SRF) by the Council of Scientific and Industrial Research (CSIR), Govt. of India, in 1996. He has also received Young Scientist Fellowship from SERC, Department of Science and Technology, Govt. of India in 2005. He has guided 43 PhDs in the recent areas of engineering. He has served as Chair of IEEE Council Society Chapters during 2007–2018.