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FPGA implementation of XOR-MUX full adder based DWT for signal processing applications
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FPGA Implementation of XOR-MUX Full Adder based DWT for Signal Processing Applications P Radhakrishnan Research scholar , G Themozhi Professor PII: DOI: Reference:
S0141-9331(19)30481-8 https://doi.org/10.1016/j.micpro.2019.102961 MICPRO 102961
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Microprocessors and Microsystems
Received date: Revised date: Accepted date:
30 September 2019 12 December 2019 18 December 2019
Please cite this article as: P Radhakrishnan Research scholar , G Themozhi Professor , FPGA Implementation of XOR-MUX Full Adder based DWT for Signal Processing Applications, Microprocessors and Microsystems (2019), doi: https://doi.org/10.1016/j.micpro.2019.102961
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FPGA Implementation of XOR-MUX Full Adder based DWT for Signal Processing Applications Radhakrishnan. P
Formatted: Number of columns: 1
Themozhi.G
Research scholar, Dept of ECE Tagore Engineering College [email protected]
Professor, Dept of EEE AMET University, Chennai [email protected]
Abstract- In the recent past there is a rapid development in the field of digital technology especially in signal processing and image processing based applications Excellent performance high speed, compactable in size low power and less delay are the essential needs of the devices used for applications such as signal processing, audio processing and software define radio and so on. Particularly, digital gadgets are prone to have more critical logic size and power consumption and take large area in VLSI Implementation due to arithmetic operations of adders and multiplier designs. Thus priority architecture of Digital Wavelet Transform (DWT) is affected as it comprises a number of Filter banks in level basics, thus all Filter banks have number of adders and multipliers due to coefficient decompositions of low and high pass filters. On this n-size repeated filter logic takes more logic size and power consumption. Here, the proposed work presents a novel approach of DWT by replacing conventional adders and multipliers with XOR-MUX adders and Truncations multipliers thereby reducing the 2n logic size to n-size logic. Finally, the proposed DWT architecture designed in VHDL and also implemented in FPGA XC6SLX9-2TQG144 proved the performance in terms of delay, area and power. Keywords: DWT (Discrete Wavelet Transform), FPGA(Field Programmable Gate Array).
I. INTRODUCTION In the modern digital world there are a range of novelty based gadgets with lot of application oriented domains such as signal processing applications, audio, image and video processing applications, software define radio and so on. In specific, digital gadget based environment of digital signal processing applications have more signal noises, signal interference and fluctuation as it consumes more power and area in hardware implementation; as a result there is a difficulty in the mathematical operations such as additions, subtractions, divisions and multiplication of designs. The recent digital signal processing applications concentrate more on priority in terms of arithmetic operations concerning cryptography application method, 3G, LTE, Tele-Communication, audio and video processing and so on. Since, this digital signal processing applications concerning additions and subtractions are of more priority to reduce signal noise, fluctuation in all type of gadgets, because these addition and subtraction process builds multiplication and division in arithmetic operations. Here, this proposed methodology concentrates on resourceful arithmetic operation with regard to priority method of Digital Wavelet Transform (DWT). This wavelet transform application consists of a number of Filter banks in level basics , thus all Filter banks have number of adders and multipliers due to coefficient decompositions of low and high pass filters, on this n-size repeated filter logic takes more logic size and power consumption. In this, digital signal processing application adders are considered to be the most important in all arithmetic operations as it has many conventional / parallel adders, parallel pre-fix adders such as Ripple carry adder, Carry look-ahead adder, Carry Select adder, Carry Save adder, Carry By-pass adder, Kogge stone adder, Brent-Kung adder, Lander-Fischer adder. Here, the proposed work presents a novel approach of DWT to replace conventional adders and multipliers with XOR-MUX adders and Truncations multipliers, so as to reduce 2n logic size to n-size logic and while comparing this XOR-MUX adder to parallel adders of RCA-BEC full adder it is clear that it has more efficiency concerning area, delay and power. This XOR-MUX adder is used to modify the conventional full adders in Truncated Multipliers, XOR-MUX based Full adders are used to reduces the number of logic gates involved in truncated multiplier reduces output bits, because these truncation multiplier is of the capability to reduce large area in internal and external architecture of FIR Filter using round based technique, which computes the truncation multiplier by adding the two n-bit partial products, this operation of two n-bits, the MSB are the most significant rows and columns with truncated, deleted, rounded and corrected forms in variable method. A normal multiplier of n x n bit computes and gets the weighted sum of output of 2n bits, but a truncation multiplier computes only n-bits, ant it takes less critical path delay, propagation delay and high performance in arithmetic operations. In this paper, our aim is to the design and implement the DWT by using full adder , Truncation Multiplier, FIR Filter, DWT , and finally provide an architecture design of Modified DWT with proven efficiency in terms of area, power and delay
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comparisons. Section II presents the details of XOR-MUX Full adder and RCA-BEC Full adder design. Section III presents the details of Truncation Multiplier design by using XOR-MUX full adder. Section IV gives the details about FIR Filter design with Truncation Multiplier and XOR-MUX full adder. Section V presents the Modified DWT architecture. Section VI presents the FPGA Implementation of Proposed DWT architecture. Section VII presents the result implementation and comparisons of all Adders, Multiplier, FIR and DWT architecture. Section VIII discusses the conclusion of this paper with future scope and further applications. II. XOR MUX & RCA-BEC FULL ADDER DESIGN In an arithmetic addition, operation of full adders has more critical paths and data paths on digital signal processing applications, its core model is used for many arithmetic operations such as multiplications, division, address computation, cache, memory accesses in floating point unit and arithmetic logic units. Here, this paper introduces two successive stages of XOR and Multiplexer based single bit full adder design with less area and power optimization [1]. While, this XOR and Multiplexer based Full adder design is compared to parallel adders of RCA-BEC (Ripple Carry Adder - Binary Excess One Converter) with area, delay and power. Fig.1 shows the proposed architecture of XOR MUX Full adder design while employing the two successive stages of XOR gate for Sum operations and 2:1 non-inverting multiplexer while using for Carry operations, it takes totally 2 logic gates and 1 multiplexer. The truth table of XOR-MUX Full adder design is shown in Table.1.
A Gate level structure of Conventional RCA with BEC adder design is shown in Fig.2. Also, in this Fig XOR, AND, OR, NOT gate based structure are shown, it takes totally 7 logic gate and 1 multiplexer. The truth table of Conventional RCA Based Carry select adder is shown in Table.2.
III. TRUNCATION MULTIPLIER WITH XOR MUX FULL ADDER DESIGN In Digital signal processing application, the multiplier is of the highest priority to reduce the signal noise, fluctuation in all type of gadgets, and it is applied in signal processing , image processing and cryptography method, since all these application methods are of the highest priority in recent technologies such as 3G, LTE, Tele-Communication, audio and video processing and so on. In the recent past, arithmetic operations need more efficient multipliers with accuracy, speed, area and power, in this multiplication process has three main steps such as partial product generation, reduction, final addition, for this multiplication procedure n-bit binary multiplicand by way of an m-bit binary multiplier, m partial products are generated and results are formed in (n + m) bits long.
In this method concerning types of multipliers, we have proposed a novel XOR MUX based truncation multiplier. The goal of this proposed multiplier is to reduced the large area in the architecture of inner and outer architecture using truncated rounded base technique, which is compared by summing up the output of 2n-bit partial products, this operation of 2n-bits, the MSB of rows and columns takes place by means of truncated, deleted and rounding to correction in uneven method. A conventional multiplier of n x n bit computes and gets the sum of output of 2n bits as shown in Fig.3 and a truncated multiplier computes and gets the sum of output of n size bits as shown in Fig.4. A truncated multiplier is a logic size and area efficient multiplier, it is useful to increase the substitution accuracy and reduce the hardware price, since this truncated multiplier helps to produce the output of n-bits from n x n bits of multiplication, it is of less significance, and some of the partial products are removed and also replaced using the technique of deletion, reduction and truncation. In the partial products generation of conventional method will take more number of columns, that are eliminated with regard to the area and power utilization, in this case the delay also decreases while comparing with the conventional operation, but some drawbacks are present in this truncated multiplication, because this multiplier does not concentrate on carry operation, such as addition and carry skip operation, here number of full adders for addition are used, but not implemented in simple and efficient gate level implementation with carry operation to significantly reduce the area, power and delay. In this method, truncated multiplier is entirely planned based on the conventional full adders as shown in Fig.5, these truncation multipliers have the potential to replace MCM multipliers in FIR Filter [2].
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IV. FIR FILTER DESIGN WITH TRUNCATION MULTIPLIER AND XOR MUX FULL ADDER Here, Finite Impulse Response (FIR) is very frequently used to support the Digital Signal Processing (DSP) application for high and low sampling range, impulse response and noise reduction with filtering order and cut-off frequency. FIR filter design has a number of arithmetic operations such as additions, subtractions, multiplications and delayed elements, all these operations require response of coefficient decompositions of high pass, low pass, band pass and band stop filter output. These FIR filters do not compute any rounding error in arithmetic operations and it is inherently stable to produce significant output and it does take maximum value in Nth order impulse response, it can be designed and configured easily with configuration sequence of linear phase coefficient and also application to detect a phase sensitive applications such as mastering, seismology, crossover filter design and data communication. In this methodology, FIR filter meets the coefficient in assured things, which can be suitable with frequency and time domain. The highest disadvantages of FIR filter are large area, and power consumption mostly due to arithmetic operations such as multiplication, addition and subtraction in number of Nth order. For the high performance, Digital signal processing method is used in Multiple Constant Multiplication(MCM) in all parts of arithmetic operations , and it is the same in FIR Filter design which inherently produces a pipelined method of significant computation results and this method of MCM based FIR is formed only in transpose form and it is suitable for large order filter implementation with fixed co-efficient, but it produces large area and power consumptions. In the Fig.6 architecture is notified for the MCM based FIR Filter with contain number of TAP (Multiplier, Delay, Adder), these ordinary MCM multipliers provide the 16-bit output for 8-bit input, these output are provided to the adder, so the adder design takes 16-bit addition [3]. A discrete time filter is implemented in the following equation: 𝑛
y [𝑛] = ∑ x[n − 1] . h[i] 𝑖=0
Where, x[n] is the input signal of FIR filter and y[n] is the output signal of FIR filter and h[n] is the impulse response coefficient of FIR filter design and it is presented in the n form such as H[0], H[1], H[2],.... H[n], it is derived from MATLAB tool with the help of FDA (Filter Design Analysis), and it helps to fix the operation of low pass, high pass, band stop and band pass with the support of cut-off frequency and sampling frequency and filter order. In the proposed system, Digital FIR filter design is modified using XOR MUX adder based Truncated Multiplier, the impulse response contains Nth order of 8-TAP and it uses this FIR filter design, and this multiplier reduces the bit size of adder and delay elements. Fig.7 shows the FIR Filter Design of Truncation Multiplier. V. MODIFIED DWT ARCHITECTURE The Discrete Wavelet Transform is a technique which is used to discrete the experimental signals which is the biggest advantage over other transformations in terms of frequency, time scale and shift, while implementing as an analog filter bank in audio processing, video processing and also in biomedical field, this technique has a large number of applications in every area i.e. science, engineering, mathematics, artificial intelligence and many more [4]. The Discrete Wavelet Transform is a common signal processing method which is used for the multi-resolution analysis of various types of signals. DWT decomposes the input signal into narrow band of the component frequencies and it is represented in the form of approximate and detailed coefficients, while the approximate coefficients correspond to the low-frequency/coarser variation of the signal, the details of coefficients are the higher frequency/finer variations. Since, DWT uses various types of wavelets and scaling functions as the basis for signal decomposition, it chooses an appropriate wavelet function which is essential for an accurate resolution of the signal due to multi-resolution property, and it helps both spectral and temporal information in the signal like FFT. In this proposed method of DWT techniques such as Mallat's algorithm or lifting facilitates low power design. The proposed system distinguishes and segregates the five acoustic signals efficiently. The Mallat's algorithm, is used to implement the wavelet transform, in lower order filters in combination with sub sampling operation to resolve the signal into very narrow frequency bands [5]. These are the advantages in implementing the hardware. However, the wavelet resolved signal is required to be processed further in order to remove the sporadic spikes and noise, which might trigger a false detection. The acoustic signals in the form of wavelet coefficients have certain patterns corresponding to the symptom to be detected [6]. We know that it is possible to represent a signal in terms of various types of absolute and statistical parameters, such as average, variance, and so on.
Fig.8 shows the architecture of Discrete Wavelet Transform, this architecture is designed using 6 filter structure including low pass filter and high pass filter, this decision is taken from coefficient decomposition method using FIR filter design. In this proposed work of DWT, architecture is integrated using FIR filter through Truncation multiplier and XOR-MUX adder with minimum area, critical path, delay and power. The wavelet decomposition coefficients range are shown in Table.2
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These Wavelet Decomposition coefficients are generated from MATLAB with the help of Filter Design Analysis (FDA) tool, here the initial two low pass and high pass filter produce X1, X2 outputs, these outputs are processed by another four filters Y1, Y2, Y3, Y4,respectively. Fig.8, Fig.9, Fig.10, Fig.11, Fig.12, and Fig.13 shows the filter design analysis of DWT Coefficients.
VI. FPGA IMPLEMENTATION OF PROPOSED DWT ARCHITECTURE In this proposed work DWT is implemented in XILINX FPGA S6LX9-2TQG144 using VHDL Language and compared in terms of area, delay and power. Based upon that proposed methodology XOR-MUX full adder is reduced to more logic size compared to parallel adder of RCA-BEC full adder design in Truncation Multiplier, FIR Filter, and DWT Architecture. Fig.15 describes the architecture of the entire design of Hardware implementation in FPGA.
Here, the input is given through UART Interface with regard to switching the input frequency from Digital Control Oscillator with the support of Dock light UART Interface Tool. Baud Rate 9600, Data Bits 8, Parity 0, Stop Bits 1 are used to Send as well as Receive Communications with designed interface code in MAX3232/SO and communicated with RS232 DB-9 Connector. Fig.16 shows the Communication output of UART Interfaces.
Here, the Digital Control Oscillator generates a sine wave signal at different KHz range, these outputs are given as inputs of Discrete Wavelet Transform to obtain the output of DATA_HH, DATA_HL, DATA_LH, DATA_LL, DATA_LOW, DATA_HIGH, these DWT outputs are given to Switch Control, to configure the DAC Interface with the help of Controller. Here, MCP4921 12-Bit DAC interface are configured using SPI Interface. In this case the DAC interface output is checked in Oscilloscope with FPGA Setup. Fig.17 shows the Hardware Implementation of DWT Interface.
VII. RESULTS & COMPARISONS OF ADDERS, MULTIPLIERS, FIR AND DWT The proposed design of, DWT, FIR Filter, Truncation multiplier, Adder are synthesized in XILINX FPGA and Simulated in Modelsim Software. Here the comparisons are made for XOR MUX adder with parallel adders of RCA-BEC full adder. Fig.18 shows the RTL Schematic of XOR-MUX Full adder design, and Fig.19 shows the RTL Schematic of RCA-BEC Full adder design. These two single bit adders are compared in terms of area, power and delay to find the efficiency and Table. 4 shows all the parameters.
Following the adder operation, as a second part Truncation Multiplier is processed which is one of the major element in the proposed DWT architecture, this truncation multiplier is designed using these two adders XOR-MUX based adder and RCA-BEC adder, the parameters of these multipliers are also compared and henceforth proved to be efficient.Fig.20 shows the RTL Schematic of Truncation Multiplier design and Table.5 shows the Comparison of Truncation Multiplier. Following the design of Adder and Truncation Multiplier , subsequent build up of FIR Filter design with these two types of truncation multipliers are done, and finally these parameters are compared to ascertain the efficiency. Fig.21 shows the RTL Schematic of FIR Filter design and Table.6 shows the parameter comparisons of FIR Filter design.
To conclude, a proposed DWT architecture is designed using XOR MUX based Truncation Multiplier and FIR Filter, this proposed work is compared with parallel adders method of RCA-BEC based DWT architecture. The complete architecture is synthesized in Xilinx FPGA and Simulated in Modelsim Software's. Synthesized report of DWT architecture is shown in Fig.22, and RTL Schematic is shown in Fig.23, and Simulation report of proposed DWT architecture is shown in Fig.24. Finally comparison of all the terms of Slice registers, LUT, Occupied Slice, IOB's, Delay, Power is shown in Tabel.7, and comparison chart of the proposed DWT architecture with XOR-MUX DWT and RCA-BEC DWT is shown in Fig.25. Based on this comparison, the proposed XOR-MUX Full adder based DWT architecture is better in all the ways in Digital Signal Processing applications.
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VIII. CONCLUSIONS A novel approach of this paper is presented to reduce the area, occupied slice and delay of DWT architecture using XOR MUX FIR Filter, XOR MUX Truncation Multiplier, XOR-MUX adders. This method reduces the number of logic gates adder design and adder based DWT architecture of Digital Signal processing applications. The proposed method of XOR-MUX Truncation Multiplier has reduced the output size 8 x 8 bits giving 8 bit outputs, and it support to reduce inner and outer architecture of DWT circuits. The comparisons henceforth prove the efficiency in terms of Slice registers, LUT, Occupied Slice, IOB's, Delay. In future, the outcome of this proposed DWT architecture is certain to support all digital processing applications of audio processing, video processing with enhanced performance of minimum area, delay and power.
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Conflict of Interest The comparisons henceforth prove the efficiency in terms of Slice registers, LUT, Occupied Slice, IOB's, Delay. In future, the outcome of this proposed DWT architecture is certain to support all digital processing applications of audio processing, video processing with enhanced performance of minimum area, delay and power.
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IX. REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
[20] [21] [22] [23] [24] [25] [26]
"High Speed Gate Level Synchronous Full Adder Design", Padmanabhan Balasubramanian, Nikos E, Mastorakis, School of Computer Science, University of Manchester, United Kingdom, WSEAS TRANSACTIONS on CIRCUITS and SYSTES. "Design and Implementation of 8x8 Truncated Multiplier of FPGA", suresh R.Rijal (Asst. Prof. KITS Ramtek), Ms. Sharda, G.Mungale, International Journal of Scientific and Research Publications, Volume 3, Issue 3, March 2013. “Survey: Performance Analysis of FIR Filter Design Using Modified Truncation Multiplier with SQRT based Carry Select Adder,” U Penchalaiah, VG Siva Kumar, International Journal of Engineering & Technology, SPC, 7(2.32) (2018) 23-34. " Decomposition of ECG Signals Using Discrete Wavelet Transform for Wolff Parkinson White Syndrome Patients ", Shipra Saraswat, Geetika Srivastava, Sachidanand Shukla, 2016, International Conference on Micro Electrions and Telecommunicaiton,. "An FPGA based Implementation of a Pre-Processing Stages for ECG Signal Analysis Using DWT", EL Mimouni El Hassan, Mohammed Karim, University Sidi Mohammed Ben Abdellah, Fez, Morocco, IEEE, 2014. "Removal of Power line Interference from ECG Signal using FIR, IIR, DWT and NLMS Adaptive Filter", Shubhankar Saxena, Rohan Jais, Malaya Kumar Hota, Internation Conference on Communication and Signal Processing, April 4-6, 2019, India. "Significance of non-local means estimation in DWT based ECG signal denoising", Pratik Singh, Gayadhar Pradhan. "A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications", Basant Kumar Mohanty, Senior Member, IEEE, and Pramod Kumar Meher, Senior Member, 1063-8210 © 2015 IEEE. "High Speed Gate Level Synchronous Full Adder Designs", WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS, PADMANABHAN BALASUBRAMANIAN and NIKOS E. MASTORAKIS, Oxford Road, Manchester M13 9PL, UNITED KINGDOM. "DESIGN OF ADDER / SUBTRACTOR CIRCUITS BASED ON REVERSIBLE GATES", V.Kamalakannan, Shilpakala.V, Ravi.H.N, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 2, Issue 8, August 2013. "Power and Area Efficient Carry Select Adder", 2015 IEEE Recent Advances in Intelligent Computational Systems (RAICS) | 10-12 December 2015 | Trivandrum. "An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term", I-Chyn Wey, Cheng-Chen Ho, Yi-Sheng Lin, and Chien-Chang Peng, Proceedings of the International Multi Conference of Engineers and Computer Science 2012 Vol II. "Designing Efficient Online Testable Reversible Adders With New Reversible Gate", HimanshuThapliyal and A.P Vinod School of Computer Engineering, Nanyang Technological University, Singapore, 2007 IEEE. "Variable Truncated Multiplier with Low Power", AthiraPrasad , Robin Abraham, International Journal Of Engineering And Computer Science ISSN:2319-7242. "On The Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays", Theo Drane, Thomas Rose and George A. Constantinides, 2013, IEEE TRANSACTIONS ON COMPUTERS. "Design of Reversible Adders Using A Novel Reversible BKG Gate", Bhuvana B, KanchanaBhaaskaran V S, 2016 Online International Conference on Green Engineering and Technologies (IC-GET). "A Novel Design of Compact Reversible SG Gate and its Applications", Payal Garg, Sandeep Saini, 2014 International Symposium on Communications and Information Technologies (ISCIT). " Low-Power System for Detection of Symptomatic Patterns in Audio Biological System", S. Himanshu, Markandeya and Kaushik Roy, Fellow, IEEE, IEEE Trans. on Very large scale integration (VLSI) Systems, vol. 24, No.8, AUGUST 2016. pp. 1063-8210. "Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection", H. S. Markandeya, G. Karakonstantis, S. Raghunathan, P. P. Irazoqui, and K. Roy, in Proc. 16th ACM/IEEE Int. Symp. Low Power Electron. Design (ISLPED), Aug. 2010,pp. 301–306. "VLSI design of 1-D DWT architecture with parallel filters", C. Souani, M. Abid, K. Torki, and R. Tourki, Integr. VLSI J., vol. 29, no. 2,pp. 181–207, 2000. Suresh R.Rijal (Asst. Prof. KITS, Ramtek), Ms.Sharda G.Mungale (Asst. Prof. PCEA, Nagpur), "Design and Implementation of 8x8 Truncated Multiplier of FPGA", International Journal of Scientific and Research Publications, Volume 3, Issue 3, March 2013. Hou-Jen Ko and Shen-Fu Hsiao, "Design and Application of Faithfully Rounded and Truncated Multipliers With Combined Deletion, Reduction, Truncation and Rounding, IEEE Transaction on Circuits and System, II.Express Briefs, Vol 58, No.5, May 2011. I-Chyn Wey, Cheng-Chen Ho, Yi-Sheng Lin, and Chien-Chang Peng, An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term, Proceedings of the International Multi Conference of Engineers and Computer Scientists, 2012, Vol II. B.Ramkumar, Harish M Kittur, "Low Power and Area Efficient Carry Select Adder", IEEE Transaction on Very Large Scale Integration (VLSI) Systems, May 2011. "Ms. Anagha U.P, Mr. Pramod P, PG Scholar, LBS College of Engineering, India, "Power and Area Efficient Carry Select Adder", 2015, IEEE Recent Advances in Intelligent Computational Systems, 10-12 December 2015. Soniya, Suresh Kumar, "A Review of Different Type of Multiplier and Multipliers-Accumulator Unit," International Journal of Emerging Trends and Technology in Computer Science, Volume 2, Issue 4, July-August 2013.
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A B
SUM
Cin
0 COUT 1 Figure 1 : Proposed XOR-MUX Full adder
8
A
B
0
RCA
BEC
CIN
SUM
CARRY
Figure 2: Conventional RCA-BEC Full adder
9
A(7:0)
P(15:0)
B(7:0) Figure 3: Block Diagram of Standard 8x8 Multiplier
10
A(7:0)
P(15:8)
B(7:0) Figure 4: Block Diagram of Truncated 8x8 Multiplier
11
A6B1
A6B0 A7B0
A6B2 A7B1
A6B3 A7B2
A6B4 A7B3
A6B5 A7B4
A6B6 A7B5
A6B7 A7B6
A7B7
FA
A5B1
A5B2
FA
FA A4B2
A5B3
FA
FA
A5B4
FA
FA
A4B3
A4B4
FA
FA
A3B3
A3B4
FA A2B4
FA
FA
A5B5
A5B6
FA
FA P15
P14
A5B7
FA
FA
FA
A4B5
A4B6
A4B7
FA
FA
FA
A3B5
A3B6
A3B7
FA
FA
FA
A2B5
A2B6
A2B7
FA
FA
FA
FA
FA
FA
FA
P13
P12
P11
P10
A1B5
A1B6
A1B7
FA
FA
A0B6
A0B7
FA
FA
FA
P9
P8
0
Figure 5 : Architecture of Truncated 8x8 Multiplier
12
X(n)
MCM
H(0)
MCM
H(1)
D
MCM
H(2)
D 16 BIT ADDER
MCM
H(3)
D 16 BIT ADDER
MCM
H(n)
D 16 BIT ADDER
Y(n)
16 BIT ADDER
Figure 6: FIR Filter Design with MCM Multiplier
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X(n)
Truncation
T
Truncation
H(0)
T
H(1)
D
Truncation
T
H(2)
D 8 BIT ADDER
Truncation
T
Truncation H(3)
D 8 BIT ADDER
T
H(n)
D 8 BIT ADDER
Y(n) 8 BIT ADDER
Figure 7 : FIR Filter Design with Truncation Multiplier
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LOW PASS
y1
HIGH PASS
y2
LOW PASS
y3
HIGH PASS
y4
LOW PASS
X[n]
HIGH PASS
Figure 8: DWT architecture
15
Figure 9: Filter design analysis method of X1 Filter - 70 KHz
16
Figure 10 : Filter design analysis method of X2 Filter - 10 KHz
17
Figure 11 : Filter design analysis method of Y1 Filter - 30 KHz
18
Figure 12: Filter design analysis method of Y2 Filter - 40 KHz
19
Figure 13 : Filter design analysis method of Y3 Filter - 60 KHz
20
Figure 14: Filter design analysis method of Y4 Filter - 50 KHz
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DATA_HH
Digital Control Oscillator
FREQ CORRELATION
DATA_HL FILTER DATA DATA_LH
Switch Control
DATA_LL DATA_HIGH
DAC_DATA
SEL
Controller
DATA_LOW
DWT CS
UDATA
SCLK
SDI
TX DATA
DAC INTERFACE
UART INTERFACE
RX DATA
Figure 15: FPGA Implementation of DWT Architecture
22
Figure 16 : UART Interface
23
Figure 17 : Hardware Implementation of DAC Interface
24
Figure 18 : RTL Schematic of XOR-MUX Full Adder
25
Figure 19: RTL Schematic of XOR-MUX Full Adder
26
Figure 20: RTL Schematic of Truncation Multiplier
27
Figure 21 : RTL Schematic of FIR Filter Design
28
Figure 22: Synthesize report of DWT architecture
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Figure 23 : RTL Schematic of Proposed DWT Architecture
30
Figure 24 : Simulation output of DWT
31
Figure 25 : Comparison chart of XOR MUX DWT and RCA-BEC DWT
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Table 1: Truth Table of XOR-MUX Full Adder CIN 0 0 0 0 1 1 1 1
A 0 0 1 1 0 0 1 1
B 0 1 0 1 0 1 0 1
SUM 0 1 1 0 1 0 0 1
COUT 0 0 0 1 0 1 1 1
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Table 2: Truth table for RCA with BEC CSLA RC A CIN 0
BE C CIN 1
A
B
RCA SU M 0
BE C CY 0
BEC SU M 1
CAR RY
SU M
0
RC A CY 0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
1
1
1
0
1
1
1
0
0
1
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
1
1
0
1
1
1
1
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Table 3 : Mapping of DWT Coefficients to Frequency DWT Coefficient X1 X2 Y1 Y2 Y3 Y4
Cut-Off Frequency (fc) 70KHz 10KHz 30KHz 40KHz 60KHz 50KHz
Sampling Frequency (fs) 50KHz 50KHz 50KHz 50KHz 50KHz 50KHz
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Table 3 : Comparisons of Single bit Full adder Design
Single Bit Full Adder Design XOR MUX RCA-BEC 0 0 Slice Registers 1 2 LUT 1 1 Occupied Slice 5 5 IOB 6.110 8.025 Delay(ns) 14 14 Power(mW)
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Table 4 : Comparisons of Truncation Multiplier
Slice Registers LUT Occupied Slice IOB Delay(ns) Power(mW)
Truncation Multiplier XOR MUX 0 66 26 24 24.248 14
RCA-BEC 0 109 44 24 39.289 14
37
Table 5 : Comparison of FIR Filter Design
Slice Registers LUT Occupied Slice IOB Delay(ns) Power(mW)
FIR Filter XOR MUX 147 180 66 18 5.260 14
RCA-BEC 154 283 91 18 21.079 14
38
Table 6 : Comparison Table of DWT Architecture
DWT XOR MUX
RCA-BEC
Slice Registers
696
1001
LUT
1014
1769
Occupied Slice
325
592
IOB
58
58
Delay(ns)
8.981
28.453
Power(mW)
14
14
39
Biography Mr P.Radhakrishnan received his B.E degree from University of Madras, Chennai, India in 2000. He received M.E Degree in Faculty of Information and Communication Engineering, Anna University, Chennai, India in 2006. Presently is pursuing Ph.D in Anna University, Chennai. He is currently working as an Associate professor in Tagore Engineering College holding an experience of 18 years in teaching. He is a life member of IETE. He has published seven papers in reputed journals. His research area is Signal processing, VLSI and Image processing. Dr.G.Themozhi received her M.E degree from University of Madras, Chennai, India in 2001. She received Ph.D Degree in Faculty of Electrical Engineering, Anna University, Chennai, India in 2013. Presently she is working as Professor in the Department of Electrical and Electronics Engineering, AMET University, Chennai. She has 26 years of teaching experience. She is life member of IETE, IE(India) and ISTE. She has published 20 research papers in reputed journals. Her research areas are VLSI, Signal Processing and Power Electronic Converters.
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FPGA Implementation of XOR-MUX Full Adder based DWT for Signal Processing Applications P Radhakrishnan Research scholar , G Themozhi Professor PII: DOI: Reference:
S0141-9331(19)30481-8 https://doi.org/10.1016/j.micpro.2019.102961 MICPRO 102961
To appear in:
Microprocessors and Microsystems
Received date: Revised date: Accepted date:
30 September 2019 12 December 2019 18 December 2019
Please cite this article as: P Radhakrishnan Research scholar , G Themozhi Professor , FPGA Implementation of XOR-MUX Full Adder based DWT for Signal Processing Applications, Microprocessors and Microsystems (2019), doi: https://doi.org/10.1016/j.micpro.2019.102961
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FPGA Implementation of XOR-MUX Full Adder based DWT for Signal Processing Applications Radhakrishnan. P
Formatted: Number of columns: 1
Themozhi.G
Research scholar, Dept of ECE Tagore Engineering College [email protected]
Professor, Dept of EEE AMET University, Chennai [email protected]
Abstract- In the recent past there is a rapid development in the field of digital technology especially in signal processing and image processing based applications Excellent performance high speed, compactable in size low power and less delay are the essential needs of the devices used for applications such as signal processing, audio processing and software define radio and so on. Particularly, digital gadgets are prone to have more critical logic size and power consumption and take large area in VLSI Implementation due to arithmetic operations of adders and multiplier designs. Thus priority architecture of Digital Wavelet Transform (DWT) is affected as it comprises a number of Filter banks in level basics, thus all Filter banks have number of adders and multipliers due to coefficient decompositions of low and high pass filters. On this n-size repeated filter logic takes more logic size and power consumption. Here, the proposed work presents a novel approach of DWT by replacing conventional adders and multipliers with XOR-MUX adders and Truncations multipliers thereby reducing the 2n logic size to n-size logic. Finally, the proposed DWT architecture designed in VHDL and also implemented in FPGA XC6SLX9-2TQG144 proved the performance in terms of delay, area and power. Keywords: DWT (Discrete Wavelet Transform), FPGA(Field Programmable Gate Array).
I. INTRODUCTION In the modern digital world there are a range of novelty based gadgets with lot of application oriented domains such as signal processing applications, audio, image and video processing applications, software define radio and so on. In specific, digital gadget based environment of digital signal processing applications have more signal noises, signal interference and fluctuation as it consumes more power and area in hardware implementation; as a result there is a difficulty in the mathematical operations such as additions, subtractions, divisions and multiplication of designs. The recent digital signal processing applications concentrate more on priority in terms of arithmetic operations concerning cryptography application method, 3G, LTE, Tele-Communication, audio and video processing and so on. Since, this digital signal processing applications concerning additions and subtractions are of more priority to reduce signal noise, fluctuation in all type of gadgets, because these addition and subtraction process builds multiplication and division in arithmetic operations. Here, this proposed methodology concentrates on resourceful arithmetic operation with regard to priority method of Digital Wavelet Transform (DWT). This wavelet transform application consists of a number of Filter banks in level basics , thus all Filter banks have number of adders and multipliers due to coefficient decompositions of low and high pass filters, on this n-size repeated filter logic takes more logic size and power consumption. In this, digital signal processing application adders are considered to be the most important in all arithmetic operations as it has many conventional / parallel adders, parallel pre-fix adders such as Ripple carry adder, Carry look-ahead adder, Carry Select adder, Carry Save adder, Carry By-pass adder, Kogge stone adder, Brent-Kung adder, Lander-Fischer adder. Here, the proposed work presents a novel approach of DWT to replace conventional adders and multipliers with XOR-MUX adders and Truncations multipliers, so as to reduce 2n logic size to n-size logic and while comparing this XOR-MUX adder to parallel adders of RCA-BEC full adder it is clear that it has more efficiency concerning area, delay and power. This XOR-MUX adder is used to modify the conventional full adders in Truncated Multipliers, XOR-MUX based Full adders are used to reduces the number of logic gates involved in truncated multiplier reduces output bits, because these truncation multiplier is of the capability to reduce large area in internal and external architecture of FIR Filter using round based technique, which computes the truncation multiplier by adding the two n-bit partial products, this operation of two n-bits, the MSB are the most significant rows and columns with truncated, deleted, rounded and corrected forms in variable method. A normal multiplier of n x n bit computes and gets the weighted sum of output of 2n bits, but a truncation multiplier computes only n-bits, ant it takes less critical path delay, propagation delay and high performance in arithmetic operations. In this paper, our aim is to the design and implement the DWT by using full adder , Truncation Multiplier, FIR Filter, DWT , and finally provide an architecture design of Modified DWT with proven efficiency in terms of area, power and delay
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comparisons. Section II presents the details of XOR-MUX Full adder and RCA-BEC Full adder design. Section III presents the details of Truncation Multiplier design by using XOR-MUX full adder. Section IV gives the details about FIR Filter design with Truncation Multiplier and XOR-MUX full adder. Section V presents the Modified DWT architecture. Section VI presents the FPGA Implementation of Proposed DWT architecture. Section VII presents the result implementation and comparisons of all Adders, Multiplier, FIR and DWT architecture. Section VIII discusses the conclusion of this paper with future scope and further applications. II. XOR MUX & RCA-BEC FULL ADDER DESIGN In an arithmetic addition, operation of full adders has more critical paths and data paths on digital signal processing applications, its core model is used for many arithmetic operations such as multiplications, division, address computation, cache, memory accesses in floating point unit and arithmetic logic units. Here, this paper introduces two successive stages of XOR and Multiplexer based single bit full adder design with less area and power optimization [1]. While, this XOR and Multiplexer based Full adder design is compared to parallel adders of RCA-BEC (Ripple Carry Adder - Binary Excess One Converter) with area, delay and power. Fig.1 shows the proposed architecture of XOR MUX Full adder design while employing the two successive stages of XOR gate for Sum operations and 2:1 non-inverting multiplexer while using for Carry operations, it takes totally 2 logic gates and 1 multiplexer. The truth table of XOR-MUX Full adder design is shown in Table.1.
A Gate level structure of Conventional RCA with BEC adder design is shown in Fig.2. Also, in this Fig XOR, AND, OR, NOT gate based structure are shown, it takes totally 7 logic gate and 1 multiplexer. The truth table of Conventional RCA Based Carry select adder is shown in Table.2.
III. TRUNCATION MULTIPLIER WITH XOR MUX FULL ADDER DESIGN In Digital signal processing application, the multiplier is of the highest priority to reduce the signal noise, fluctuation in all type of gadgets, and it is applied in signal processing , image processing and cryptography method, since all these application methods are of the highest priority in recent technologies such as 3G, LTE, Tele-Communication, audio and video processing and so on. In the recent past, arithmetic operations need more efficient multipliers with accuracy, speed, area and power, in this multiplication process has three main steps such as partial product generation, reduction, final addition, for this multiplication procedure n-bit binary multiplicand by way of an m-bit binary multiplier, m partial products are generated and results are formed in (n + m) bits long.
In this method concerning types of multipliers, we have proposed a novel XOR MUX based truncation multiplier. The goal of this proposed multiplier is to reduced the large area in the architecture of inner and outer architecture using truncated rounded base technique, which is compared by summing up the output of 2n-bit partial products, this operation of 2n-bits, the MSB of rows and columns takes place by means of truncated, deleted and rounding to correction in uneven method. A conventional multiplier of n x n bit computes and gets the sum of output of 2n bits as shown in Fig.3 and a truncated multiplier computes and gets the sum of output of n size bits as shown in Fig.4. A truncated multiplier is a logic size and area efficient multiplier, it is useful to increase the substitution accuracy and reduce the hardware price, since this truncated multiplier helps to produce the output of n-bits from n x n bits of multiplication, it is of less significance, and some of the partial products are removed and also replaced using the technique of deletion, reduction and truncation. In the partial products generation of conventional method will take more number of columns, that are eliminated with regard to the area and power utilization, in this case the delay also decreases while comparing with the conventional operation, but some drawbacks are present in this truncated multiplication, because this multiplier does not concentrate on carry operation, such as addition and carry skip operation, here number of full adders for addition are used, but not implemented in simple and efficient gate level implementation with carry operation to significantly reduce the area, power and delay. In this method, truncated multiplier is entirely planned based on the conventional full adders as shown in Fig.5, these truncation multipliers have the potential to replace MCM multipliers in FIR Filter [2].
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IV. FIR FILTER DESIGN WITH TRUNCATION MULTIPLIER AND XOR MUX FULL ADDER Here, Finite Impulse Response (FIR) is very frequently used to support the Digital Signal Processing (DSP) application for high and low sampling range, impulse response and noise reduction with filtering order and cut-off frequency. FIR filter design has a number of arithmetic operations such as additions, subtractions, multiplications and delayed elements, all these operations require response of coefficient decompositions of high pass, low pass, band pass and band stop filter output. These FIR filters do not compute any rounding error in arithmetic operations and it is inherently stable to produce significant output and it does take maximum value in Nth order impulse response, it can be designed and configured easily with configuration sequence of linear phase coefficient and also application to detect a phase sensitive applications such as mastering, seismology, crossover filter design and data communication. In this methodology, FIR filter meets the coefficient in assured things, which can be suitable with frequency and time domain. The highest disadvantages of FIR filter are large area, and power consumption mostly due to arithmetic operations such as multiplication, addition and subtraction in number of Nth order. For the high performance, Digital signal processing method is used in Multiple Constant Multiplication(MCM) in all parts of arithmetic operations , and it is the same in FIR Filter design which inherently produces a pipelined method of significant computation results and this method of MCM based FIR is formed only in transpose form and it is suitable for large order filter implementation with fixed co-efficient, but it produces large area and power consumptions. In the Fig.6 architecture is notified for the MCM based FIR Filter with contain number of TAP (Multiplier, Delay, Adder), these ordinary MCM multipliers provide the 16-bit output for 8-bit input, these output are provided to the adder, so the adder design takes 16-bit addition [3]. A discrete time filter is implemented in the following equation: 𝑛
y [𝑛] = ∑ x[n − 1] . h[i] 𝑖=0
Where, x[n] is the input signal of FIR filter and y[n] is the output signal of FIR filter and h[n] is the impulse response coefficient of FIR filter design and it is presented in the n form such as H[0], H[1], H[2],.... H[n], it is derived from MATLAB tool with the help of FDA (Filter Design Analysis), and it helps to fix the operation of low pass, high pass, band stop and band pass with the support of cut-off frequency and sampling frequency and filter order. In the proposed system, Digital FIR filter design is modified using XOR MUX adder based Truncated Multiplier, the impulse response contains Nth order of 8-TAP and it uses this FIR filter design, and this multiplier reduces the bit size of adder and delay elements. Fig.7 shows the FIR Filter Design of Truncation Multiplier. V. MODIFIED DWT ARCHITECTURE The Discrete Wavelet Transform is a technique which is used to discrete the experimental signals which is the biggest advantage over other transformations in terms of frequency, time scale and shift, while implementing as an analog filter bank in audio processing, video processing and also in biomedical field, this technique has a large number of applications in every area i.e. science, engineering, mathematics, artificial intelligence and many more [4]. The Discrete Wavelet Transform is a common signal processing method which is used for the multi-resolution analysis of various types of signals. DWT decomposes the input signal into narrow band of the component frequencies and it is represented in the form of approximate and detailed coefficients, while the approximate coefficients correspond to the low-frequency/coarser variation of the signal, the details of coefficients are the higher frequency/finer variations. Since, DWT uses various types of wavelets and scaling functions as the basis for signal decomposition, it chooses an appropriate wavelet function which is essential for an accurate resolution of the signal due to multi-resolution property, and it helps both spectral and temporal information in the signal like FFT. In this proposed method of DWT techniques such as Mallat's algorithm or lifting facilitates low power design. The proposed system distinguishes and segregates the five acoustic signals efficiently. The Mallat's algorithm, is used to implement the wavelet transform, in lower order filters in combination with sub sampling operation to resolve the signal into very narrow frequency bands [5]. These are the advantages in implementing the hardware. However, the wavelet resolved signal is required to be processed further in order to remove the sporadic spikes and noise, which might trigger a false detection. The acoustic signals in the form of wavelet coefficients have certain patterns corresponding to the symptom to be detected [6]. We know that it is possible to represent a signal in terms of various types of absolute and statistical parameters, such as average, variance, and so on.
Fig.8 shows the architecture of Discrete Wavelet Transform, this architecture is designed using 6 filter structure including low pass filter and high pass filter, this decision is taken from coefficient decomposition method using FIR filter design. In this proposed work of DWT, architecture is integrated using FIR filter through Truncation multiplier and XOR-MUX adder with minimum area, critical path, delay and power. The wavelet decomposition coefficients range are shown in Table.2
3
These Wavelet Decomposition coefficients are generated from MATLAB with the help of Filter Design Analysis (FDA) tool, here the initial two low pass and high pass filter produce X1, X2 outputs, these outputs are processed by another four filters Y1, Y2, Y3, Y4,respectively. Fig.8, Fig.9, Fig.10, Fig.11, Fig.12, and Fig.13 shows the filter design analysis of DWT Coefficients.
VI. FPGA IMPLEMENTATION OF PROPOSED DWT ARCHITECTURE In this proposed work DWT is implemented in XILINX FPGA S6LX9-2TQG144 using VHDL Language and compared in terms of area, delay and power. Based upon that proposed methodology XOR-MUX full adder is reduced to more logic size compared to parallel adder of RCA-BEC full adder design in Truncation Multiplier, FIR Filter, and DWT Architecture. Fig.15 describes the architecture of the entire design of Hardware implementation in FPGA.
Here, the input is given through UART Interface with regard to switching the input frequency from Digital Control Oscillator with the support of Dock light UART Interface Tool. Baud Rate 9600, Data Bits 8, Parity 0, Stop Bits 1 are used to Send as well as Receive Communications with designed interface code in MAX3232/SO and communicated with RS232 DB-9 Connector. Fig.16 shows the Communication output of UART Interfaces.
Here, the Digital Control Oscillator generates a sine wave signal at different KHz range, these outputs are given as inputs of Discrete Wavelet Transform to obtain the output of DATA_HH, DATA_HL, DATA_LH, DATA_LL, DATA_LOW, DATA_HIGH, these DWT outputs are given to Switch Control, to configure the DAC Interface with the help of Controller. Here, MCP4921 12-Bit DAC interface are configured using SPI Interface. In this case the DAC interface output is checked in Oscilloscope with FPGA Setup. Fig.17 shows the Hardware Implementation of DWT Interface.
VII. RESULTS & COMPARISONS OF ADDERS, MULTIPLIERS, FIR AND DWT The proposed design of, DWT, FIR Filter, Truncation multiplier, Adder are synthesized in XILINX FPGA and Simulated in Modelsim Software. Here the comparisons are made for XOR MUX adder with parallel adders of RCA-BEC full adder. Fig.18 shows the RTL Schematic of XOR-MUX Full adder design, and Fig.19 shows the RTL Schematic of RCA-BEC Full adder design. These two single bit adders are compared in terms of area, power and delay to find the efficiency and Table. 4 shows all the parameters.
Following the adder operation, as a second part Truncation Multiplier is processed which is one of the major element in the proposed DWT architecture, this truncation multiplier is designed using these two adders XOR-MUX based adder and RCA-BEC adder, the parameters of these multipliers are also compared and henceforth proved to be efficient.Fig.20 shows the RTL Schematic of Truncation Multiplier design and Table.5 shows the Comparison of Truncation Multiplier. Following the design of Adder and Truncation Multiplier , subsequent build up of FIR Filter design with these two types of truncation multipliers are done, and finally these parameters are compared to ascertain the efficiency. Fig.21 shows the RTL Schematic of FIR Filter design and Table.6 shows the parameter comparisons of FIR Filter design.
To conclude, a proposed DWT architecture is designed using XOR MUX based Truncation Multiplier and FIR Filter, this proposed work is compared with parallel adders method of RCA-BEC based DWT architecture. The complete architecture is synthesized in Xilinx FPGA and Simulated in Modelsim Software's. Synthesized report of DWT architecture is shown in Fig.22, and RTL Schematic is shown in Fig.23, and Simulation report of proposed DWT architecture is shown in Fig.24. Finally comparison of all the terms of Slice registers, LUT, Occupied Slice, IOB's, Delay, Power is shown in Tabel.7, and comparison chart of the proposed DWT architecture with XOR-MUX DWT and RCA-BEC DWT is shown in Fig.25. Based on this comparison, the proposed XOR-MUX Full adder based DWT architecture is better in all the ways in Digital Signal Processing applications.
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VIII. CONCLUSIONS A novel approach of this paper is presented to reduce the area, occupied slice and delay of DWT architecture using XOR MUX FIR Filter, XOR MUX Truncation Multiplier, XOR-MUX adders. This method reduces the number of logic gates adder design and adder based DWT architecture of Digital Signal processing applications. The proposed method of XOR-MUX Truncation Multiplier has reduced the output size 8 x 8 bits giving 8 bit outputs, and it support to reduce inner and outer architecture of DWT circuits. The comparisons henceforth prove the efficiency in terms of Slice registers, LUT, Occupied Slice, IOB's, Delay. In future, the outcome of this proposed DWT architecture is certain to support all digital processing applications of audio processing, video processing with enhanced performance of minimum area, delay and power.
5
Conflict of Interest The comparisons henceforth prove the efficiency in terms of Slice registers, LUT, Occupied Slice, IOB's, Delay. In future, the outcome of this proposed DWT architecture is certain to support all digital processing applications of audio processing, video processing with enhanced performance of minimum area, delay and power.
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IX. REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
[20] [21] [22] [23] [24] [25] [26]
"High Speed Gate Level Synchronous Full Adder Design", Padmanabhan Balasubramanian, Nikos E, Mastorakis, School of Computer Science, University of Manchester, United Kingdom, WSEAS TRANSACTIONS on CIRCUITS and SYSTES. "Design and Implementation of 8x8 Truncated Multiplier of FPGA", suresh R.Rijal (Asst. Prof. KITS Ramtek), Ms. Sharda, G.Mungale, International Journal of Scientific and Research Publications, Volume 3, Issue 3, March 2013. “Survey: Performance Analysis of FIR Filter Design Using Modified Truncation Multiplier with SQRT based Carry Select Adder,” U Penchalaiah, VG Siva Kumar, International Journal of Engineering & Technology, SPC, 7(2.32) (2018) 23-34. " Decomposition of ECG Signals Using Discrete Wavelet Transform for Wolff Parkinson White Syndrome Patients ", Shipra Saraswat, Geetika Srivastava, Sachidanand Shukla, 2016, International Conference on Micro Electrions and Telecommunicaiton,. "An FPGA based Implementation of a Pre-Processing Stages for ECG Signal Analysis Using DWT", EL Mimouni El Hassan, Mohammed Karim, University Sidi Mohammed Ben Abdellah, Fez, Morocco, IEEE, 2014. "Removal of Power line Interference from ECG Signal using FIR, IIR, DWT and NLMS Adaptive Filter", Shubhankar Saxena, Rohan Jais, Malaya Kumar Hota, Internation Conference on Communication and Signal Processing, April 4-6, 2019, India. "Significance of non-local means estimation in DWT based ECG signal denoising", Pratik Singh, Gayadhar Pradhan. "A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications", Basant Kumar Mohanty, Senior Member, IEEE, and Pramod Kumar Meher, Senior Member, 1063-8210 © 2015 IEEE. "High Speed Gate Level Synchronous Full Adder Designs", WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS, PADMANABHAN BALASUBRAMANIAN and NIKOS E. MASTORAKIS, Oxford Road, Manchester M13 9PL, UNITED KINGDOM. "DESIGN OF ADDER / SUBTRACTOR CIRCUITS BASED ON REVERSIBLE GATES", V.Kamalakannan, Shilpakala.V, Ravi.H.N, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 2, Issue 8, August 2013. "Power and Area Efficient Carry Select Adder", 2015 IEEE Recent Advances in Intelligent Computational Systems (RAICS) | 10-12 December 2015 | Trivandrum. "An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term", I-Chyn Wey, Cheng-Chen Ho, Yi-Sheng Lin, and Chien-Chang Peng, Proceedings of the International Multi Conference of Engineers and Computer Science 2012 Vol II. "Designing Efficient Online Testable Reversible Adders With New Reversible Gate", HimanshuThapliyal and A.P Vinod School of Computer Engineering, Nanyang Technological University, Singapore, 2007 IEEE. "Variable Truncated Multiplier with Low Power", AthiraPrasad , Robin Abraham, International Journal Of Engineering And Computer Science ISSN:2319-7242. "On The Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays", Theo Drane, Thomas Rose and George A. Constantinides, 2013, IEEE TRANSACTIONS ON COMPUTERS. "Design of Reversible Adders Using A Novel Reversible BKG Gate", Bhuvana B, KanchanaBhaaskaran V S, 2016 Online International Conference on Green Engineering and Technologies (IC-GET). "A Novel Design of Compact Reversible SG Gate and its Applications", Payal Garg, Sandeep Saini, 2014 International Symposium on Communications and Information Technologies (ISCIT). " Low-Power System for Detection of Symptomatic Patterns in Audio Biological System", S. Himanshu, Markandeya and Kaushik Roy, Fellow, IEEE, IEEE Trans. on Very large scale integration (VLSI) Systems, vol. 24, No.8, AUGUST 2016. pp. 1063-8210. "Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection", H. S. Markandeya, G. Karakonstantis, S. Raghunathan, P. P. Irazoqui, and K. Roy, in Proc. 16th ACM/IEEE Int. Symp. Low Power Electron. Design (ISLPED), Aug. 2010,pp. 301–306. "VLSI design of 1-D DWT architecture with parallel filters", C. Souani, M. Abid, K. Torki, and R. Tourki, Integr. VLSI J., vol. 29, no. 2,pp. 181–207, 2000. Suresh R.Rijal (Asst. Prof. KITS, Ramtek), Ms.Sharda G.Mungale (Asst. Prof. PCEA, Nagpur), "Design and Implementation of 8x8 Truncated Multiplier of FPGA", International Journal of Scientific and Research Publications, Volume 3, Issue 3, March 2013. Hou-Jen Ko and Shen-Fu Hsiao, "Design and Application of Faithfully Rounded and Truncated Multipliers With Combined Deletion, Reduction, Truncation and Rounding, IEEE Transaction on Circuits and System, II.Express Briefs, Vol 58, No.5, May 2011. I-Chyn Wey, Cheng-Chen Ho, Yi-Sheng Lin, and Chien-Chang Peng, An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term, Proceedings of the International Multi Conference of Engineers and Computer Scientists, 2012, Vol II. B.Ramkumar, Harish M Kittur, "Low Power and Area Efficient Carry Select Adder", IEEE Transaction on Very Large Scale Integration (VLSI) Systems, May 2011. "Ms. Anagha U.P, Mr. Pramod P, PG Scholar, LBS College of Engineering, India, "Power and Area Efficient Carry Select Adder", 2015, IEEE Recent Advances in Intelligent Computational Systems, 10-12 December 2015. Soniya, Suresh Kumar, "A Review of Different Type of Multiplier and Multipliers-Accumulator Unit," International Journal of Emerging Trends and Technology in Computer Science, Volume 2, Issue 4, July-August 2013.
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A B
SUM
Cin
0 COUT 1 Figure 1 : Proposed XOR-MUX Full adder
8
A
B
0
RCA
BEC
CIN
SUM
CARRY
Figure 2: Conventional RCA-BEC Full adder
9
A(7:0)
P(15:0)
B(7:0) Figure 3: Block Diagram of Standard 8x8 Multiplier
10
A(7:0)
P(15:8)
B(7:0) Figure 4: Block Diagram of Truncated 8x8 Multiplier
11
A6B1
A6B0 A7B0
A6B2 A7B1
A6B3 A7B2
A6B4 A7B3
A6B5 A7B4
A6B6 A7B5
A6B7 A7B6
A7B7
FA
A5B1
A5B2
FA
FA A4B2
A5B3
FA
FA
A5B4
FA
FA
A4B3
A4B4
FA
FA
A3B3
A3B4
FA A2B4
FA
FA
A5B5
A5B6
FA
FA P15
P14
A5B7
FA
FA
FA
A4B5
A4B6
A4B7
FA
FA
FA
A3B5
A3B6
A3B7
FA
FA
FA
A2B5
A2B6
A2B7
FA
FA
FA
FA
FA
FA
FA
P13
P12
P11
P10
A1B5
A1B6
A1B7
FA
FA
A0B6
A0B7
FA
FA
FA
P9
P8
0
Figure 5 : Architecture of Truncated 8x8 Multiplier
12
X(n)
MCM
H(0)
MCM
H(1)
D
MCM
H(2)
D 16 BIT ADDER
MCM
H(3)
D 16 BIT ADDER
MCM
H(n)
D 16 BIT ADDER
Y(n)
16 BIT ADDER
Figure 6: FIR Filter Design with MCM Multiplier
13
X(n)
Truncation
T
Truncation
H(0)
T
H(1)
D
Truncation
T
H(2)
D 8 BIT ADDER
Truncation
T
Truncation H(3)
D 8 BIT ADDER
T
H(n)
D 8 BIT ADDER
Y(n) 8 BIT ADDER
Figure 7 : FIR Filter Design with Truncation Multiplier
14
LOW PASS
y1
HIGH PASS
y2
LOW PASS
y3
HIGH PASS
y4
LOW PASS
X[n]
HIGH PASS
Figure 8: DWT architecture
15
Figure 9: Filter design analysis method of X1 Filter - 70 KHz
16
Figure 10 : Filter design analysis method of X2 Filter - 10 KHz
17
Figure 11 : Filter design analysis method of Y1 Filter - 30 KHz
18
Figure 12: Filter design analysis method of Y2 Filter - 40 KHz
19
Figure 13 : Filter design analysis method of Y3 Filter - 60 KHz
20
Figure 14: Filter design analysis method of Y4 Filter - 50 KHz
21
DATA_HH
Digital Control Oscillator
FREQ CORRELATION
DATA_HL FILTER DATA DATA_LH
Switch Control
DATA_LL DATA_HIGH
DAC_DATA
SEL
Controller
DATA_LOW
DWT CS
UDATA
SCLK
SDI
TX DATA
DAC INTERFACE
UART INTERFACE
RX DATA
Figure 15: FPGA Implementation of DWT Architecture
22
Figure 16 : UART Interface
23
Figure 17 : Hardware Implementation of DAC Interface
24
Figure 18 : RTL Schematic of XOR-MUX Full Adder
25
Figure 19: RTL Schematic of XOR-MUX Full Adder
26
Figure 20: RTL Schematic of Truncation Multiplier
27
Figure 21 : RTL Schematic of FIR Filter Design
28
Figure 22: Synthesize report of DWT architecture
29
Figure 23 : RTL Schematic of Proposed DWT Architecture
30
Figure 24 : Simulation output of DWT
31
Figure 25 : Comparison chart of XOR MUX DWT and RCA-BEC DWT
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Table 1: Truth Table of XOR-MUX Full Adder CIN 0 0 0 0 1 1 1 1
A 0 0 1 1 0 0 1 1
B 0 1 0 1 0 1 0 1
SUM 0 1 1 0 1 0 0 1
COUT 0 0 0 1 0 1 1 1
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Table 2: Truth table for RCA with BEC CSLA RC A CIN 0
BE C CIN 1
A
B
RCA SU M 0
BE C CY 0
BEC SU M 1
CAR RY
SU M
0
RC A CY 0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
1
1
1
0
1
1
1
0
0
1
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
1
1
0
1
1
1
1
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Table 3 : Mapping of DWT Coefficients to Frequency DWT Coefficient X1 X2 Y1 Y2 Y3 Y4
Cut-Off Frequency (fc) 70KHz 10KHz 30KHz 40KHz 60KHz 50KHz
Sampling Frequency (fs) 50KHz 50KHz 50KHz 50KHz 50KHz 50KHz
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Table 3 : Comparisons of Single bit Full adder Design
Single Bit Full Adder Design XOR MUX RCA-BEC 0 0 Slice Registers 1 2 LUT 1 1 Occupied Slice 5 5 IOB 6.110 8.025 Delay(ns) 14 14 Power(mW)
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Table 4 : Comparisons of Truncation Multiplier
Slice Registers LUT Occupied Slice IOB Delay(ns) Power(mW)
Truncation Multiplier XOR MUX 0 66 26 24 24.248 14
RCA-BEC 0 109 44 24 39.289 14
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Table 5 : Comparison of FIR Filter Design
Slice Registers LUT Occupied Slice IOB Delay(ns) Power(mW)
FIR Filter XOR MUX 147 180 66 18 5.260 14
RCA-BEC 154 283 91 18 21.079 14
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Table 6 : Comparison Table of DWT Architecture
DWT XOR MUX
RCA-BEC
Slice Registers
696
1001
LUT
1014
1769
Occupied Slice
325
592
IOB
58
58
Delay(ns)
8.981
28.453
Power(mW)
14
14
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Biography Mr P.Radhakrishnan received his B.E degree from University of Madras, Chennai, India in 2000. He received M.E Degree in Faculty of Information and Communication Engineering, Anna University, Chennai, India in 2006. Presently is pursuing Ph.D in Anna University, Chennai. He is currently working as an Associate professor in Tagore Engineering College holding an experience of 18 years in teaching. He is a life member of IETE. He has published seven papers in reputed journals. His research area is Signal processing, VLSI and Image processing. Dr.G.Themozhi received her M.E degree from University of Madras, Chennai, India in 2001. She received Ph.D Degree in Faculty of Electrical Engineering, Anna University, Chennai, India in 2013. Presently she is working as Professor in the Department of Electrical and Electronics Engineering, AMET University, Chennai. She has 26 years of teaching experience. She is life member of IETE, IE(India) and ISTE. She has published 20 research papers in reputed journals. Her research areas are VLSI, Signal Processing and Power Electronic Converters.
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