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Function of the parasitic bipolar transistor in the 40 nm PD SOI NMOS device considering the floating body effect
Solid-State Electronics 70 (2012) 3–7
Contents lists available at SciVerse ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Function of the parasitic bipolar transistor in the 40 nm PD SOI NMOS device considering the floating body effect C.H. Chena a, J.B. Kuo a,⇑, D. Chen b, C.S. Yeh b a b
Dept. of Electrical Eng., National Taiwan University, Taipei 10617, Taiwan, ROC United Microelectronics Corp., Hsinchu 300, Taiwan, ROC
a r t i c l e
i n f o
Article history: Available online 5 January 2012 Keywords: SOI Partially depleted Floating body effect
a b s t r a c t This paper reports the function of the parasitic bipolar device in the 40 nm PD SOI NMOS device with the floating body effect. Using a unique extraction method, the function of the parasitic bipolar device during DC and transient operations could be modelled. During the turn-on transient by imposing a step voltage from 0 V to 2 V on the gate, the case with the a slower rise time shows a relatively faster turn-on in the drain current due to a stronger function of the parasitic bipolar device from smaller displacement currents through the gate oxide, as reflected in the current gain, as verified by the experimentally measured result. Ó 2011 Elsevier Ltd. All rights reserved.
1. Introduction Floating body effect of PD SOI CMOS devices have been studied intensively in the past [1,2]. The parasitic bipolar device in the PD device, which could cause the kink effect, is difficult to model [3,4]. In fact, the parasitic bipolar device is important for the behaviour of the PD SOI CMOS devices. In this paper, using a unique extraction method, the function of the parasitic bipolar device during the DC and the transient operations could be modelled. It will be shown that during the turn-on transient by imposing a step voltage from 0 V to 2 V on the gate, the case with a slower rise time shows a relatively faster turn-on in the drain current due to a stronger function of the parasitic bipolar device as reflected in the current gain as verified by the experimentally measured results. In the following section, the test device is described first, followed by the DC and transient operations and discussion. 2. 40 nm PD SOI NMOS device The 40 nm PD SOI NMOS test device fabricated in the industry with its TEM cross section as shown in Fig. 1 has a 70 nm thin film doped with a p-type density of 3 1018 cm3 above a buried oxide of 145 nm and a gate oxide of 1.5 nm. A 65 nm LDD region doped with an n-type density of 1019 cm3 under a sidewall spacer has been used. A nickel polycide is formed on the top of the gate and a SiN capping layer is deposited over the device. The effective channel length of the device is 40 nm. Experimental measurement of the test device has been done for this study. In addition, 2D device simulation using a simulator [5] considering impact ionization ⇑ Corresponding author. E-mail address: [email protected] (J.B. Kuo). 0038-1101/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2011.11.013
[6,7] has also been used to carry out the study. For the PD device, there are 2152 grids used in the 2D simulation. No fixed charge has been assumed at the Si/SiO2 interface. Gate tunnelling leakage current has been neglected in this study [8]. 3. DC operation As described in Ref. [9], under the DC operation, the drain current behaviour of the 40 nm PD SOI NMOS device shows the kink effect. Fig. 2 shows the current conduction mechanism of the PD SOI NMOS device. At the gate oxide/thin film interface, there is a channel current (Ich) due to electron drift. In the high electric field region near the drain, impact ionization takes place, resulting in electron and hole pair formation. The generated electrons and holes move in the opposite directions as a result of the electric field – the generated electrons move toward the drain contact and the generated holes move in the source direction. This results in the generated electron and hole currents (Ih) that are equal in magnitude (the impact ionization current). A portion of the impact ionization current (kIh) is directed vertically toward the buried oxide owing to the vertical electric field. As a result, in the area above the buried oxide in the thin film, there is a base current, which leads to activation of the parasitic bipolar device above the buried oxide. As the bipolar device is activated, these holes recombine with electrons in the base region. In the parasitic bipolar region, a portion of the collec0 tor current ðk Ic Þ, which is mainly composed of electrons, is toward the high electric field as a result of the vertical electric field. These electrons also give rise to impact ionization and consequently also generate electron and hole pairs as for the channel current described above. Considering the effects of the impact ionization and the parasitic bipolar device, the drain current is composed of
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Fig. 1. TEM cross section of the 40 nm PD SOI NMOS device under study.
the channel current (Ich), the impact ionization current (Ih), and the collector current (Ic) of the parasitic bipolar device:
ID ¼ Ich þ Ih þ Ic
Fig. 3. Multiplication factor (M1) and current gain of the parasitic bipolar device versus gate voltage of the 40 nm PD SOI NMOS device biased at VD = 2 V, VS = 0 V and body floating, based on the 2D device simulation results.
ð1Þ
The source current of the device can be expressed as the sum of the channel current (Ich), a portion of the impact ionization current ½ð1 kÞIh , and the emitter current (Ie) of the parasitic bipolar device:
IS ¼ Ich þ ð1 kÞIh þ Ie
ð2Þ
The impact ionization current is a function of the current components, which include the channel current (Ich), and a portion of 0 the collector current ðk Ic Þ following through the high electric field region: 0
Ih ¼ ðM 1ÞðIch þ k Ic Þ
ð3Þ
where M1 is the multiplication factor. From above, the drain current of the PD SOI NMOS device is closely related to the parasitic bipolar device and impact ionization in the post-pinchoff region. From the 2D device simulation results, we may obtain the hole current component (1 k)Ih by extracting the hole current component from the source contact current IS. Also from the 2D simulation results, extracting from the drain contact current ID, we may obtain the hole current Ih. The channel current Ich, is obtained by
Fig. 4. Drain current of the 40 nm PD SOI NMOS device during the turn-on transient by imposing a step voltage from 0 V to 2 V on the gate and biased at VD = 2 V, VS = 0 V, and body floating, based on the experimentally measured data and the 2D device simulation results for the cases with the rise times of 10 ns and 100 ns.
Fig. 2. Current conduction mechanism of the PD SOI NMOS device.
C.H. Chena et al. / Solid-State Electronics 70 (2012) 3–7
5
Fig. 5. Equivalent circuit composed of the parasitic bipolar device and the surface MOS device of the PD SOI NMOS device with the floating body effect for transient analysis.
measuring the drain current ID by turning off impact ionization in the 2D device simulation. With extracted Ich, Ih, and (1 k)Ih with IS and ID from the 2D simulation results, one may obtain Ic, Ie, and M1 from Eqs. (1)–(3) as shown in following figure. Fig. 3 shows multiplication factor (M1) and current gain of the parasitic bipolar device versus gate voltage of the 40 nm PD SOI NMOS device biased at VD = 2 V, VS = 0 V and body floating, based on the 2D device simulation results. As shown in the figure, when the gate voltage decreases, M1 becomes smaller since the postpinchoff region shrinks. On the other hand, when the gate voltage increases, the trend on the current gain of the parasitic bipolar device is different – it becomes larger. 4. Transient operation The behaviour of the parasitic bipolar device during the transient operation of the PD SOI NMOS device may be quite different from that during the DC. Fig. 4 shows the drain current of the PD NMOS device during the turn-on transient by imposing a step voltage from 0 V to 2 V on the gate of the test device based on the experimentally
Fig. 6. Multiplication factor (M1) and current gain of the parasitic bipolar device in the PD SOI NMOS device during the turn-on transient with a voltage step from 0 V to 2 V imposed on the gate, biased at VD = 2 V and VS = 0 V and body floating, based on the 2D device simulation results.
measured data and the 2D device simulation results for the cases with the rise times of 10 ns and 100 ns. (The drain is connected to 2 V and the source is grounded with the body floating.) As shown in the figure, with a rise time of 10 ns for the gate voltage, the drain current could not reach its peak value at the end of the gate voltage ramp up period while with a rise time of 100 ns, it almost reaches it. The difference in the relative slew rate of the drain current curves during the ramp-up transients between the cases with different rise times may have some implications. Fig. 5 shows the equivalent circuit composed of the parasitic bipolar device and the surface MOS device of the PD SOI NMOS device with the floating body effect for transient analysis. As shown in the figure, during the turn-on transient, the current conduction mechanism of the PD SOI NMOS device considering the floating body effect is different from that of the DC case as indicated in Fig. 2. During the turn-on transient, the drain and the source displacement currents dQ D =dt; dQ s =dt through the gate oxide need to be considered. Taking into account the partitioned charge model (QS, QD) for the surface channel of the device with the current conduction mechanism described in the figure, the drain current
Fig. 7. Displacement currents during the turn-on transient of the 40 nm PD SOI NMOS device with the body floating and VD = 2 V and VS = 0 V, extracted from the 2D device simulation results.
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C.H. Chena et al. / Solid-State Electronics 70 (2012) 3–7
is composed of the surface channel current (Ich), the impact ionization current (Ih), the collector current of the parasitic bipolar device, and the drain displacement current (dQD/dt):
ID ¼ Ich þ lh þ lC þ ðdQ D =dtÞ
ð4Þ
The source current is composed of the surface channel current (Ich), the hole current component ½ð1 kÞIh , the emitter current (Ie) and the source displacement current (dQS/dt):
Is ¼ Ich þ ð1 kÞle þ ðdQ s =dtÞ
ð5Þ
where QS and QD are the weighted source and drain charges in the RL RL surface channel: Q s ¼ 0 ð1 ðy=LÞÞQ n ðy; tÞdy and Q D ¼ 0 ðy=LÞ Q n ðy; tÞdy, Qn is the total electrons in the surface channel. From Eqs. 4 and 5 one may obtain the multiplication factor (M1) and the current gain of the parasitic bipolar device during the turn-on transient of the test device as shown in Fig. 6. Fig. 6 shows the multiplication factor (M1) and the current gain of the parasitic bipolar device in the PD SOI NMOS device during the
turn-on transient with a voltage step from 0 V to 2 V imposed on the gate, biased at VD = 2 V and VS = 0 V and body floating, based on the 2D device simulation results. As shown in the figure, along with the progress of time during the gate voltage ramp-up period, the multiplication factor (M1) decreases due to the increase of the gate voltage leading to a smaller post-pinchoff region. On the other hand, when the gate voltage is small during the initial stage of the gate voltage ramp-up period, the current gain of the parasitic bipolar device is relatively small, indicating that the parasitic bipolar device is not turned on yet. During the final stage of the gate voltage ramp-up period, the current gain suddenly increases, which implies the turnon of the parasitic bipolar device. As shown in the solid lines, for the case with the longer rise time of 100 ns, both M1 and the current gain are larger as compared to the 10 ns case, which means the impact ionization in the post-pinchoff region is larger and the parasitic bipolar device functions stronger. Fig. 7 shows the displacement currents (dQS/dt, dQD/dt) during the turn-on transient of the 40 nm PD SOI NMOS device with the
Fig. 8. 2D electron density contours in the thin film of the 40 nm PD SOI NMOS device during the turn-on transient by imposing a step voltage from 0 V to 2 V on the gate, at the one-tenth of the gate voltage ramp-up period, for the cases with the rise times of 100 ns and 10 ns.
C.H. Chena et al. / Solid-State Electronics 70 (2012) 3–7
body floating and VD = 2 V and VS = 0 V, by imposing a voltage step from 0 V to 2 V on the gate, extracted from the 2D device simulation results. As shown in the figure, when the rise time of the gate voltage ramp-up period becomes longer, the drain displacement current (dQD/dt) becomes much smaller. Therefore, from Eq. 4 the collector current IC increases substantially. In addition, when the rise time of the gate voltage ramp-up period becomes longer, (dQS/dt) decreases to a smaller extent and the emitter current increases mildly. As a result, when the rise time of the gate voltage ramp-up period increases, the current gain of the parasitic bipolar device increases as shown in Fig. 6.
7
6. Conclusions In this paper, the function of the parasitic bipolar device in the 40 nm PD SOI NMOS device during the turn-on transient considering the floating body effect via a unique extraction method has been presented. During the turn-on transient, with a slower rise time for the gate voltage, the drain current turns on faster since the parasitic bipolar device is stronger with a larger current gain resulting from smaller displacement currents as verified by the experimentally measured result. References
5. Discussion More insight into the operation of the parasitic bipolar device in the PD SOI NMOS device during the turn-on transient could be obtained by studying the 2D hole density contours in the thin film of the device at the one 10th of the gate voltage ramp-up period. As shown Fig. 8, for the rise time of 100 ns, the more hole content in the thin film implies a stronger function of the parasitic bipolar device. Hence, the drain current is larger for the case with the rise time of 100 ns. With a larger rise time, the drain and source displacement currents (dQD/dt, dQS/dt) become smaller. As a result, more holes generated by the impact ionization in the past-pinchoff region stay at the bottom of the thin film, becoming the base current of the parasitic bipolar device. Therefore, the function of the parasitic bipolar device is stronger, leading to a larger drain current.
[1] Kuo JB. Low-voltage SOI CMOS VLSI devices and circuits. New York: Wiley; 2001. [2] Lin SC, Kuo JB. Temperature dependent kink effect model for Pd SOI NMOS device. IEEE Trans Elec Dev 1999;46:254–8. [3] Lin IS, Kuo JB. STI-induced mechanical stress-related kink effect of PD SOI NMOS device. EUROSOI 2008:81–2. [4] Lin IS, Kuo JB. STI-induced mechanical-stress-related kink effect behavior of 40 nm PD NMOS device. IEEE Trans Elec Dev 2008;55:1558–62. [5] Taurus Medici, Synopsys, Version X-2005-10. [6] Selberherr S. Analysis and simulation of semiconductor devices. Wien, New York: Springer-Verlag; 1984. [7] Valdinoci M, Ventura D, Vercchi MC, Rudan M, Baccarani G, Illien F, et al. Impact ionization in silicon at large operating temperature. Int Conf Simul Semicond Processes Dev 1999. [8] Hung HJ, Kuo JB, Chen D, Yeh CS. Gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect. Microelectron Reliab 2010;50:607–9. [9] Lin IS, Kuo JB, Chen D, Yeh CS. Analysis of STI-induced mechanical stress-related kink effect of 40 nm PD SOI NMOS devices biased in saturation. Solid St Elec 2008;52:1884–8.
Contents lists available at SciVerse ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Function of the parasitic bipolar transistor in the 40 nm PD SOI NMOS device considering the floating body effect C.H. Chena a, J.B. Kuo a,⇑, D. Chen b, C.S. Yeh b a b
Dept. of Electrical Eng., National Taiwan University, Taipei 10617, Taiwan, ROC United Microelectronics Corp., Hsinchu 300, Taiwan, ROC
a r t i c l e
i n f o
Article history: Available online 5 January 2012 Keywords: SOI Partially depleted Floating body effect
a b s t r a c t This paper reports the function of the parasitic bipolar device in the 40 nm PD SOI NMOS device with the floating body effect. Using a unique extraction method, the function of the parasitic bipolar device during DC and transient operations could be modelled. During the turn-on transient by imposing a step voltage from 0 V to 2 V on the gate, the case with the a slower rise time shows a relatively faster turn-on in the drain current due to a stronger function of the parasitic bipolar device from smaller displacement currents through the gate oxide, as reflected in the current gain, as verified by the experimentally measured result. Ó 2011 Elsevier Ltd. All rights reserved.
1. Introduction Floating body effect of PD SOI CMOS devices have been studied intensively in the past [1,2]. The parasitic bipolar device in the PD device, which could cause the kink effect, is difficult to model [3,4]. In fact, the parasitic bipolar device is important for the behaviour of the PD SOI CMOS devices. In this paper, using a unique extraction method, the function of the parasitic bipolar device during the DC and the transient operations could be modelled. It will be shown that during the turn-on transient by imposing a step voltage from 0 V to 2 V on the gate, the case with a slower rise time shows a relatively faster turn-on in the drain current due to a stronger function of the parasitic bipolar device as reflected in the current gain as verified by the experimentally measured results. In the following section, the test device is described first, followed by the DC and transient operations and discussion. 2. 40 nm PD SOI NMOS device The 40 nm PD SOI NMOS test device fabricated in the industry with its TEM cross section as shown in Fig. 1 has a 70 nm thin film doped with a p-type density of 3 1018 cm3 above a buried oxide of 145 nm and a gate oxide of 1.5 nm. A 65 nm LDD region doped with an n-type density of 1019 cm3 under a sidewall spacer has been used. A nickel polycide is formed on the top of the gate and a SiN capping layer is deposited over the device. The effective channel length of the device is 40 nm. Experimental measurement of the test device has been done for this study. In addition, 2D device simulation using a simulator [5] considering impact ionization ⇑ Corresponding author. E-mail address: [email protected] (J.B. Kuo). 0038-1101/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2011.11.013
[6,7] has also been used to carry out the study. For the PD device, there are 2152 grids used in the 2D simulation. No fixed charge has been assumed at the Si/SiO2 interface. Gate tunnelling leakage current has been neglected in this study [8]. 3. DC operation As described in Ref. [9], under the DC operation, the drain current behaviour of the 40 nm PD SOI NMOS device shows the kink effect. Fig. 2 shows the current conduction mechanism of the PD SOI NMOS device. At the gate oxide/thin film interface, there is a channel current (Ich) due to electron drift. In the high electric field region near the drain, impact ionization takes place, resulting in electron and hole pair formation. The generated electrons and holes move in the opposite directions as a result of the electric field – the generated electrons move toward the drain contact and the generated holes move in the source direction. This results in the generated electron and hole currents (Ih) that are equal in magnitude (the impact ionization current). A portion of the impact ionization current (kIh) is directed vertically toward the buried oxide owing to the vertical electric field. As a result, in the area above the buried oxide in the thin film, there is a base current, which leads to activation of the parasitic bipolar device above the buried oxide. As the bipolar device is activated, these holes recombine with electrons in the base region. In the parasitic bipolar region, a portion of the collec0 tor current ðk Ic Þ, which is mainly composed of electrons, is toward the high electric field as a result of the vertical electric field. These electrons also give rise to impact ionization and consequently also generate electron and hole pairs as for the channel current described above. Considering the effects of the impact ionization and the parasitic bipolar device, the drain current is composed of
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C.H. Chena et al. / Solid-State Electronics 70 (2012) 3–7
Fig. 1. TEM cross section of the 40 nm PD SOI NMOS device under study.
the channel current (Ich), the impact ionization current (Ih), and the collector current (Ic) of the parasitic bipolar device:
ID ¼ Ich þ Ih þ Ic
Fig. 3. Multiplication factor (M1) and current gain of the parasitic bipolar device versus gate voltage of the 40 nm PD SOI NMOS device biased at VD = 2 V, VS = 0 V and body floating, based on the 2D device simulation results.
ð1Þ
The source current of the device can be expressed as the sum of the channel current (Ich), a portion of the impact ionization current ½ð1 kÞIh , and the emitter current (Ie) of the parasitic bipolar device:
IS ¼ Ich þ ð1 kÞIh þ Ie
ð2Þ
The impact ionization current is a function of the current components, which include the channel current (Ich), and a portion of 0 the collector current ðk Ic Þ following through the high electric field region: 0
Ih ¼ ðM 1ÞðIch þ k Ic Þ
ð3Þ
where M1 is the multiplication factor. From above, the drain current of the PD SOI NMOS device is closely related to the parasitic bipolar device and impact ionization in the post-pinchoff region. From the 2D device simulation results, we may obtain the hole current component (1 k)Ih by extracting the hole current component from the source contact current IS. Also from the 2D simulation results, extracting from the drain contact current ID, we may obtain the hole current Ih. The channel current Ich, is obtained by
Fig. 4. Drain current of the 40 nm PD SOI NMOS device during the turn-on transient by imposing a step voltage from 0 V to 2 V on the gate and biased at VD = 2 V, VS = 0 V, and body floating, based on the experimentally measured data and the 2D device simulation results for the cases with the rise times of 10 ns and 100 ns.
Fig. 2. Current conduction mechanism of the PD SOI NMOS device.
C.H. Chena et al. / Solid-State Electronics 70 (2012) 3–7
5
Fig. 5. Equivalent circuit composed of the parasitic bipolar device and the surface MOS device of the PD SOI NMOS device with the floating body effect for transient analysis.
measuring the drain current ID by turning off impact ionization in the 2D device simulation. With extracted Ich, Ih, and (1 k)Ih with IS and ID from the 2D simulation results, one may obtain Ic, Ie, and M1 from Eqs. (1)–(3) as shown in following figure. Fig. 3 shows multiplication factor (M1) and current gain of the parasitic bipolar device versus gate voltage of the 40 nm PD SOI NMOS device biased at VD = 2 V, VS = 0 V and body floating, based on the 2D device simulation results. As shown in the figure, when the gate voltage decreases, M1 becomes smaller since the postpinchoff region shrinks. On the other hand, when the gate voltage increases, the trend on the current gain of the parasitic bipolar device is different – it becomes larger. 4. Transient operation The behaviour of the parasitic bipolar device during the transient operation of the PD SOI NMOS device may be quite different from that during the DC. Fig. 4 shows the drain current of the PD NMOS device during the turn-on transient by imposing a step voltage from 0 V to 2 V on the gate of the test device based on the experimentally
Fig. 6. Multiplication factor (M1) and current gain of the parasitic bipolar device in the PD SOI NMOS device during the turn-on transient with a voltage step from 0 V to 2 V imposed on the gate, biased at VD = 2 V and VS = 0 V and body floating, based on the 2D device simulation results.
measured data and the 2D device simulation results for the cases with the rise times of 10 ns and 100 ns. (The drain is connected to 2 V and the source is grounded with the body floating.) As shown in the figure, with a rise time of 10 ns for the gate voltage, the drain current could not reach its peak value at the end of the gate voltage ramp up period while with a rise time of 100 ns, it almost reaches it. The difference in the relative slew rate of the drain current curves during the ramp-up transients between the cases with different rise times may have some implications. Fig. 5 shows the equivalent circuit composed of the parasitic bipolar device and the surface MOS device of the PD SOI NMOS device with the floating body effect for transient analysis. As shown in the figure, during the turn-on transient, the current conduction mechanism of the PD SOI NMOS device considering the floating body effect is different from that of the DC case as indicated in Fig. 2. During the turn-on transient, the drain and the source displacement currents dQ D =dt; dQ s =dt through the gate oxide need to be considered. Taking into account the partitioned charge model (QS, QD) for the surface channel of the device with the current conduction mechanism described in the figure, the drain current
Fig. 7. Displacement currents during the turn-on transient of the 40 nm PD SOI NMOS device with the body floating and VD = 2 V and VS = 0 V, extracted from the 2D device simulation results.
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C.H. Chena et al. / Solid-State Electronics 70 (2012) 3–7
is composed of the surface channel current (Ich), the impact ionization current (Ih), the collector current of the parasitic bipolar device, and the drain displacement current (dQD/dt):
ID ¼ Ich þ lh þ lC þ ðdQ D =dtÞ
ð4Þ
The source current is composed of the surface channel current (Ich), the hole current component ½ð1 kÞIh , the emitter current (Ie) and the source displacement current (dQS/dt):
Is ¼ Ich þ ð1 kÞle þ ðdQ s =dtÞ
ð5Þ
where QS and QD are the weighted source and drain charges in the RL RL surface channel: Q s ¼ 0 ð1 ðy=LÞÞQ n ðy; tÞdy and Q D ¼ 0 ðy=LÞ Q n ðy; tÞdy, Qn is the total electrons in the surface channel. From Eqs. 4 and 5 one may obtain the multiplication factor (M1) and the current gain of the parasitic bipolar device during the turn-on transient of the test device as shown in Fig. 6. Fig. 6 shows the multiplication factor (M1) and the current gain of the parasitic bipolar device in the PD SOI NMOS device during the
turn-on transient with a voltage step from 0 V to 2 V imposed on the gate, biased at VD = 2 V and VS = 0 V and body floating, based on the 2D device simulation results. As shown in the figure, along with the progress of time during the gate voltage ramp-up period, the multiplication factor (M1) decreases due to the increase of the gate voltage leading to a smaller post-pinchoff region. On the other hand, when the gate voltage is small during the initial stage of the gate voltage ramp-up period, the current gain of the parasitic bipolar device is relatively small, indicating that the parasitic bipolar device is not turned on yet. During the final stage of the gate voltage ramp-up period, the current gain suddenly increases, which implies the turnon of the parasitic bipolar device. As shown in the solid lines, for the case with the longer rise time of 100 ns, both M1 and the current gain are larger as compared to the 10 ns case, which means the impact ionization in the post-pinchoff region is larger and the parasitic bipolar device functions stronger. Fig. 7 shows the displacement currents (dQS/dt, dQD/dt) during the turn-on transient of the 40 nm PD SOI NMOS device with the
Fig. 8. 2D electron density contours in the thin film of the 40 nm PD SOI NMOS device during the turn-on transient by imposing a step voltage from 0 V to 2 V on the gate, at the one-tenth of the gate voltage ramp-up period, for the cases with the rise times of 100 ns and 10 ns.
C.H. Chena et al. / Solid-State Electronics 70 (2012) 3–7
body floating and VD = 2 V and VS = 0 V, by imposing a voltage step from 0 V to 2 V on the gate, extracted from the 2D device simulation results. As shown in the figure, when the rise time of the gate voltage ramp-up period becomes longer, the drain displacement current (dQD/dt) becomes much smaller. Therefore, from Eq. 4 the collector current IC increases substantially. In addition, when the rise time of the gate voltage ramp-up period becomes longer, (dQS/dt) decreases to a smaller extent and the emitter current increases mildly. As a result, when the rise time of the gate voltage ramp-up period increases, the current gain of the parasitic bipolar device increases as shown in Fig. 6.
7
6. Conclusions In this paper, the function of the parasitic bipolar device in the 40 nm PD SOI NMOS device during the turn-on transient considering the floating body effect via a unique extraction method has been presented. During the turn-on transient, with a slower rise time for the gate voltage, the drain current turns on faster since the parasitic bipolar device is stronger with a larger current gain resulting from smaller displacement currents as verified by the experimentally measured result. References
5. Discussion More insight into the operation of the parasitic bipolar device in the PD SOI NMOS device during the turn-on transient could be obtained by studying the 2D hole density contours in the thin film of the device at the one 10th of the gate voltage ramp-up period. As shown Fig. 8, for the rise time of 100 ns, the more hole content in the thin film implies a stronger function of the parasitic bipolar device. Hence, the drain current is larger for the case with the rise time of 100 ns. With a larger rise time, the drain and source displacement currents (dQD/dt, dQS/dt) become smaller. As a result, more holes generated by the impact ionization in the past-pinchoff region stay at the bottom of the thin film, becoming the base current of the parasitic bipolar device. Therefore, the function of the parasitic bipolar device is stronger, leading to a larger drain current.
[1] Kuo JB. Low-voltage SOI CMOS VLSI devices and circuits. New York: Wiley; 2001. [2] Lin SC, Kuo JB. Temperature dependent kink effect model for Pd SOI NMOS device. IEEE Trans Elec Dev 1999;46:254–8. [3] Lin IS, Kuo JB. STI-induced mechanical stress-related kink effect of PD SOI NMOS device. EUROSOI 2008:81–2. [4] Lin IS, Kuo JB. STI-induced mechanical-stress-related kink effect behavior of 40 nm PD NMOS device. IEEE Trans Elec Dev 2008;55:1558–62. [5] Taurus Medici, Synopsys, Version X-2005-10. [6] Selberherr S. Analysis and simulation of semiconductor devices. Wien, New York: Springer-Verlag; 1984. [7] Valdinoci M, Ventura D, Vercchi MC, Rudan M, Baccarani G, Illien F, et al. Impact ionization in silicon at large operating temperature. Int Conf Simul Semicond Processes Dev 1999. [8] Hung HJ, Kuo JB, Chen D, Yeh CS. Gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect. Microelectron Reliab 2010;50:607–9. [9] Lin IS, Kuo JB, Chen D, Yeh CS. Analysis of STI-induced mechanical stress-related kink effect of 40 nm PD SOI NMOS devices biased in saturation. Solid St Elec 2008;52:1884–8.