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GaN HEMTs after hot electron stressing
Microelectronics Reliability 55 (2015) 1187–1191
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Performance of commercial foundry-level AlGaN/GaN HEMTs after hot electron stressing B.S. Poling a,⇑, J.L. Brown b, E.R. Heller c, B. Stumpff b, J.A. Beckman d, A.M. Hilton b a
Air Force Research Laboratory, Sensors Directorate, Wright-Patterson AFB, OH, United States Wyle, Dayton, OH, United States c Air Force Research Laboratory, Materials and Manufacturing Directorate, Wright-Patterson AFB, OH, United States d Southwestern Ohio Council for Higher Education, Dayton, OH, United States b
a r t i c l e
i n f o
Article history: Received 29 December 2014 Received in revised form 14 May 2015 Accepted 15 May 2015 Available online 12 June 2015 Keywords: Gallium nitride (GaN) High electron mobility transistors (HEMTs) Electroluminescence Hot electron
a b s t r a c t The performance degradation of commercial foundry level GaN HEMTs placed under a constant-power drain voltage step-stress test has been studied. By utilizing electroluminescence measurement techniques to optimize hot electron stress testing conditions (Meneghini, 2012), no significant permanent changes in saturation current (Idss), transconductance (Gm), and threshold voltage (Vth) can be seen after stress testing of drain voltages from 30 V up to 200 V. We observe little permanent degradation due to hot electron effects in GaN HEMTs at these extreme operating conditions and it is inferred that other considerations, such as key dimensions in channel or peak electric field (Chynoweth, 1958; Zhang and Singh, 2001) [2,3], are more relevant to physics of failure than drain bias alone. Published by Elsevier Ltd.
1. Introduction GaN high electron mobility transistors (HEMTs) have advantages over current RF amplifier technology in output power, bandwidth, and efficiency [4]. GaN HEMTs offer more power and better efficiency in a smaller periphery than leading GaAs technology alternatives [5]. Currently there are concerns regarding the reliability of GaN HEMTs due to the extremely large estimated lifetimes reported in literature and the number of failure mechanisms noted [6]. Current research in improvements of thermal management [7] present possibilities of operating GaN HEMTs at higher power and lower channel temperatures where non-thermally activated failure mechanisms become more prominent. For thermally induced degradation, lattice temperature is the dominant rate limiter to failure based on an Arrhenius rate law and degradation proceeds much faster as either ambient temperature or power is increased, other things held constant. In marked contrast, it has been reported that degradation can occur with as little as 10–30 V drain bias when GaN HEMTs are held in a partially-on state [8], with little to no ambient temperature acceleration and with a degradation rate that peaks at a partially on condition for a set drain bias. Hot electron degradation has been reported [1] on GaN HEMTs utilizing electroluminescence (EL) to characterize the hot electron concentration in the channel ⇑ Corresponding author. http://dx.doi.org/10.1016/j.microrel.2015.05.010 0026-2714/Published by Elsevier Ltd.
with stress test on the devices at a drain voltage of 30 V and several gate voltage values. The author reported degradation in drain current caused by hot electron stressing and no change in threshold voltage. From this setup, a degradation rate is reported to peak at maximum EL intensity and a peak degradation rate can be determined as a function of gate voltage. Voltage limitations from hot electron stress have been reported at VSD = 30 V, VGD 31 V and LGD = 2 lm for 14 h (gate–drain average electric field 15 V/lm) [1], VSD = 20 V, VGD = 22 V and LGD 2–3 lm (LGD was not specified but LSD was 4 lm and LG was 0.25 lm) so gate–drain average electric field > 6.7 V/lm for 30 h [9], VSD = 20 V, VGD = 25.5 V and LGD = 3.4 lm (gate–drain average electric field 5.9 V/lm) for 10 h [10], and it is clear there is considerable spread in values and also in all cases these are far below GaN’s known breakdown field of300 V/lm [11]. In these cases gate–drain average electric field is defined assuming the field is uniform between the drain edge of the gate footprint and the beginning of the drain metallization. Of course, to understand the intrinsic reliability of GaN based technology, other metrics such as the peak electric field [2,3] in the channel region are more appropriate, for which gate–drain average electric field is a lower limit. We did not compute peak field because this requires details not found in most publications such as overhang of gate field plate and dielectric composition and thickness under it. One limitation in much of the reported literature on hot electron stress is that the devices are not described in enough detail
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to ascertain if the findings are intrinsic to the GaN materials system or process or defect driven in nature, frustrating efforts to understand materials intrinsic physics of failure. Our devices are commercially fabricated, unused for prior studies prior to the work described herein, representative of a stable commercial process that has been seen to pass thermally accelerated life tests [12], and were verified to be representative of the lot (in family) prior to data collection. Reliability improvements in GaN HEMTs have been ongoing and the failure modes once noted have been reduced by optimization. This paper utilizes the characterized EL method of hot electron stressing [1], the reported optimal condition of hot electron stressing [10], and introduces reliability testing at the reported optimal condition and step stress testing at various drain voltages to attempt to induce hot electron degradation in commercially-relevant devices.
2. Test setup and devices The devices used were 2 50 lm periphery AlGaN/GaN commercial foundry level HEMT structures having a source connected field plate and no source connected field plate. Both sample lots were taken from the same wafer, approximately in the center with 4 devices tested per sample lot. Field plate and non-field plate devices are nominally the same other than this one difference (i.e. same gate length, source–gate and gate–drain channel spacing, periphery, and are from neighboring locations from same wafer). While this is not central to the hypothesis explored in this work, it is added as a valuable comparison. The devices were grown on a SiC substrate with an AlGaN barrier, a GaN buffer, and a nominal 0.5 lm gate length (see Fig. 1) [6]. Each die was mounted on a Stratedge 580,286 LPA package using EPO-TEK H20E-HC silver bearing epoxy and then wire bonded to the input and output lead frames using 0.000700 diameter 99.99% Au wire. More information on the devices used can be found in [12]. The source connected field plate devices were tested utilizing a Keithley 2612A SMU with coax cables going from the outputs to a copper block with 50 X bias T’s for device operation. Light exposure was done with an AmScope HL-250-A white light source and measurements were recorded using custom written test code for the SMU. The non-source connected field plate devices were electrically characterized and stressed using an Accel-RF reliability test system with an integrated Agilent E5270B Mainframe with E5280B SMU’s and test fixtures integrated with bias T’s for device operation. All data recordings were done using Accel-RF’s commercial Lifetest software. EL characterization was performed by a Quantum Focus Instruments (QFI) unit with a Si deep depletion CCD detector for photoemission and utilizing a 50 near Infrared (NIR) objective. The source connected field plate devices were electrically characterized by a current–voltage family of curves (IV-FOC) pre and post stress. The hot electron stress testing was conducted with a gate bias (Vg) of 2 V and drain biases (Vd) of 30 V, 100 V, 150 V, and 200 V. After each bias condition, electrical characterization was conducted to track any changes in device performance. The non-source connected field plate devices were stress tested using knowledge gained from testing the source connected field plate devices. By utilizing the method described in [1], electroluminescence was performed on two samples out of four total at Vd = 10 V, 20 V, and 30 V with Vg ranging from 6 V up to 0 V for each Vd value used and a baseplate temperature (Tbp) = 50 °C. After reaching 0 V on the gate, three additional measurements were taken at Vg = 1 V, 2 V, and 3 V to verify focus drift of the QFI system and to ensure sample degradation is not a contributor to the data. For the constant-power drain voltage step stress test, a power bias of 10 W/mm was chosen with a Vd value ranging
Fig. 1. A representation of the channel region [6] of devices used in this study. S = source, G = gate, D = drain, SCFP = source connected field plate. The SCFP in light pink was not present for the non-source connected field plate devices. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
from 30 V up to 100 V at a Tbp = 50 °C. Each step was separated by 10 V and each step lasted a total time of 24 h. The testing sequence consisted of IV-FOC, transfer curves, and gate leakage electrical characterization, and then stress testing for 24 h at the desired Vd value, followed by another round of electrical characterization test. After the last stress point of Vd = 100 V, a suite of post stress electrical characterization was performed, followed by a resting period of 30 days in the dark. To understand the nature of the post-stress changes seen, electrical characterization was conducted after the rest, and then white light was shined on the stress parts for 5 min each, followed by a last round of electrical characterization on the device under test. The electrical characterization test consisting of IV-FOC, transfer curves, and gate leakage was conducted at a Tbp = 50 °C. The IV-FOC swept Vg = 4 V to 0 V in 1 V steps and sweeping Vd = 0– 10 V in 31 steps. The transfer curve set Vd = 10 V and swept Vg = 6 V to 0.5 V in 41 steps. Gate leakage set Vg = 5 V and sweeping Vd = 0–28 V in 29 steps. Vknee was taken at Vg = 0 V curve (from IV-FOC), Gm was taken at DIds/DVgs and Vth was calculated using peak Gm. Idss was taken at Vg = 0 V and Idmax was taken at Vg = 0.5 V. Both the step stress and electrical characterization were performed in a dark enclosure with dry nitrogen being fed into control the environment.
3. Results and discussion Minimal gate periphery and low ambient temperatures during stress were chosen to minimize thermal heating of the channel and cleanly separate any degradation seen from classic thermally accelerated degradation; peak channel temperature was estimated to be 135 °C, using thermal modeling techniques from [13] and adjusted to device periphery, during stressing (10 W/mm and Tbp = 50 °C). This is in marked contrast to thermally accelerated failure, where channel temperature is commonly estimated at 200 °C for extrapolated lifetimes from 105 to 107 h (107 h at 200 °C for devices representative of ones tested here [12]), and far higher still during a thermally accelerated life test [6,12]. The source connected field plate devices were stressed with the main purpose of inducing degradation in GaN HEMTs at a controlled rate. After failing to observe significant permanent degradation after stressing the device at a drain voltage of 30 V and a gate voltage of 2 V as expected from prior reports [1,10], the drain voltage was increased in controlled steps to 200 V. The source connected field plate device was stressed at a drain voltage of 200 V at a gate voltage of 2.5 V for a duration of 150 h. Baseline measurements were taken pre and post stress showing minimal change seen in Idss and Gm (Figs. 2 and 3). At a drain voltage = 200 V, minimal change is seen in the drain current and Gm, indicating that either hot electron degradation has
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Fig. 2. Pre vs. post stress IV-FOC for the devices with source connected field plate. Stress test was for 150 h.
not occurred or that the devices were not experiencing hot electron stressing. From the data with the source connected field plate devices, it was determined to take the non-source connected field plate devices and perform electroluminescence measurements to see if an optimal stressing condition can be determined (maximum degradation rate at a set drain bias). With light being obscured by the field plate, the non-source connected field plate device was used for EL testing. The non-source connected field plate device was tested at a drain voltage of 10 V, 20 V, and 30 V while sweeping the gate voltage from 6 V up to 0 V. To derive the relative EL intensity at each bias condition, an image was captured and the integrated, background subtracted sum, over the active area of the device was calculated (Fig. 4). This methodology was chosen because it is relatively insensitive to camera focus or any non-uniformity of light emission such as along the gate width or finger to finger. The method therefore compares light output summed from the entire device to electrical bias which is also effectively a sum from the entire device. It has been observed that the degradation rate is directly correlated with the EL intensity [1], and peaks at a partially open channel for a given drain bias. Plotting the EL intensity (arbitrary units) vs. the applied gate voltage for each drain voltage shows that as the drain voltage was increased, the peak EL is in agreement with [1] at lower drain bias, but the peak EL intensity moves towards open
Fig. 3. Pre vs. post stress Gm for the devices with source connected field plate. Vd ranges from 1 V up to 3 V. Stress test was for 150 h.
Fig. 4. EL at (a) 10 V, (b) 20 V and (c) 30 V for a device without source connected field plate showing typical within-finger variation, finger–finger variation and lightpiping effects. In all cases, the relative intensity scale at far left applies to that row.
channel and beyond (Fig. 5) as the drain voltage is increased, implying peak hot electron stress at higher power for a given baseplate temperature. This proves to be a problem when trying to conduct hot electron stress testing at higher than 30 V drain values. With the trend of the peak degradation rate moving to more open channel, the higher drain value coupled with higher power will cause the device to self-heat due to the higher power dissipation. This induces thermal stressing to the device instead of hot electron stressing. To avoid this, an input bias point of 10 W/mm was used while stepping the drain voltage from 30 V up to 100 V, with the gate voltage in the range of 3 V to 1.9 V. To verify a repeatable EL measurement, after the last bias point was measured three more points (at Vg = 1 V, 2 V, and 3 V) were measured and no drift and no degradation was observed in the non-source connected field plate devices. With reported degradation from hot electron stressing occurring within hours, setting the time duration of each drain voltage step at 24 h was considered sufficient to observe noticeable degradation. At each step, electrical characterization was conducted as described in Section 2, and after each step a decrease in Idss was seen in the IV-FOC curves (Fig. 6 blue1 and red curves). Unexpectedly, the transfer curve conducted less than one minute at a baseplate temperature of 50 °C after the IV-FOC’s showed little sign of degradation and Idss taken from the transfer curve (Fig. 7 blue and red curves) data showed little change as well. With data showing changes in the IV-FOC but insignificant change in the transfer curve, it was hypothesized that a fast acting trap was being reset before the transfer curve could be conducted.
1 For interpretation of color in Figs. 6 and 7, the reader is referred to the web version of this article.
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Fig. 5. EL relative intensity at various Vd values for device without source connected field plate.
Fig. 8. Idss step-stress data for each characterization step. X axis step 2 refers to prestress, step 3 refers to 30 V, and so on to step 12 refers to after light exposure characterization.
Table 1 Transfer curve data summary non-field plate device. Key parameters
Pre
Post
Rest
Light
Idss (mA) Idmax (mA) Vth (V) Gm (mS/mm)
73.26 80.93 3.45 232.92
72.49 80.34 3.42 232.62
73.07 80.93 3.45 231.69
73.23 81.12 3.44 232.62
Table 2 IV-FOC data summary non-field plate device. Fig. 6. IV-FOC for device without source connected field plate.
Fig. 7. Transfer curve and Gm for device without source connected field plate.
This can be seen when comparing each characterization point, the change in Idss does not start to occur until Vd = 50 V, at which point Idss changes more and more, but after each IV-FOC curve test, the transfer curve test shows the trap resetting (Fig. 8). To test if change in device performance was due to the trap, the device was allowed to rest (no bias and room temperature baseplate) in the same environment that the step stress was conducted at. After rest, the devices showed near complete recovery in the IV-FOC (Fig. 6 green curve) and no change seen in the transfer curve. After rest, a white light (see Section 2) was shined on the devices for a total time of 5 min, after which the devices were electrically characterized; this showed the devices fully recovered from the trap degradation seen (Fig. 6 and 7 purple curve). This showed there was no permanent degradation due to the constant-power
Key parameters
Pre
Post
Rest
Light
Idss (mA) VKnee (V)
73.40 3.40
69.75 3.50
73.45 3.45
73.65 3.45
drain voltage step-stress at the expected hot electron stressing conditions. When taking in consideration some of the key electrical parameters quantified from the electrical characterization test, the changes observed are dependent on when the characterization test was performed, which is attributed to fast acting trap recovery. Comparing the change seen in Idss, when recorded from the IV-FOC data (Table 2), shows a delta of 5%. Associating the change seen in Idss, when recorded from the transfer curve data (Table 1), shows a delta of 1% due to the trap not being fully reset, yet recovering. Calculating the percent change after rest and after light exposure shows a delta nearly 0% from both the IV-FOC data and transfer curve data, indicating a fully reset trap. 4. Conclusion Hot electron stressing using known and reported stress conditions was conducted on a commercial foundry level sample lot of devices to evaluate the extent of hot electron degradation. At nominal operating conditions and highly elevated drain voltages up to 200 V and gate–drain average electric field 40 V/lm (based on nominal 5 lm gate to drain gap) for source connected field plate devices and 100 V for ones unprotected by this field plate, temporary changes from fast-resetting traps were observed, but no permanent degradation from hot electron stress was observed. This is in contrast to reports of significant degradation at 20–30 V and gate–drain average electric field of roughly 5.9–15 V/lm and demonstrates the fundamental limitations of the GaN materials
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system in either voltage or peak field from hot electron stress have not been reached. Acknowledgements The authors wish to thank the High Reliability Virtual Electronics Center (HiREV) for funding and helpful discussions and the Reliability of Electronics Devices – Failure Analysis and Characterization Laboratory (RED-FALCon) for test support. References [1] Meneghini M, Stocco A, Silvestri R, Meneghesso G, Zanoni E. Degradation of AlGaN/GaN high electron mobility transistors related to hot electrons. Appl Phys Lett 2012;100:233508. [2] Chynoweth AG. Ionization rates for electrons and holes in silicon. Phys Rev 1958;109(5):1537–40. [3] Zhang Y, Singh J. Monte Carlo studies of two dimensional transport in GaN/ AlGaN transistors: comparison with transport in AlGaAs/GaAs channels. J Appl Phys 2001;89(1):386–9. [4] Shur MS. GaN based transistors for high power applications. Solid-State Electron 1998;42:2131–8. [5] Christou A, Fantini F. Introduction to the special issue on GaN and related nitride compound device reliability. IEEE Trans Dev Mater 2008;8(2):239.
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[6] Christiansen BD, Coutu Jr. RA, Vetury R, Shealy JB, Heller ER, Poling B, et al. Reliability testing of AlGaN/GaN HEMTs under multiple stressors. In: IEEE IRPS conference, 2011. p. CD.2.1–5. [7] Via GD, Felbinger JG, Blevins J, Chabak K, Jessen G, Gillespie J, et al. Wafer-scale GaN HEMT performance enhancement by diamond substrate integration. PSS 2014;11(3–4):871–4. [8] Mukherjee S, Puzyrev Y, Chen J, Schrimpf RD, Fleetwood DM, Patelides ST. Modeling hot-carrier-induced degradation in AlGaN/GaN HEMTs. In: Reliability of compound semiconductors workshop, New Orleans, LA, May 13th, 2013 [presentation only]. [9] Silvestri M, Uren MJ, Kuball M. Dynamic transconductance dispersion characterization of channel hot-carrier stressed 0.25-lm AlGaN/GaN HEMTs. IEEE Electron Dev Lett 2012;33(11):1550–2. [10] Meneghesso G, Verzelesi G, Danesin F, Rampazzo F, Zanon F, Tazzoli A, et al. Reliability of GaN high-electron-mobility transistors: state of the art and perspectives. IEEE Trans Dev Mater Reliab 2008;8(2):332–43. [11] Dyakonova N, Dickens A, Shur MS, Gaska R, Yang JW. Temperature dependence of impact ionization in AlGaN–GaN heterostructure field effect transistors. Appl Phys Lett 1998;72(20):2562–4. 2562. [12] Shealy JB, Vetury R, Trabert B, Runton D. A manufacturable high power RF gallium nitride (GaN) technology portfolio with 65V operation and enhanced linearity. IEEE COMCAS; 2011. [13] Heller E, Choi S, Dorsey D, Vetury R, Graham S. Electrical and structural dependence of operating temperature of AlGaN/GaN HEMTs. Microelectron Reliab 2013;53:872–7.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Performance of commercial foundry-level AlGaN/GaN HEMTs after hot electron stressing B.S. Poling a,⇑, J.L. Brown b, E.R. Heller c, B. Stumpff b, J.A. Beckman d, A.M. Hilton b a
Air Force Research Laboratory, Sensors Directorate, Wright-Patterson AFB, OH, United States Wyle, Dayton, OH, United States c Air Force Research Laboratory, Materials and Manufacturing Directorate, Wright-Patterson AFB, OH, United States d Southwestern Ohio Council for Higher Education, Dayton, OH, United States b
a r t i c l e
i n f o
Article history: Received 29 December 2014 Received in revised form 14 May 2015 Accepted 15 May 2015 Available online 12 June 2015 Keywords: Gallium nitride (GaN) High electron mobility transistors (HEMTs) Electroluminescence Hot electron
a b s t r a c t The performance degradation of commercial foundry level GaN HEMTs placed under a constant-power drain voltage step-stress test has been studied. By utilizing electroluminescence measurement techniques to optimize hot electron stress testing conditions (Meneghini, 2012), no significant permanent changes in saturation current (Idss), transconductance (Gm), and threshold voltage (Vth) can be seen after stress testing of drain voltages from 30 V up to 200 V. We observe little permanent degradation due to hot electron effects in GaN HEMTs at these extreme operating conditions and it is inferred that other considerations, such as key dimensions in channel or peak electric field (Chynoweth, 1958; Zhang and Singh, 2001) [2,3], are more relevant to physics of failure than drain bias alone. Published by Elsevier Ltd.
1. Introduction GaN high electron mobility transistors (HEMTs) have advantages over current RF amplifier technology in output power, bandwidth, and efficiency [4]. GaN HEMTs offer more power and better efficiency in a smaller periphery than leading GaAs technology alternatives [5]. Currently there are concerns regarding the reliability of GaN HEMTs due to the extremely large estimated lifetimes reported in literature and the number of failure mechanisms noted [6]. Current research in improvements of thermal management [7] present possibilities of operating GaN HEMTs at higher power and lower channel temperatures where non-thermally activated failure mechanisms become more prominent. For thermally induced degradation, lattice temperature is the dominant rate limiter to failure based on an Arrhenius rate law and degradation proceeds much faster as either ambient temperature or power is increased, other things held constant. In marked contrast, it has been reported that degradation can occur with as little as 10–30 V drain bias when GaN HEMTs are held in a partially-on state [8], with little to no ambient temperature acceleration and with a degradation rate that peaks at a partially on condition for a set drain bias. Hot electron degradation has been reported [1] on GaN HEMTs utilizing electroluminescence (EL) to characterize the hot electron concentration in the channel ⇑ Corresponding author. http://dx.doi.org/10.1016/j.microrel.2015.05.010 0026-2714/Published by Elsevier Ltd.
with stress test on the devices at a drain voltage of 30 V and several gate voltage values. The author reported degradation in drain current caused by hot electron stressing and no change in threshold voltage. From this setup, a degradation rate is reported to peak at maximum EL intensity and a peak degradation rate can be determined as a function of gate voltage. Voltage limitations from hot electron stress have been reported at VSD = 30 V, VGD 31 V and LGD = 2 lm for 14 h (gate–drain average electric field 15 V/lm) [1], VSD = 20 V, VGD = 22 V and LGD 2–3 lm (LGD was not specified but LSD was 4 lm and LG was 0.25 lm) so gate–drain average electric field > 6.7 V/lm for 30 h [9], VSD = 20 V, VGD = 25.5 V and LGD = 3.4 lm (gate–drain average electric field 5.9 V/lm) for 10 h [10], and it is clear there is considerable spread in values and also in all cases these are far below GaN’s known breakdown field of300 V/lm [11]. In these cases gate–drain average electric field is defined assuming the field is uniform between the drain edge of the gate footprint and the beginning of the drain metallization. Of course, to understand the intrinsic reliability of GaN based technology, other metrics such as the peak electric field [2,3] in the channel region are more appropriate, for which gate–drain average electric field is a lower limit. We did not compute peak field because this requires details not found in most publications such as overhang of gate field plate and dielectric composition and thickness under it. One limitation in much of the reported literature on hot electron stress is that the devices are not described in enough detail
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to ascertain if the findings are intrinsic to the GaN materials system or process or defect driven in nature, frustrating efforts to understand materials intrinsic physics of failure. Our devices are commercially fabricated, unused for prior studies prior to the work described herein, representative of a stable commercial process that has been seen to pass thermally accelerated life tests [12], and were verified to be representative of the lot (in family) prior to data collection. Reliability improvements in GaN HEMTs have been ongoing and the failure modes once noted have been reduced by optimization. This paper utilizes the characterized EL method of hot electron stressing [1], the reported optimal condition of hot electron stressing [10], and introduces reliability testing at the reported optimal condition and step stress testing at various drain voltages to attempt to induce hot electron degradation in commercially-relevant devices.
2. Test setup and devices The devices used were 2 50 lm periphery AlGaN/GaN commercial foundry level HEMT structures having a source connected field plate and no source connected field plate. Both sample lots were taken from the same wafer, approximately in the center with 4 devices tested per sample lot. Field plate and non-field plate devices are nominally the same other than this one difference (i.e. same gate length, source–gate and gate–drain channel spacing, periphery, and are from neighboring locations from same wafer). While this is not central to the hypothesis explored in this work, it is added as a valuable comparison. The devices were grown on a SiC substrate with an AlGaN barrier, a GaN buffer, and a nominal 0.5 lm gate length (see Fig. 1) [6]. Each die was mounted on a Stratedge 580,286 LPA package using EPO-TEK H20E-HC silver bearing epoxy and then wire bonded to the input and output lead frames using 0.000700 diameter 99.99% Au wire. More information on the devices used can be found in [12]. The source connected field plate devices were tested utilizing a Keithley 2612A SMU with coax cables going from the outputs to a copper block with 50 X bias T’s for device operation. Light exposure was done with an AmScope HL-250-A white light source and measurements were recorded using custom written test code for the SMU. The non-source connected field plate devices were electrically characterized and stressed using an Accel-RF reliability test system with an integrated Agilent E5270B Mainframe with E5280B SMU’s and test fixtures integrated with bias T’s for device operation. All data recordings were done using Accel-RF’s commercial Lifetest software. EL characterization was performed by a Quantum Focus Instruments (QFI) unit with a Si deep depletion CCD detector for photoemission and utilizing a 50 near Infrared (NIR) objective. The source connected field plate devices were electrically characterized by a current–voltage family of curves (IV-FOC) pre and post stress. The hot electron stress testing was conducted with a gate bias (Vg) of 2 V and drain biases (Vd) of 30 V, 100 V, 150 V, and 200 V. After each bias condition, electrical characterization was conducted to track any changes in device performance. The non-source connected field plate devices were stress tested using knowledge gained from testing the source connected field plate devices. By utilizing the method described in [1], electroluminescence was performed on two samples out of four total at Vd = 10 V, 20 V, and 30 V with Vg ranging from 6 V up to 0 V for each Vd value used and a baseplate temperature (Tbp) = 50 °C. After reaching 0 V on the gate, three additional measurements were taken at Vg = 1 V, 2 V, and 3 V to verify focus drift of the QFI system and to ensure sample degradation is not a contributor to the data. For the constant-power drain voltage step stress test, a power bias of 10 W/mm was chosen with a Vd value ranging
Fig. 1. A representation of the channel region [6] of devices used in this study. S = source, G = gate, D = drain, SCFP = source connected field plate. The SCFP in light pink was not present for the non-source connected field plate devices. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
from 30 V up to 100 V at a Tbp = 50 °C. Each step was separated by 10 V and each step lasted a total time of 24 h. The testing sequence consisted of IV-FOC, transfer curves, and gate leakage electrical characterization, and then stress testing for 24 h at the desired Vd value, followed by another round of electrical characterization test. After the last stress point of Vd = 100 V, a suite of post stress electrical characterization was performed, followed by a resting period of 30 days in the dark. To understand the nature of the post-stress changes seen, electrical characterization was conducted after the rest, and then white light was shined on the stress parts for 5 min each, followed by a last round of electrical characterization on the device under test. The electrical characterization test consisting of IV-FOC, transfer curves, and gate leakage was conducted at a Tbp = 50 °C. The IV-FOC swept Vg = 4 V to 0 V in 1 V steps and sweeping Vd = 0– 10 V in 31 steps. The transfer curve set Vd = 10 V and swept Vg = 6 V to 0.5 V in 41 steps. Gate leakage set Vg = 5 V and sweeping Vd = 0–28 V in 29 steps. Vknee was taken at Vg = 0 V curve (from IV-FOC), Gm was taken at DIds/DVgs and Vth was calculated using peak Gm. Idss was taken at Vg = 0 V and Idmax was taken at Vg = 0.5 V. Both the step stress and electrical characterization were performed in a dark enclosure with dry nitrogen being fed into control the environment.
3. Results and discussion Minimal gate periphery and low ambient temperatures during stress were chosen to minimize thermal heating of the channel and cleanly separate any degradation seen from classic thermally accelerated degradation; peak channel temperature was estimated to be 135 °C, using thermal modeling techniques from [13] and adjusted to device periphery, during stressing (10 W/mm and Tbp = 50 °C). This is in marked contrast to thermally accelerated failure, where channel temperature is commonly estimated at 200 °C for extrapolated lifetimes from 105 to 107 h (107 h at 200 °C for devices representative of ones tested here [12]), and far higher still during a thermally accelerated life test [6,12]. The source connected field plate devices were stressed with the main purpose of inducing degradation in GaN HEMTs at a controlled rate. After failing to observe significant permanent degradation after stressing the device at a drain voltage of 30 V and a gate voltage of 2 V as expected from prior reports [1,10], the drain voltage was increased in controlled steps to 200 V. The source connected field plate device was stressed at a drain voltage of 200 V at a gate voltage of 2.5 V for a duration of 150 h. Baseline measurements were taken pre and post stress showing minimal change seen in Idss and Gm (Figs. 2 and 3). At a drain voltage = 200 V, minimal change is seen in the drain current and Gm, indicating that either hot electron degradation has
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Fig. 2. Pre vs. post stress IV-FOC for the devices with source connected field plate. Stress test was for 150 h.
not occurred or that the devices were not experiencing hot electron stressing. From the data with the source connected field plate devices, it was determined to take the non-source connected field plate devices and perform electroluminescence measurements to see if an optimal stressing condition can be determined (maximum degradation rate at a set drain bias). With light being obscured by the field plate, the non-source connected field plate device was used for EL testing. The non-source connected field plate device was tested at a drain voltage of 10 V, 20 V, and 30 V while sweeping the gate voltage from 6 V up to 0 V. To derive the relative EL intensity at each bias condition, an image was captured and the integrated, background subtracted sum, over the active area of the device was calculated (Fig. 4). This methodology was chosen because it is relatively insensitive to camera focus or any non-uniformity of light emission such as along the gate width or finger to finger. The method therefore compares light output summed from the entire device to electrical bias which is also effectively a sum from the entire device. It has been observed that the degradation rate is directly correlated with the EL intensity [1], and peaks at a partially open channel for a given drain bias. Plotting the EL intensity (arbitrary units) vs. the applied gate voltage for each drain voltage shows that as the drain voltage was increased, the peak EL is in agreement with [1] at lower drain bias, but the peak EL intensity moves towards open
Fig. 3. Pre vs. post stress Gm for the devices with source connected field plate. Vd ranges from 1 V up to 3 V. Stress test was for 150 h.
Fig. 4. EL at (a) 10 V, (b) 20 V and (c) 30 V for a device without source connected field plate showing typical within-finger variation, finger–finger variation and lightpiping effects. In all cases, the relative intensity scale at far left applies to that row.
channel and beyond (Fig. 5) as the drain voltage is increased, implying peak hot electron stress at higher power for a given baseplate temperature. This proves to be a problem when trying to conduct hot electron stress testing at higher than 30 V drain values. With the trend of the peak degradation rate moving to more open channel, the higher drain value coupled with higher power will cause the device to self-heat due to the higher power dissipation. This induces thermal stressing to the device instead of hot electron stressing. To avoid this, an input bias point of 10 W/mm was used while stepping the drain voltage from 30 V up to 100 V, with the gate voltage in the range of 3 V to 1.9 V. To verify a repeatable EL measurement, after the last bias point was measured three more points (at Vg = 1 V, 2 V, and 3 V) were measured and no drift and no degradation was observed in the non-source connected field plate devices. With reported degradation from hot electron stressing occurring within hours, setting the time duration of each drain voltage step at 24 h was considered sufficient to observe noticeable degradation. At each step, electrical characterization was conducted as described in Section 2, and after each step a decrease in Idss was seen in the IV-FOC curves (Fig. 6 blue1 and red curves). Unexpectedly, the transfer curve conducted less than one minute at a baseplate temperature of 50 °C after the IV-FOC’s showed little sign of degradation and Idss taken from the transfer curve (Fig. 7 blue and red curves) data showed little change as well. With data showing changes in the IV-FOC but insignificant change in the transfer curve, it was hypothesized that a fast acting trap was being reset before the transfer curve could be conducted.
1 For interpretation of color in Figs. 6 and 7, the reader is referred to the web version of this article.
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Fig. 5. EL relative intensity at various Vd values for device without source connected field plate.
Fig. 8. Idss step-stress data for each characterization step. X axis step 2 refers to prestress, step 3 refers to 30 V, and so on to step 12 refers to after light exposure characterization.
Table 1 Transfer curve data summary non-field plate device. Key parameters
Pre
Post
Rest
Light
Idss (mA) Idmax (mA) Vth (V) Gm (mS/mm)
73.26 80.93 3.45 232.92
72.49 80.34 3.42 232.62
73.07 80.93 3.45 231.69
73.23 81.12 3.44 232.62
Table 2 IV-FOC data summary non-field plate device. Fig. 6. IV-FOC for device without source connected field plate.
Fig. 7. Transfer curve and Gm for device without source connected field plate.
This can be seen when comparing each characterization point, the change in Idss does not start to occur until Vd = 50 V, at which point Idss changes more and more, but after each IV-FOC curve test, the transfer curve test shows the trap resetting (Fig. 8). To test if change in device performance was due to the trap, the device was allowed to rest (no bias and room temperature baseplate) in the same environment that the step stress was conducted at. After rest, the devices showed near complete recovery in the IV-FOC (Fig. 6 green curve) and no change seen in the transfer curve. After rest, a white light (see Section 2) was shined on the devices for a total time of 5 min, after which the devices were electrically characterized; this showed the devices fully recovered from the trap degradation seen (Fig. 6 and 7 purple curve). This showed there was no permanent degradation due to the constant-power
Key parameters
Pre
Post
Rest
Light
Idss (mA) VKnee (V)
73.40 3.40
69.75 3.50
73.45 3.45
73.65 3.45
drain voltage step-stress at the expected hot electron stressing conditions. When taking in consideration some of the key electrical parameters quantified from the electrical characterization test, the changes observed are dependent on when the characterization test was performed, which is attributed to fast acting trap recovery. Comparing the change seen in Idss, when recorded from the IV-FOC data (Table 2), shows a delta of 5%. Associating the change seen in Idss, when recorded from the transfer curve data (Table 1), shows a delta of 1% due to the trap not being fully reset, yet recovering. Calculating the percent change after rest and after light exposure shows a delta nearly 0% from both the IV-FOC data and transfer curve data, indicating a fully reset trap. 4. Conclusion Hot electron stressing using known and reported stress conditions was conducted on a commercial foundry level sample lot of devices to evaluate the extent of hot electron degradation. At nominal operating conditions and highly elevated drain voltages up to 200 V and gate–drain average electric field 40 V/lm (based on nominal 5 lm gate to drain gap) for source connected field plate devices and 100 V for ones unprotected by this field plate, temporary changes from fast-resetting traps were observed, but no permanent degradation from hot electron stress was observed. This is in contrast to reports of significant degradation at 20–30 V and gate–drain average electric field of roughly 5.9–15 V/lm and demonstrates the fundamental limitations of the GaN materials
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system in either voltage or peak field from hot electron stress have not been reached. Acknowledgements The authors wish to thank the High Reliability Virtual Electronics Center (HiREV) for funding and helpful discussions and the Reliability of Electronics Devices – Failure Analysis and Characterization Laboratory (RED-FALCon) for test support. References [1] Meneghini M, Stocco A, Silvestri R, Meneghesso G, Zanoni E. Degradation of AlGaN/GaN high electron mobility transistors related to hot electrons. Appl Phys Lett 2012;100:233508. [2] Chynoweth AG. Ionization rates for electrons and holes in silicon. Phys Rev 1958;109(5):1537–40. [3] Zhang Y, Singh J. Monte Carlo studies of two dimensional transport in GaN/ AlGaN transistors: comparison with transport in AlGaAs/GaAs channels. J Appl Phys 2001;89(1):386–9. [4] Shur MS. GaN based transistors for high power applications. Solid-State Electron 1998;42:2131–8. [5] Christou A, Fantini F. Introduction to the special issue on GaN and related nitride compound device reliability. IEEE Trans Dev Mater 2008;8(2):239.
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