High performance low temperature solution-processed zinc oxide thin film transistor

Thin Solid Films 519 (2011) 5623–5628

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Thin Solid Films j o u r n a l h o m e p a g e : w w w. e l s ev i e r. c o m / l o c a t e / t s f

High performance low temperature solution-processed zinc oxide thin film transistor R. Theissmann, S. Bubel, M. Sanlialp, C. Busch, G. Schierning, R. Schmechel ⁎ Faculty of Engineering and Center for NanoIntegration Duisburg-Essen (CeNIDE), University of Duisburg-Essen, Bismarckstr. 81, D-47057 Duisburg, Germany

a r t i c l e

i n f o

Article history: Received 17 April 2010 Received in revised form 17 February 2011 Accepted 22 February 2011 Available online 2 March 2011 Keywords: Printable electronics Deposition from Solution Zinc oxide Thin film transistor Transparent conducting oxide

a b s t r a c t Amorphous zinc oxide thin films have been processed out of an aqueous solution applying a one step synthesis procedure. For this, zinc oxide containing crystalline water (ZnO⋅ × H2O) is dissolved in aqueous ammonia (NH3), making use of the higher solubility of ZnO⋅ × H2O compared with the commonly used zinc oxide. Characteristically, as-produced layers have a thickness of below 10 nm. The films have been probed in standard thin film transistor devices, using silicon dioxide as dielectric layer. Keeping the maximum process temperature at 125 °C, a device mobility of 0.25 cm2V− 1s− 1 at an on/off ratio of 106 was demonstrated. At an annealing temperature of 300 °C, the performance could be optimized up to a mobility of 0.8 cm2V− 1s− 1. © 2011 Elsevier B.V. All rights reserved.

1. Introduction As a potential low-cost alternative for traditional inorganic semiconductor processing, printing of electrical circuits is gaining importance. Printed devices such as radio frequency identification tags or active flat panel displays require high performance thin film transistors (TFTs) preferably processed at low manufacturing temperatures. Stability in air as well as transparency are further specifications which would reduce integration costs and open the market of display electronics. The first TFT based on an organic semiconductor (polythiophene) was demonstrated in the mid 1980s with a field effect mobility (μFE) of around 10− 5 cm2V− 1s− 1 and opened the idea of low temperature processed TFTs [1]. Nowadays, mobilities of organic p-type TFT-devices are in the range of 0.5 cm2V− 1s− 1, realized using selforganized and aligned layers with partly crystalline domains of conjugated p-type polymers making a 2-dimensional transport possible [2,3]. Even though the mobility of n-type organic devices generally is inferior to p-type devices, an optimization of the interface between dielectric layer and semiconductor lead to n-type polymer transistors with a mobility of 10− 3 to 10− 2 cm2V− 1s− 1 [4] and also exceeding 0.5 cm2V− 1s− 1 [5]. Nonetheless, the transport properties of functional organic compounds can hardly compete against those of inorganic semiconductors, even if the latter are used in a low crystalline quality. Thus, there are considerable efforts to make inorganic materials printable.

⁎ Corresponding author. Tel.: +49 203 379 3347; fax: +49 203 379 3268. E-mail address: [email protected] (R. Schmechel). 0040-6090/$ – see front matter © 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2011.02.073

For this, function-carrying nanoparticles are stabilized in dispersions and used as inks for printing processes. After depositing the ink on a substrate, the solvent evaporates and the particles remain loosely packed in a thin film. First n-type all-inorganic printable thin film transistors used cadmium selenide (CdSe) nanoparticles as semiconductor [6] and reached a mobility of 1 cm2V− 1s− 1. Devices with active layers made of lead selenide (PbSe) [7] and mercury telluride (HgTe) [8] nanoparticles were realized. Albeit successful proof-of-principle, the introduction of such devices into a mass market is not unproblematic because of environmental concerns. Against this background, zinc oxide (ZnO) is attracting attention as an environmentally friendly, conditionally air stable and transparent semiconductor for both, high-end electronic applications as well as the low cost sector. Field effect mobilities of sputtered ZnO thin films are commonly around 20–30 cm2V− 1s− 1 [9,10], but values up to 70 cm2V− 1s− 1 have also been reported [11]. Single nanowire transistors of ZnO show mobilities between 30 cm2V− 1s− 1 [12] and up to 96 cm2V− 1s− 1 [13]. The combination of single ZnO nanowires with organic electronics demonstrated basic operation of a hybrid solar cell [14]. For low cost electronics, attempts have been made to develop solution-based deposition techniques and the corresponding precursor chemistry for ZnO thin films in order to demonstrate the feasibility of printing processes. Solution processed thin film transistor devices [15–19] or ultraviolet photodetectors [20] have been demonstrated. Their performance still is competitive with amorphous silicon. Volkman et al. [15] used dispersions of ZnO nanoparticles. Dense ZnO layers were obtained by spin coating and annealing, yielding device mobilities of 0.2 cm2V− 1s− 1. Sun and Sirringhaus [16] similarly produced ZnO-nanoparticles and nanorods in stable dispersions. After layer formation and additional hydrothermal ZnO-growth,

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devices showed a mobility around 0.6 cm2V− 1s− 1. There are also several approaches for solution-based process with liquid precursors, without the intermediate step of nanoparticle formation. Bashir et al. [19] solved a zinc acetate dihydrate precursor directly in methanol. Layer formation by spray pyrolysis was combined with varying substrate temperatures up to 600 °C. Device performance was optimized to best values of the mobility of μ = 15 cm2V− 1s− 1. Li and co-workers [17] used an aqueous solution of zinc nitrate, hexamethylenetetramine, and water. For layer formation, they heated the sample within the solution. Using a bottom gate device structure with a high-k dielectric layer, a device mobility of 0.56 cm2V− 1s− 1 was shown. Meyers and co-workers [18] also used zinc nitrate as precursor. It was solved in a strong base, NaOH, to form the hydroxide Zn(OH)2. The supernatant was removed by centrifugation and the precipitate re-suspended in H2O. This procedure was repeated several times to reduce the concentration of ions. The obtained product was dissolved in ammonia, NH3(aq). Layer formation was done by spin coating, followed by an annealing step. Mobilities between 0.4 and 6 cm2V− 1s− 1 were shown, depending on annealing temperature and the type of the dielectric layer. Common of the cited work is that the preparation of the zinc precursor solution usually requires several steps of purification or substrate temperatures which are too high to be compatible with flexible substrates. Here we show that the time-consuming purification procedure can be overcome by the use of a zinc oxide hydrate (ZnO ⋅ × H2O) precursor which has a sufficient solubility in ammonia due to the crystal water. This leads most probably to a similar − x) + ammine-hydroxo zinc complex Zn(OH)x(NH3)(2 in aqueous y solution, as described by Meyers and co-workers [18], however in a simple one step procedure. This precursor solution can be transformed to amorphous ZnO-thin films at a temperature of 125 °C, well suitable for the purpose of printable electronics. Taking benefit of these properties, a simple one-step fabrication procedure for high performance low temperature solution-processed zinc oxide thin film transistors is demonstrated. 2. Experimental details The commercially available zinc oxide hydrate, ZnO ⋅ × H2O, of (Sigma-Aldrich, 97% purity), shows a sufficient solubility in NH3 which has its origin in the crystal-water. For the herein used thin films, the ZnO precursor solution was varied between 0.04 and 0.07 molar solution of ZnO ⋅ × H2O in NH3(aq) (Sigma-Aldrich, ≥99.99% purity, 28% in H2O). For most devices a 0.05 molar solution was used. The solution was kept at 40 °C under rigorous stirring for 48 h. This yielded a clear transparent liquid which was filtered using a 700 nm glass filter. The thin-film formation was carried out by spin coating at 3000 rpm followed by an annealing step for 60 min in ambient atmosphere to convert the ZnO precursor. The annealing temperature was varied between 125 °C and 500 °C, with 125 °C being the standard annealing temperature. In order to improve the layer morphology and device performance the film forming step has been partially doubled (indicated in the text). For the device fabrication, phosphorus doped silicon wafers (3⋅ 1017 cm− 3) with thermally grown SiO2 of 200 nm thickness were used. Substrates were cleaned and made hydrophilic before spin coating. After the layer formation, source and drain aluminum electrodes were deposited by physical vapor deposition through a shadow mask. Electrode spacing was 100 μm and width 7.4 mm. The electrical characterization was carried out under the exclusion from ambient light in a nitrogen filled glovebox using a Keithley parameter analyzer 4200-SCS in combination with a probe station. In order to study the layer morphology, electron transparent lamellae of two transistor-samples were prepared using focused ion beam (FIB, FEI Helios Nanolab). A platinum layer was deposited on top of the devices using ion beam induced decomposition prior to the FIB sample preparation to protect the

device from the ion beam. The lamellae were investigated with an FEI Tecnai F20 equipped with an energy dispersive X-ray (EDX) system and a GIF2000 energy filter. Optical transmission was measured in an UV–VIS spectrometer Lambda 9 from Perkin-Elmer. 3. Results and discussion ZnO thin films were processed by spin-coating a 0.05 molar precursor solution of zinc oxide hydrate, ZnO ⋅ × H2O, in NH3 as described above onto Si/SiO2 substrates. Subsequently, the thin films were annealed at 125 °C under ambient conditions. Some of the devices were processed in a way, that the procedure of spin-coating and annealing was repeated. This double spin-coating procedure includes: spin-coating a precursor solution onto a Si/SiO2 substrate, annealing at 125 °C, spin coating the same precursor solution a second time onto the already processed ZnO layer, and annealing at 125 °C. The film morphology was exemplarily investigated by transmission electron microscopy (TEM) on a FIB lamella prepared from a ZnO transistor produced by double spin coating and annealing at 125 °C. Fig. 1a shows a TEM image of the stack. The active layer (ZnO) together with the gate oxide (SiO2) and one of the electrodes (Al) can be distinguished. The ZnO layer is uniformly smooth over the whole lamella—several micrometers of the device could be investigated by TEM with no defects found whatsoever. The thickness of the ZnO thin film is around 7 nm, the thickness of the evaporated Al-contacts around 54 nm. Fig. 1b shows an energy filtered bright-field image of the same sample. Part c shows an EDX line scan over the stacked layers. The very sharp Zn-signal can again be assigned to a layer thinner than 10 nm. An additional X-ray diffraction investigation was carried out (not shown), where an amorphous film was found. Fig. 1d shows the cross section of a transistor sample after single spin-coating and annealing at 500 °C. A ZnO crystallite of a size larger than 20 nm is shown, the presence of ZnO crystallites was observed along the whole lamella. The transistor characteristics of two different devices are shown in Fig. 2. In Fig. 2a and b, the ZnO thin film was processed by a single spin coating step of the 0.05 molar precursor solution as described above and subsequent annealing at 125 °C. For the transistor characteristics shown in Fig. 2c and d, the active layer was obtained by doubling the procedure (spin coating, annealing at 125 °C, spin coating, annealing at 125 °C). A clear enhancement mode for positive gate bias and linear progression in the saturation regime combined with a moderate hysteresis is demonstrated for both devices. By doubling the spin coating and annealing, a higher drain current, less hysteresis, and a clear reduction in threshold voltage is yielded compared to the singly spin coated sample. The mobility μFE was derived from the transfer characteristics in Fig. 2b and d, respectively. In the linear regime with the drain current Ilin, the curves were fitted to the Eq. (1): ∂Ilin = μ FE g ðVD −xÞ: ∂VG

ð1Þ

The factor g contains the gate dielectric capacitance and the electrodes geometry, x denotes the x-axis shift, while VG and VD are the applied gate and drain voltages. For the saturation regime (subscript sat) at higher source-drain bias, the square root plot of the drain current was fitted to the Eq. (2) with the drain current Isat and the threshold voltage Vth: pffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffi ∂ Isat = μ sat g ðVG −Vth Þ: ∂VG

ð2Þ

Table 1 summarizes the obtained data for the two devices shown in Fig. 2. It can be seen that by doubling the layer formation step, μFE can be increased significantly from μFE = 0.12 cm2V− 1s− 1 (single

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Fig. 1. TEM images of cross sections prepared from two different ZnO-TFTs: (a) TEM image showing the stack of Si, SiO2, ZnO, Al layers annealed at 125 °C; (b) energy filtered bright-field image of the same stack; (c) EDX-line-scan verifying the composition and approximate thickness of the ZnO-layer; Fig. 2(c) and (d) give the electric characteristics of the transistor shown in (a)–(c); (d) bright-field image of a transistor annealed at 500 °C, showing a ZnO crystallite of the size of more than 20 nm.

layer) to μFE = 0.25 cm2V− 1s− 1 (double layer), while the threshold voltage Vth was lowered likewise from 58 V to 30 V and the on/off ratio increased from 104 to 106. The increase in performance by doubling the spin-coating and annealing procedure could therefore be due to an improved layer morphology in terms of density and interface smoothness. Since the TFTs operate in an accumulation mode, charge transport occurs mainly close to the gate-dielectric interface. Trap-states are usually responsible for (a) a lowered mobility, since the charge carriers get partially trapped during transport, (b) an increased threshold voltage, due to the requirement to fill-up deep trap states before transport can take place, and (c) an enhanced hysteresis, due to a longer relaxation time of the system. Comparing the results in Fig. 2 one can conclude therefore, that doubling of the coating process lowers the number of trap states close to the transport channel and improves the film density. Therefore, a single film coating process leads most probably to a laterally inhomogeneous ZnO film, trap-states on the ZnO surface are very close to the accumulation channel, affecting the charge transport negatively. The second coating step will improve the lateral homogeneity, making the ZnO film denser and moving trap-states at the ZnO surface farer away from the critical transport channel. A similar effect was observed by Tellier et al. [21]. The authors repeatedly formed 3 to 5 nm films from a zinc acetate dihydrate precursor solution. They report a better density and morphology of the doubled layer rather than just an increase in film thickness. The thin film transistor devices were further optimized regarding the precursor concentration in the NH3 solution. For this series, devices were fabricated by varying the concentration of the precursor solution from 0.04 to 0.07 mol/l, while keeping all other parameters constant and the annealing temperature at 125 °C. A single spin

coating procedure was performed for this series of devices. The results of this optimization are shown in Fig. 3a and b. Layer formation with solutions of a concentration less than 0.045 mol/l was not successful. The solubility limit of ZnO⋅ × H2O in NH3 was reached for concentrations higher than 0.073 mol/l so that the process of layer formation was not applicable for higher concentrations, either. If a 0.0625 molar solution is used for the ZnO precursor, a further increase in μFE can be obtained up to a value of μFE = 0.26 cm2V− 1s− 1 (compare Fig. 3a). The threshold voltage decreases with increasing concentration of the precursor solution. Using the 0.0625 molar solution, the device showed a threshold voltage of 46 V and an on/off ratio of 1 × 106. The effect of solution concentration on the device performance is similar as the difference between a single and a double coating process. As the produced ZnO thin films have a high content of solvent, it is reasonable that higher concentrations of the precursor solution result in a slightly higher density of the layer and thus in an improved performance. This is seen for concentrations up to 0.073 mol/l (Fig. 3a and b). With decreasing concentration, the transistor characteristics indicate more influence of trap states (reduced mobility and increased threshold voltage). As discussed before, this may be the result of a laterally less homogeneous film. The lower limit is achieved at a concentration of less than 0.045 mol/l, where the mobility drops down by several orders of magnitude indicating that small and mainly no longer percolating ZnO islands are formed. The other limit is given by the solubility. For concentrations higher than 0.073 mol/l homogeneous film formation is not possible. A comparably high scattering of the data of this series occurs because of the uncertainty of the initial weighting of the ZnO⋅ × H2O and NH3. Other series of optimization presented in this paper with a constant precursor concentration have been processed from the same solution, accompanied with less data scattering.

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Fig. 2. Output and transfer characteristics of ZnO bottom gate transistors on standard Si/SiO2(200 nm) devices, employing Al source/drain contacts. Layers were formed using a 0.05 molar precursor solution and 125 °C annealing in air. Layer formation: (a) and (b) by a single spin coating process and subsequent annealing; (c) and (d) by spin coating and annealing twice.

In a second series, the annealing temperature was optimized. Higher annealing temperatures generally can be applied to improve the transistor characteristics of solution processed ZnO thin film transistor devices [18,19]. The device parameters of several TFTs obtained by a variation of the annealing temperature are shown in Fig. 3c and d. All samples were temperature treated in air. Precursor concentration was kept at 0.05 mol/l for this series of devices. The increase of device performance with higher annealing temperature up to the maximum of 300 °C can be explained by the effusion of gaseous products of the precursor dissociation, mainly H2O and NH3 [22]. The improvement of mobility and decreasing threshold voltage with increasing annealing temperature indicates a reduction of trap-states within the transport channel. At around 300 °C, a maximum mobility of around 0.8 cm2V− 1s− 1 together with a minimum threshold voltage of around 40 V was found. Annealing temperatures higher than 300 °C did not further optimize the devices and temperatures above 350 °C reduce the device mobility to values below 10− 2 cm2V− 1s− 1. This sudden drop of mobility indicates essential changes in the film morphology. A crystallization of an amorphous ZnO thin film above 350 °C was reported by O'Brien et al. [23]. This crystallization is accompanied by a Table 1 Parameters obtained from TFTs processed by single or double spin coated thin film transistors. Annealing temperature TAnnealing in °C, concentration csolution of the precursor solution in mol/l, Mobility μFE and μsat in cm2V− 1s− 1, threshold voltage Vth in V (the turn-on voltage Von in round brackets).

Single layer Double layer Single layer Single layer

TAnnealing

csolution

μFE

μ sat

Vth(Von)

On/off

125 125 125 300

0.050 0.050 0.063 0.050

0.12 0.25 0.26 0.82

0.10 0.19 0.20 0.67

58 (50) 30 (8) 46 (26) 41 (9)

4 × 104 1 × 106 1 × 106 3 × 104

suddenly decreasing conductivity. We assume that a beginning crystallization of the amorphous ZnO film, which is going along with a decreasing smoothness and homogeneity, is the reason for the abrupt decrease of our device performance. To demonstrate this, a device annealed at 500 °C was investigated by TEM. A ZnO layer containing a large ZnO crystallite – compared to the initial layer thickness – is shown in Fig. 1d. This finding was characteristic for this sample and demonstrates the occurring crystallization. Data from both optimization series, precursor concentration and annealing temperature, are included in Table 1. Table 2 gives a compilation of device characteristics of ZnO-TFTs published in literature. Data was selected for devices which were fabricated using comparable standard device geometry and low temperature processes. It can be seen that this work's transistor characteristics gives competitive performance in the low temperature range (125 °C), but using a simple one-step synthesis and comparably low process temperatures, while the process of Meyers et al. [18] shows a slightly higher performance, when processed at slightly higher temperatures (150 °C). Further, the ZnO thin film used in our devices is considerably thinner than in comparable TFTs reported in literature. For instance, Meyers et al. [18] have worked with an 80 nm thick active layer. At higher process temperatures (300 °C), other fabrication routes [18,19] are advantageous. Together with the very small ZnO layer thickness, it is an additional feature of the applied thin film processing technique that the active layer is perfectly transparent in the visible range. For a measurement of the optical transmission, a ZnO layer was fabricated on a hydrophilic quartz glass substrate with otherwise identical processing parameters. In the transmission spectrum shown in Fig. 4a, no detectable absorption can be seen in the visible spectrum, whereas the absorption at 350 nm can be attributed to the free exciton

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Fig. 3. (a) and (b) mobility and threshold voltage of TFT devices processed with different molar ratio of ZnO⋅ × H2O in NH3(aq) annealed at 125 °C. (c) and (d) mobility and threshold voltage of devices processed from constant 0.05 molar precursor at different annealing temperatures.

absorption known from crystalline ZnO. Fig. 4b shows the sample with the ZnO thin film processed on a quartz glass. 4. Conclusion Concluding, we have demonstrated an exceedingly simple way of fabricating amorphous ZnO thin film transistors out of a precursor Table 2 Compilation of literature data on solution or dispersion processed ZnO-TFTs. Standard device geometry with bottom gate Si/SiO2 substrates and low temperature processed TFT data are collected only. Thickness dSiO2 of SiO2 in nm, maximum process temperature Tmax in ∘C, μ in cm2V− 1s− 1. Author

dSiO2

Tmax

μ

On/off

Volkman [15] Sun [16] Meyers [18]

100 300 100 100 100 200 200

400 230 150 200 300 200 300

0.2 0.6 0.4 0.7 4.3 0.1 3.7

103 105 106 106 106 105 105

Bashir [19]

Fig. 4. (a) UV–VIS spectrum of the solution-processed ZnO thin film on quartz glass; (b) photograph of the same sample. The sample is fully transparent in the visible spectrum.

based solution process, which shows competitive performance if produced at low temperatures. The ZnO layer is dense and has a total thickness of approximately 7 nm. The low annealing temperature of 125 °C is compatible with flexible polymer substrates. Full transparency in the visible spectrum is an additional feature of the produced thin film. Enhancement mode for positive gate bias and linear progression in the saturation regime have been demonstrated for a standard device geometry. A mobility of 0.25 cm2V− 1s− 1, a threshold voltage around 30 V, and an on/off ratio of 106 were obtained. Acknowledgments Financial support of the Deutsche Forschungsgemeinschaft (DFG) within the collaborative research center SFB 445 as well as of the Dutch Polymer Institute (DPI) is gratefully acknowledged. Professor M. Farle is gratefully acknowledged for providing access to his transmission electron microscopy facility and Professor A. Lorke for providing access to the focused ion beam. References [1] A. Tsumura, H. Koezuka, T. Ando, Appl. Phys. Lett. 49 (1986) 1210. [2] H. Sirringhaus, N. Tessler, R.H. Friend, Science 280 (1998) 1741. [3] H. Sirringhaus, P.J. Brown, R.H. Friend, M.M. Nielson, K. Bechgaard, B.M.W. Langeveld-Voss, A.J.H. Spiering, R.A.J. Janssen, E.W. Meijer, P. Herwig, D.M. de Leeuw, Nature 401 (1999) 685. [4] L.-L. Chua, J. Zaumseil, J.-F. Chang, P.K.-H. Ou, E.C.-W. Ho, H. Sirringhaus, R.H. Friend, Nature 434 (2005) 194. [5] H. Yan, Z. Chen, Y. Zheng, C. Newman, J.R. Quinn, F. Do, M. Kastler, A. Facchetti, Nature 457 (2009) 679. [6] J.M. Jacobson, B.A. Ridley, B. Nivi, Science 286 (1999) 746. [7] D.V. Talapin, C.B. Murray, Science 310 (2005) 86. [8] D.-W. Kim, H.-R. Lee, H. Kim, K. Cho, S. Kim, Appl. Phys. Lett. 89 (2006) 173107. [9] E. Fortunato, P. Barquinha, A. Pimentel, A. Gonçalves, A. Marques, L. Pereira, R. Martins, Thin Solid Films 487 (2005) 205. [10] B. Souharce, H. Thiem, U. Scherf, S. Allard, M. Forster, Angew. Chem. Int. Ed. 47 (2008) 4070. [11] E. Fortunato, A. Pimentel, L. Pereira, A. Gonçalves, G. Lavareda, H. Aguas, I. Ferreira, C.N. Carvalho, R. Martins, J. Non-Cryst. Solids 338 (2004) 806. [12] K. Keem, D.-Y. Jeong, S. Kim, Nano Lett. 6 (2006) 1454.

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