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HTS-SFQ ring oscillator circuit fabricated with a novel multilayer structure
Physica C 392–396 (2003) 1433–1440 www.elsevier.com/locate/physc
HTS-SFQ ring oscillator circuit fabricated with a novel multilayer structure H. Katsuno *, T. Nagano, K. Nakayama, J. Yoshida Corporate R&D Center, Toshiba Corporation, 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki 212-8582, Japan Received 13 November 2002; accepted 25 March 2003
Abstract A novel multilayer structure composed of a NBCO groundplane and stannate isolation layers was fabricated in order to improve the quality of Josephson characteristics and wiring layers on a buried groundplane. The fabricated junctions exhibited high magnetic modulation of Ic exceeding 90% and an Ic Rn product of 0.75 mV at 30 K. The sheet inductances of the counter-electrode and the base-electrode wiring were 1.1 and 1.3 pH, respectively, nearly independent of a temperature ranging from 20 to 30 K. We also fabricated an HTS-SFQ ring oscillator circuit including 21 junctions by adopting this novel multilayer and confirmed a proper operation of the ring oscillator at 20–30 K. The maximum output voltage of the ring oscillator was observed to be 0.06 mV at 30 K and 0.12 mV at 20 K, indicating the signal delay time per stage to be 3.4 and 1.8 ps, respectively. Ó 2003 Elsevier B.V. All rights reserved. PACS: 85.25.Hv; 85.25.Am Keywords: Interface engineered junction; NdBa2 Cu3 O7d ; Stannate; SFQ circuit; Ring oscillator
1. Introduction The interface engineered junction (IEJ) introduced by Moeckly and Char [1] is the most promising candidate for the construction of ultrahigh-speed circuits utilizing a single flux quantum (SFQ) as an information carrier [2], because IEJs are expected to satisfy the requirement of high uniformity for the circuit operation in terms of junction characteristics [3,4]. However, the thin
* Corresponding author. Tel.: +81-44-549-2110; fax: +81-44520-1801. E-mail address: [email protected] (H. Katsuno).
barrier layers of IEJs fabricated by damaging the base-electrode surface with ion bombardment and recrystallizing in an annealing process during the counter-electrode deposition are extremely sensitive to the annealing temperature. Because the critical current (Ic ) value appropriate to the operation of the SFQ circuit can be observed in a relatively low substrate temperature range during the counter-electrode deposition, this process temperature conflicts with complete c-axis oriented growth of the counter-electrode layer, especially when sputter-deposited YBa2 Cu3 O7d (YBCO) is used as the counter-electrode layer. In the previous paper [5], we adopted YbBa2 Cu3 O7d (YbBCO) as the counter-electrode layer because this material is known to exhibit
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complete c-axis oriented growth in a far wider temperature range than is possible with YBCO [6]. The junctions for which YbBCO was adopted as the counter-electrode layer exhibited excellent Josephson characteristics and appropriate Ic values for fabrication of SFQ circuits, maintaining the complete c-axis orientation of the counter-electrode layer. We also pointed out that the surface morphology of the insulator/base-electrode bilayer had a significant influence on the 1r-spread in Ic of the junctions fabricated on the ramp-edge of this bilayer. Recently, high-temperature superconducting (HTS) SFQ circuits without a groundplane have been investigated [7–9]. However, for the operation of the large-scale SFQ circuits, it is indispensable to reduce the inductance of the counter-electrode and base-electrode wiring by using a groundplane [10,11] insulated from these wiring layers except for the superconducting-contact area. A serious problem in such a multilayer is the degradation of the superconducting characteristics by increasing the number of stacked layers. The surface morphology of the insulator/groundplane bilayer is important in particular because it affects significantly the quality of the insulator/base-electrode bilayer. Our experimental results indicate that such rough surface of the insulator/groundplane bilayer results in uncontrollable junction characteristics and an unexpected increase of the sheet inductance of each superconducting wiring arising from decreasing Tc and Jc of each one. In this paper, we report a novel multilayer process to improve the surface morphology of the insulator/groundplane bilayer by selecting the ap-
propriate materials, and the successful operation of an SFQ ring oscillator.
2. Fabrication process At first, we adopted NdBa2 Cu3 O7d (NBCO) as the groundplane, because this HTS material is expected to improve surface morphology more effectively than YBCO, probably due to the formation of a solid solution system, Nd1þx Ba2x Cu3 O7d [12]. We confirmed that the average surface roughness (Ra ) of a 200-nm-thick NBCO film prepared on an LSAT(0 0 1) substrate by sputtering at a substrate temperature of 850 °C was below 1 nm as shown in Fig. 1(a). This value was better than that obtained for YBCO films with the same thickness by more than a factor of 2.5. The isolation layers in HTS-SFQ circuits are required to have a simple perovskite structure with reasonable lattice matching to HTS materials and a low dielectric constant. We selected CaSnO3 and SrSnO3 [13], whose dielectric constants were as low as 20, as the possible candidates. We found that CaSnO3 exhibited better surface morphology than SrSnO3 when deposited on NBCO films, whereas the situation was just the reverse on YBCO films. Therefore, we adopted CaSnO3 as the insulator on the groundplane, and SrSnO3 was used on the YBCO base-electrodes. The average surface roughness of a 500-nm-thick CaSnO3 /200-nmthick NBCO was below 1 nm as shown in Fig. 1(b), which was comparable to that of NBCO single layer. AFM observations also revealed that the surface of the bilayer contained few precipitates
Fig. 1. The AFM image of the NBCO groundplane film is shown in (a), and that of the CaSnO3 insulator/NBCO groundplane bilayer is shown in (b). Scanning areas are in the range of 20 lm 20 lm.
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Fig. 2. The schematic cross section of the multilayer structure consisting of NBCO groundplane and stannate isolation layer (CaSnO3 and SrSnO3 ).
as shown in Fig. 1(b); their relative area to the whole film surface was estimated to be below 0.01%. Fig. 2 shows the schematic cross section of the HTS-SFQ circuit. Ramp-edge junctions with YbBCO as the counter-electrode were formed on a buried NBCO groundplane, and the superconducting contacts between the base-electrode and the groundplane were provided through via holes in the CaSnO3 isolation layer. A 200-nm-thick NBCO groundplane was fabricated by sputtering at a substrate temperature of 850 °C. The asdeposited NBCO film exhibited a critical temperature (Tc ) exceeding 80 K and a critical current density exceeding 1 1011 A/m2 at 4.2 K. The groundplane was patterned by the two-step etching technique [14]. After depositing a 400-nm-thick CaSnO3 on the patterned groundplane, the superconducting contacts between the groundplane and the base-electrode layer were formed using a similar etching technique. A 200-nm-thick YBCO base-electrode layer and subsequently a 500-nmthick SrSnO3 isolation layer were deposited and the ramp-edge structure for IEJs was fabricated. Then, the sample was heated up to the temperature for the counter-electrode deposition in the sputtering chamber and maintained at that temperature for 10 min in an activated oxygen flux from an ECR plasma source. Successively, a 300-nm-thick YbBCO counter-electrode layer was deposited and the counter-electrode pattern was formed after
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covering the whole wafer surface with a 1-lmthick Au film. The resultant ramp-edge was formed at about 20° independent of the edge orientation in a wafer. After fabrication of the whole circuit structure, the sample was annealed at 600 °C in 1 atm. O2 for 12 h and cooled to the room temperature at a cooling rate of 0.1 °C/min to eliminate any possible damage to the superconducting layers in the fabrication process. This annealing process was effective for the YBCO base-electrode and the YbBCO counter-electrode layers as shown by their Tc exceeding 80 K. Unfortunately, however, the Tc of the NBCO groundplane remained at around 70 K and never reached the value of the as-deposited film.
3. Junction and film characteristics Fig. 3 shows typical current–voltage characteristics at 4.2 and 30 K for 4-lm-width junction on a buried groundplane. The junction displays weak hysteretic behavior below 20 K and the RSJ characteristics. The magnetic-field modulation of Ic exceeded 90% and the excess current was less than 10%, indicating a barrier structure without pin-holes. This sample was fabricated under the condition that was expected to give the Ic value of
Fig. 3. The I–V characteristics at 4.2 and 30 K on a buried groundplane.
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0.4 mA at 30 K. Although fabricated junctions exhibited slightly lower Ic value such as 0.3 mA as shown in Fig. 3, the Ic Rn product of 0.75 mV was satisfactory. According to the experimental results of junction array fabricated by using the above multilayer process, the 1r-spread in Ic was estimated to be 10–20% at 4.2 K. The problem of the 1r-spread in Ic remained even after adopting the novel multilayer process. Fig. 4 shows the temperature dependence of the sheet inductance (Ls ) of both counter-electrode and base-electrode layers on the groundplane. Each Ls was evaluated from SQUID modulation at strip lines of various lengths. The sheet inductance values of the counter- and the base-electrodes were 1.1 and 1.3 pH, respectively, nearly independent of the temperature ranging from 20 to 30 K for the operation of the HTS-SFQ circuit. These sheet inductance values of both electrodes fabricated by the novel multilayer were almost the same or slightly larger than those of the other reports [4,10]. The low transmissivity of oxygen in CaSnO3 resulted in the relatively low Tc of the NBCO groundplane such as 70 K and the sharp increase of Ls near Tc of the groundplane. According to the result for the as-deposited NBCO film exhibiting high Tc value, the superconducting characteristics of the NBCO groundplane are ex-
pected to be improved by the optimization of the annealing condition or the fabrication of the hole in the CaSnO3 /NBCO bilayer for the oxygen transmission, resulting in the improvement in the sheet inductance of both electrodes of less than 1.0 pH at the measurement temperature. We confirmed that the experimental data in Fig. 4 could be well fit to the conventional theoretical expression for a superconducting microstrip line by assuming the empirical temperature dependence of the London penetration depth in HTS materials given by Eq. (1) [15,16] by using the least squares method: p 1=2
kðT Þ=kð0Þ ¼ ð1 ðT =Tc Þ Þ
;
p¼2
ð1Þ
The penetration depths of the counter-electrode, base-electrode and groundplane can be estimated to be 170, 230 and 360 nm at 30 K, respectively. These results imply that the novel multilayer process simultaneously satisfies junctions and wiring characteristics for the operation of HTSSFQ circuits [17], indicating that this novel multilayer is appropriate for the fabrication of HTSSFQ circuits.
4. Ring oscillator operation 4.1. Ring oscillator structure
Fig. 4. The sheet inductance values of the counter- and the base-electrodes on a buried groundplane as functions of the temperature. The solid lines are fit by (1).
We have fabricated an SFQ ring oscillator circuit for estimating a signal delay per stage and a bit error rate of SFQ circuit [18]. In this paper, we have demonstrated the operation of the SFQ ring oscillator circuit elements and estimated a signal delay per stage in the ring oscillator. Fig. 5(a) shows the SEM image of the ring oscillator, and its equivalent circuit is shown in (b). This circuit consists of a dc/SFQ converter including a junction generating an SFQ pulse (J1 ) and an escape junction (Je ), a SQUID detecting an SFQ pulse generation, a Josephson transmission line (JTL), a confluence buffer and a ring oscillator. The ring oscillator is composed of 10-stage JTL with a closed-loop configuration containing an SFQ balanced comparator. Eight current sources (from source-I to source-III and from source-A to source-E) are used independently to supply the
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4.2. dc/SFQ converter
Fig. 5. The SEM image of the SFQ ring oscillator circuit is shown in (a), and its equivalent circuit is shown in (b). Eight current sources (from source-I to source-III and from source-A to source-E as shown in (b)) are used to supply the junctions in the whole circuit.
bias currents to the junctions of this whole circuit, as shown in Fig. 5(b). The SFQ pulse generated at the dc/SFQ converter is injected into the ring oscillator through the JTL and the confluence buffer. The dc/SFQ converter also generates an anti-flux in the loop including the detecting SQUID. It is possible independently of the other circuit elements to know whether the dc/SFQ works correctly or not, by detecting the SQUID voltage. The SFQ pulse injected into the ring oscillator rotates in the circuit until an additional current (comparator input as shown in Fig. 5(b)) is supplied to the balanced comparator. The ring output voltage can be detected among the junctions of JTL as shown in Fig. 5(b). The circulation frequency f of the SFQ pulse is determined from f ¼ V =U0 ; V is a dcvoltage that appears at the ring oscillator and U0 denotes the flux quantum (h=2e).
In the case of the correct operation for the dc/ SFQ converter, J1 generates both a flux injected into the ring oscillator and an anti-flux trapped in the left-hand loop of J1 in Fig. 5(b). Then, the antiflux escapes from Je by the opposite input current. Fig. 6 shows the experimental results of the dc/ SFQ converter operation at 30 K measured by changing the input current and the bias current (source-I shown in Fig. 5(b)). The sample was measured in a helium Dewar insert with three mumetal shields. The solid circles correspond to the characteristics with a trap of one flux, which was generated by the input current into a loop including the detecting SQUID. The open circles are the result in the case of disappearance of the trapped flux from the loop by the opposite input current. From the slope of the experimental data, it is possible to know which junctions generate fluxes because the slope can be determined just by the rate of the currents injected into two junctions that are fixed by the inductance of the wiring layer including the nonlinear term of the junctions. In the low-bias-current region in Fig. 6, the open circles show a similar slope to that indicated by the solid circles, indicating that J1 generates the fluxes
Fig. 6. The relation between the input current and the bias current of source-I as shown in Fig. 5(b), at 30 K. The solid circles are the result in the case of a trap of one flux in a loop including the detecting SQUID by the input current. The open circles are the result in the case of a disappearance of the trapped flux from the loop by the opposite input current.
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incorrectly. This method is available to probe the circuit operation easily; however, it is difficult to know whether the fluxes are trapped in the JTL loops or not, resulting in the uncertain Ic value of the generated junctions. In any case, the result in Fig. 6 indicates that it is possible to inject the SFQ pulse into the ring oscillator by controlling the input current. 4.3. Ring oscillator operation at 30 K Fig. 7 shows the experimental result for the ring oscillator operation at 30 K. The bias currents were adjusted to maximize the output voltage of the ring oscillator. When a positive-input current was supplied to the dc/SFQ converter, an output voltage appeared at the detecting SQUID, indicating the generation of the one SFQ pulse from the dc/SFQ converter. The SQUID voltage remained even after returning the input current to zero and disappeared by the successive negative one, as expected for the correct operation of the input current. The SFQ pulse generated in the dc/ SFQ converter transferred into the ring oscillator, resulting in the generation of the ring-output voltage. By supplying the additional current signal
Fig. 7. The experimental result for the ring oscillator operation at 30 K. The scale of each result is the following value; 0.5 mA/ div for input current, 0.2 mV/div for SQUID output, 1 mA/div for comparator input and 0.1 mV/div for ring output.
to the balanced comparator, the ring oscillator was returned to the initial state of the zero-output voltage, confirming the correct operation of the ring oscillator as designed. The maximum dc-output voltages of the ring oscillator were 0.06 mV at 30 K and 0.12 mV at 20 K, respectively. These values indicate the circulation frequency of SFQ to be 29 GHz at 30 K, and were increased up to 57 GHz at 20 K. Thus, the signal delay per stage in the ring oscillator can be estimated to be 3.4 ps at 30 K and 1.8 ps at 20 K. The rapid decrease in the output voltage by increasing the temperature cannot be ascribed to the decrease in the Ic Rn product value within this temperature range, and requires more detailed analysis including the variation in the Ic values of the junctions in the circuit. 4.4. Temperature dependence of the ring-output voltage Fig. 8 shows the relation between the bias current (source-B shown in Fig. 5(b)) and the output voltage observed for the ring oscillator at various temperatures between 20 and 30 K with and without the SFQ pulse injection. The solid lines
Fig. 8. The relations between the output voltage of the ring oscillator and the bias current (source-B shown in Fig. 5(b)) at various temperatures from 20 to 30 K. The solid lines are the experimental data for the self-oscillation without the SFQ pulse injection, and the dotted lines correspond to the characteristics with the SFQ pulse injection.
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correspond to the self-oscillation without the SFQ injection, and the dotted lines are the result in the case of the proper oscillation with the SFQ injection. The differences between the dotted and the solid lines at the zero-output voltage represent the bias margin for current source-B at each temperature. It can be seen that the bias margin shrinks rapidly with increasing the temperature. The relations between output voltage of the ring oscillator and the other current sources (source-C, source-D and source-E shown in Fig. 5(b)) are almost the same as for Fig. 8 with respect to the temperature dependence of the bias margin. For simplicity, we assume that the bias current is supplied equally to each junction in the ring oscillator. In the case without the SFQ pulse, the threshold at which the ring oscillator starts the self-oscillation is determined by the lowest Ic (Ic min ) value of the junctions constituting the ring oscillator. On the other hand, by assuming a circulating current to be a simple expression U0 =L in each JTL constituting the ring oscillator, the threshold of the proper oscillation by the injection of the SFQ pulse could be approximately represented as Ic max U0 =L, where Ic max is the highest Ic of the junctions in the ring oscillator and L is the loop inductance in each stage of the JTL constituting the ring oscillator. As a result, the bias margin could be given as U0 =L ðIc max Ic min Þ. This simple analysis clearly shows that the variation of the Ic value results in the serious decrease in the bias margin. According to this model, the temperature dependence of the bias margin seen in Fig. 8 can be ascribed to the term of Ic max Ic min because the temperature dependence of L is sufficiently weak between 20 and 30 K. The temperature dependence of Ic on the same wafer is expected to show the same feature on the whole because the barrier structures of such junctions are almost the same after passing through the same fabrication process. However, there is a possibility that there are some junctions exhibiting relatively large Ic with low magneticfield modulation. The results of our experiments obtained on the same wafer with the ring oscillator indicate that the temperature dependence of such junctions is weaker than that of high magneticfield modulation exhibiting strong temperature dependence of Ic . We tried to explain the shrinking
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of the bias margin with increasing the temperature by the circuit simulation. However, it is difficult to simulate and fully understand the experimental results because of the deviation from the design for the balance in Ic and the difficulty in confirming the characteristics of all junctions constituting the ring oscillator. Further improvement in reproducibility of the Ic value is necessary even after adopting the multilayer structure proposed in this paper, in order to discuss the performance and the prospect for high-temperature and ultra-highspeed operation of HTS-SFQ circuits in more detail.
5. Summary A novel multilayer available for the HTS-SFQ circuit was fabricated by adopting a NBCO groundplane and stannate isolation layers that show excellent surface morphology with Ra below 1 nm. The junction characteristics of IEJs using the novel multilayer exhibited the magnetic modulation of Ic exceeding 90% and nearly appropriate Ic value of about 0.3 mA at 30 K. The sheet inductances of the counter-electrode and the baseelectrode wiring were 1.1 and 1.3 pH, respectively, within a temperature ranging from 20 to 30 K. It is possible to reduce the sheet inductance of less than 1.0 pH by improving the superconducting characteristics of the groundplane. We also demonstrated the operation of the ring oscillator composed of 10-stage JTL with a closed-loop configuration at 20–30 K. The maximum output voltage of the ring oscillator was 0.06 mV at 30 K and 0.12 mV at 20 K. From these values, the circulation frequency of SFQ was calculated to be 29 GHz at 30 K and was increased up to 57 GHz at 20 K. Therefore, the delay time per stage can be estimated to be 3.4 ps at 30 K and 1.8 ps at 20 K, respectively. It was also pointed out that the large variation in Ic of the junctions constituting the ring oscillator resulted in the shrinking of the bias margin. Although the novel multilayer that improved the surface morphology of insulator/ groundplane bilayer satisfied the characteristics of junctions and superconducting wiring appropriate for the fabrication of SFQ circuits, it would be
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necessary to analyze the electric properties and crystal structure of IEJs to further improve the 1rspread in Ic . Acknowledgements This work was supported by the New Energy and Industrial Technology Development Organization (NEDO) as Collaborative Research and Development of Fundamental Technologies for Superconductivity Applications. References [1] B.H. Moeckly, K. Char, Appl. Phys. Lett. 71 (1997) 2526. [2] K.K. Likharev, V.K. Semenov, IEEE Trans. Appl. Supercond. 1 (1991) 3. [3] D.L. Miller, J.X. Przybysz, J.H. Kang, IEEE Trans. Appl. Supercond. 3 (1993) 2728. [4] Y. Soutome, T. Fukazawa, K. Saitoh, A. Tsukamoto, K. Takagi, IEICE Trans. Electron. E85-C (2002) 759. [5] H. Katsuno, S. Inoue, T. Nagano, J. Yoshida, Appl. Phys. Lett. 79 (2001) 4189.
[6] K. Osamura, W. Zhang, Z. Metaqallkd. 84 (1993) 522. [7] K. Saitoh, Y. Soutome, T. Fukazawa, Y. Tarutani, K. Takagi, Appl. Phys. Lett. 76 (2000) 2606. [8] K. Saitoh, Y. Soutome, T. Fukazawa, Y. Tarutani, K. Takagi, IEEE Trans. Appl. Supercond. 11 (2001) 791. [9] T. Hato, N. Harada, Y. Ishimaru, A. Yoshida, N. Yokoyama, IEEE Trans. Appl. Supercond. 11 (2001) 936. [10] J.D. McCambridge, M.G. Forrestger, D.L. Miller, B.D. Hunt, J.X. Pryzbysz, J. Talvacchio, R.M. Young, IEEE Trans. Appl. Supercond. 7 (1997) 3622. [11] A.H. Sonnenberg, I. Oomen, H. Hilgenkamp, G.J. Gerritsma, H. Rogalla, IEEE Trans. Appl. Supercond. 11 (2001) 200. [12] M. Salluzzo, I. Maggio-Aprile, O. Fischer, Appl. Phys. Lett. 73 (1998) 683. [13] O.M. OM Parkash, K.D. Mandal, C.C. Christopher, M.S. Sastry, D. Kumar, J. Mater. Sci. Lett. 13 (1994) 1616. [14] T. Satoh, M. Hidaka, S. Tahara, IEEE Trans. Appl. Supercond. 7 (1997) 3001. [15] J.Y. Lee, K.M. Paqet, T.R. Lemberger, S.R. Foltyn, X. Wu, Phys. Rev. B 50 (1994) 3337. [16] R. Fagerberg, J.K. Grepstad, J. Appl. Phys. 75 (1994) 7408. [17] J. Yoshida, IEICE Trans. Electron. E83-C (2000) 49. [18] B. Ruck, Y. Chong, R. Dittmann, A. Engelhardt, B. Oelze, E. Sodtke, M. Siegel, IEEE Trans. Appl. Supercond. 9 (1999) 3850.
HTS-SFQ ring oscillator circuit fabricated with a novel multilayer structure H. Katsuno *, T. Nagano, K. Nakayama, J. Yoshida Corporate R&D Center, Toshiba Corporation, 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki 212-8582, Japan Received 13 November 2002; accepted 25 March 2003
Abstract A novel multilayer structure composed of a NBCO groundplane and stannate isolation layers was fabricated in order to improve the quality of Josephson characteristics and wiring layers on a buried groundplane. The fabricated junctions exhibited high magnetic modulation of Ic exceeding 90% and an Ic Rn product of 0.75 mV at 30 K. The sheet inductances of the counter-electrode and the base-electrode wiring were 1.1 and 1.3 pH, respectively, nearly independent of a temperature ranging from 20 to 30 K. We also fabricated an HTS-SFQ ring oscillator circuit including 21 junctions by adopting this novel multilayer and confirmed a proper operation of the ring oscillator at 20–30 K. The maximum output voltage of the ring oscillator was observed to be 0.06 mV at 30 K and 0.12 mV at 20 K, indicating the signal delay time per stage to be 3.4 and 1.8 ps, respectively. Ó 2003 Elsevier B.V. All rights reserved. PACS: 85.25.Hv; 85.25.Am Keywords: Interface engineered junction; NdBa2 Cu3 O7d ; Stannate; SFQ circuit; Ring oscillator
1. Introduction The interface engineered junction (IEJ) introduced by Moeckly and Char [1] is the most promising candidate for the construction of ultrahigh-speed circuits utilizing a single flux quantum (SFQ) as an information carrier [2], because IEJs are expected to satisfy the requirement of high uniformity for the circuit operation in terms of junction characteristics [3,4]. However, the thin
* Corresponding author. Tel.: +81-44-549-2110; fax: +81-44520-1801. E-mail address: [email protected] (H. Katsuno).
barrier layers of IEJs fabricated by damaging the base-electrode surface with ion bombardment and recrystallizing in an annealing process during the counter-electrode deposition are extremely sensitive to the annealing temperature. Because the critical current (Ic ) value appropriate to the operation of the SFQ circuit can be observed in a relatively low substrate temperature range during the counter-electrode deposition, this process temperature conflicts with complete c-axis oriented growth of the counter-electrode layer, especially when sputter-deposited YBa2 Cu3 O7d (YBCO) is used as the counter-electrode layer. In the previous paper [5], we adopted YbBa2 Cu3 O7d (YbBCO) as the counter-electrode layer because this material is known to exhibit
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complete c-axis oriented growth in a far wider temperature range than is possible with YBCO [6]. The junctions for which YbBCO was adopted as the counter-electrode layer exhibited excellent Josephson characteristics and appropriate Ic values for fabrication of SFQ circuits, maintaining the complete c-axis orientation of the counter-electrode layer. We also pointed out that the surface morphology of the insulator/base-electrode bilayer had a significant influence on the 1r-spread in Ic of the junctions fabricated on the ramp-edge of this bilayer. Recently, high-temperature superconducting (HTS) SFQ circuits without a groundplane have been investigated [7–9]. However, for the operation of the large-scale SFQ circuits, it is indispensable to reduce the inductance of the counter-electrode and base-electrode wiring by using a groundplane [10,11] insulated from these wiring layers except for the superconducting-contact area. A serious problem in such a multilayer is the degradation of the superconducting characteristics by increasing the number of stacked layers. The surface morphology of the insulator/groundplane bilayer is important in particular because it affects significantly the quality of the insulator/base-electrode bilayer. Our experimental results indicate that such rough surface of the insulator/groundplane bilayer results in uncontrollable junction characteristics and an unexpected increase of the sheet inductance of each superconducting wiring arising from decreasing Tc and Jc of each one. In this paper, we report a novel multilayer process to improve the surface morphology of the insulator/groundplane bilayer by selecting the ap-
propriate materials, and the successful operation of an SFQ ring oscillator.
2. Fabrication process At first, we adopted NdBa2 Cu3 O7d (NBCO) as the groundplane, because this HTS material is expected to improve surface morphology more effectively than YBCO, probably due to the formation of a solid solution system, Nd1þx Ba2x Cu3 O7d [12]. We confirmed that the average surface roughness (Ra ) of a 200-nm-thick NBCO film prepared on an LSAT(0 0 1) substrate by sputtering at a substrate temperature of 850 °C was below 1 nm as shown in Fig. 1(a). This value was better than that obtained for YBCO films with the same thickness by more than a factor of 2.5. The isolation layers in HTS-SFQ circuits are required to have a simple perovskite structure with reasonable lattice matching to HTS materials and a low dielectric constant. We selected CaSnO3 and SrSnO3 [13], whose dielectric constants were as low as 20, as the possible candidates. We found that CaSnO3 exhibited better surface morphology than SrSnO3 when deposited on NBCO films, whereas the situation was just the reverse on YBCO films. Therefore, we adopted CaSnO3 as the insulator on the groundplane, and SrSnO3 was used on the YBCO base-electrodes. The average surface roughness of a 500-nm-thick CaSnO3 /200-nmthick NBCO was below 1 nm as shown in Fig. 1(b), which was comparable to that of NBCO single layer. AFM observations also revealed that the surface of the bilayer contained few precipitates
Fig. 1. The AFM image of the NBCO groundplane film is shown in (a), and that of the CaSnO3 insulator/NBCO groundplane bilayer is shown in (b). Scanning areas are in the range of 20 lm 20 lm.
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Fig. 2. The schematic cross section of the multilayer structure consisting of NBCO groundplane and stannate isolation layer (CaSnO3 and SrSnO3 ).
as shown in Fig. 1(b); their relative area to the whole film surface was estimated to be below 0.01%. Fig. 2 shows the schematic cross section of the HTS-SFQ circuit. Ramp-edge junctions with YbBCO as the counter-electrode were formed on a buried NBCO groundplane, and the superconducting contacts between the base-electrode and the groundplane were provided through via holes in the CaSnO3 isolation layer. A 200-nm-thick NBCO groundplane was fabricated by sputtering at a substrate temperature of 850 °C. The asdeposited NBCO film exhibited a critical temperature (Tc ) exceeding 80 K and a critical current density exceeding 1 1011 A/m2 at 4.2 K. The groundplane was patterned by the two-step etching technique [14]. After depositing a 400-nm-thick CaSnO3 on the patterned groundplane, the superconducting contacts between the groundplane and the base-electrode layer were formed using a similar etching technique. A 200-nm-thick YBCO base-electrode layer and subsequently a 500-nmthick SrSnO3 isolation layer were deposited and the ramp-edge structure for IEJs was fabricated. Then, the sample was heated up to the temperature for the counter-electrode deposition in the sputtering chamber and maintained at that temperature for 10 min in an activated oxygen flux from an ECR plasma source. Successively, a 300-nm-thick YbBCO counter-electrode layer was deposited and the counter-electrode pattern was formed after
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covering the whole wafer surface with a 1-lmthick Au film. The resultant ramp-edge was formed at about 20° independent of the edge orientation in a wafer. After fabrication of the whole circuit structure, the sample was annealed at 600 °C in 1 atm. O2 for 12 h and cooled to the room temperature at a cooling rate of 0.1 °C/min to eliminate any possible damage to the superconducting layers in the fabrication process. This annealing process was effective for the YBCO base-electrode and the YbBCO counter-electrode layers as shown by their Tc exceeding 80 K. Unfortunately, however, the Tc of the NBCO groundplane remained at around 70 K and never reached the value of the as-deposited film.
3. Junction and film characteristics Fig. 3 shows typical current–voltage characteristics at 4.2 and 30 K for 4-lm-width junction on a buried groundplane. The junction displays weak hysteretic behavior below 20 K and the RSJ characteristics. The magnetic-field modulation of Ic exceeded 90% and the excess current was less than 10%, indicating a barrier structure without pin-holes. This sample was fabricated under the condition that was expected to give the Ic value of
Fig. 3. The I–V characteristics at 4.2 and 30 K on a buried groundplane.
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0.4 mA at 30 K. Although fabricated junctions exhibited slightly lower Ic value such as 0.3 mA as shown in Fig. 3, the Ic Rn product of 0.75 mV was satisfactory. According to the experimental results of junction array fabricated by using the above multilayer process, the 1r-spread in Ic was estimated to be 10–20% at 4.2 K. The problem of the 1r-spread in Ic remained even after adopting the novel multilayer process. Fig. 4 shows the temperature dependence of the sheet inductance (Ls ) of both counter-electrode and base-electrode layers on the groundplane. Each Ls was evaluated from SQUID modulation at strip lines of various lengths. The sheet inductance values of the counter- and the base-electrodes were 1.1 and 1.3 pH, respectively, nearly independent of the temperature ranging from 20 to 30 K for the operation of the HTS-SFQ circuit. These sheet inductance values of both electrodes fabricated by the novel multilayer were almost the same or slightly larger than those of the other reports [4,10]. The low transmissivity of oxygen in CaSnO3 resulted in the relatively low Tc of the NBCO groundplane such as 70 K and the sharp increase of Ls near Tc of the groundplane. According to the result for the as-deposited NBCO film exhibiting high Tc value, the superconducting characteristics of the NBCO groundplane are ex-
pected to be improved by the optimization of the annealing condition or the fabrication of the hole in the CaSnO3 /NBCO bilayer for the oxygen transmission, resulting in the improvement in the sheet inductance of both electrodes of less than 1.0 pH at the measurement temperature. We confirmed that the experimental data in Fig. 4 could be well fit to the conventional theoretical expression for a superconducting microstrip line by assuming the empirical temperature dependence of the London penetration depth in HTS materials given by Eq. (1) [15,16] by using the least squares method: p 1=2
kðT Þ=kð0Þ ¼ ð1 ðT =Tc Þ Þ
;
p¼2
ð1Þ
The penetration depths of the counter-electrode, base-electrode and groundplane can be estimated to be 170, 230 and 360 nm at 30 K, respectively. These results imply that the novel multilayer process simultaneously satisfies junctions and wiring characteristics for the operation of HTSSFQ circuits [17], indicating that this novel multilayer is appropriate for the fabrication of HTSSFQ circuits.
4. Ring oscillator operation 4.1. Ring oscillator structure
Fig. 4. The sheet inductance values of the counter- and the base-electrodes on a buried groundplane as functions of the temperature. The solid lines are fit by (1).
We have fabricated an SFQ ring oscillator circuit for estimating a signal delay per stage and a bit error rate of SFQ circuit [18]. In this paper, we have demonstrated the operation of the SFQ ring oscillator circuit elements and estimated a signal delay per stage in the ring oscillator. Fig. 5(a) shows the SEM image of the ring oscillator, and its equivalent circuit is shown in (b). This circuit consists of a dc/SFQ converter including a junction generating an SFQ pulse (J1 ) and an escape junction (Je ), a SQUID detecting an SFQ pulse generation, a Josephson transmission line (JTL), a confluence buffer and a ring oscillator. The ring oscillator is composed of 10-stage JTL with a closed-loop configuration containing an SFQ balanced comparator. Eight current sources (from source-I to source-III and from source-A to source-E) are used independently to supply the
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4.2. dc/SFQ converter
Fig. 5. The SEM image of the SFQ ring oscillator circuit is shown in (a), and its equivalent circuit is shown in (b). Eight current sources (from source-I to source-III and from source-A to source-E as shown in (b)) are used to supply the junctions in the whole circuit.
bias currents to the junctions of this whole circuit, as shown in Fig. 5(b). The SFQ pulse generated at the dc/SFQ converter is injected into the ring oscillator through the JTL and the confluence buffer. The dc/SFQ converter also generates an anti-flux in the loop including the detecting SQUID. It is possible independently of the other circuit elements to know whether the dc/SFQ works correctly or not, by detecting the SQUID voltage. The SFQ pulse injected into the ring oscillator rotates in the circuit until an additional current (comparator input as shown in Fig. 5(b)) is supplied to the balanced comparator. The ring output voltage can be detected among the junctions of JTL as shown in Fig. 5(b). The circulation frequency f of the SFQ pulse is determined from f ¼ V =U0 ; V is a dcvoltage that appears at the ring oscillator and U0 denotes the flux quantum (h=2e).
In the case of the correct operation for the dc/ SFQ converter, J1 generates both a flux injected into the ring oscillator and an anti-flux trapped in the left-hand loop of J1 in Fig. 5(b). Then, the antiflux escapes from Je by the opposite input current. Fig. 6 shows the experimental results of the dc/ SFQ converter operation at 30 K measured by changing the input current and the bias current (source-I shown in Fig. 5(b)). The sample was measured in a helium Dewar insert with three mumetal shields. The solid circles correspond to the characteristics with a trap of one flux, which was generated by the input current into a loop including the detecting SQUID. The open circles are the result in the case of disappearance of the trapped flux from the loop by the opposite input current. From the slope of the experimental data, it is possible to know which junctions generate fluxes because the slope can be determined just by the rate of the currents injected into two junctions that are fixed by the inductance of the wiring layer including the nonlinear term of the junctions. In the low-bias-current region in Fig. 6, the open circles show a similar slope to that indicated by the solid circles, indicating that J1 generates the fluxes
Fig. 6. The relation between the input current and the bias current of source-I as shown in Fig. 5(b), at 30 K. The solid circles are the result in the case of a trap of one flux in a loop including the detecting SQUID by the input current. The open circles are the result in the case of a disappearance of the trapped flux from the loop by the opposite input current.
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incorrectly. This method is available to probe the circuit operation easily; however, it is difficult to know whether the fluxes are trapped in the JTL loops or not, resulting in the uncertain Ic value of the generated junctions. In any case, the result in Fig. 6 indicates that it is possible to inject the SFQ pulse into the ring oscillator by controlling the input current. 4.3. Ring oscillator operation at 30 K Fig. 7 shows the experimental result for the ring oscillator operation at 30 K. The bias currents were adjusted to maximize the output voltage of the ring oscillator. When a positive-input current was supplied to the dc/SFQ converter, an output voltage appeared at the detecting SQUID, indicating the generation of the one SFQ pulse from the dc/SFQ converter. The SQUID voltage remained even after returning the input current to zero and disappeared by the successive negative one, as expected for the correct operation of the input current. The SFQ pulse generated in the dc/ SFQ converter transferred into the ring oscillator, resulting in the generation of the ring-output voltage. By supplying the additional current signal
Fig. 7. The experimental result for the ring oscillator operation at 30 K. The scale of each result is the following value; 0.5 mA/ div for input current, 0.2 mV/div for SQUID output, 1 mA/div for comparator input and 0.1 mV/div for ring output.
to the balanced comparator, the ring oscillator was returned to the initial state of the zero-output voltage, confirming the correct operation of the ring oscillator as designed. The maximum dc-output voltages of the ring oscillator were 0.06 mV at 30 K and 0.12 mV at 20 K, respectively. These values indicate the circulation frequency of SFQ to be 29 GHz at 30 K, and were increased up to 57 GHz at 20 K. Thus, the signal delay per stage in the ring oscillator can be estimated to be 3.4 ps at 30 K and 1.8 ps at 20 K. The rapid decrease in the output voltage by increasing the temperature cannot be ascribed to the decrease in the Ic Rn product value within this temperature range, and requires more detailed analysis including the variation in the Ic values of the junctions in the circuit. 4.4. Temperature dependence of the ring-output voltage Fig. 8 shows the relation between the bias current (source-B shown in Fig. 5(b)) and the output voltage observed for the ring oscillator at various temperatures between 20 and 30 K with and without the SFQ pulse injection. The solid lines
Fig. 8. The relations between the output voltage of the ring oscillator and the bias current (source-B shown in Fig. 5(b)) at various temperatures from 20 to 30 K. The solid lines are the experimental data for the self-oscillation without the SFQ pulse injection, and the dotted lines correspond to the characteristics with the SFQ pulse injection.
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correspond to the self-oscillation without the SFQ injection, and the dotted lines are the result in the case of the proper oscillation with the SFQ injection. The differences between the dotted and the solid lines at the zero-output voltage represent the bias margin for current source-B at each temperature. It can be seen that the bias margin shrinks rapidly with increasing the temperature. The relations between output voltage of the ring oscillator and the other current sources (source-C, source-D and source-E shown in Fig. 5(b)) are almost the same as for Fig. 8 with respect to the temperature dependence of the bias margin. For simplicity, we assume that the bias current is supplied equally to each junction in the ring oscillator. In the case without the SFQ pulse, the threshold at which the ring oscillator starts the self-oscillation is determined by the lowest Ic (Ic min ) value of the junctions constituting the ring oscillator. On the other hand, by assuming a circulating current to be a simple expression U0 =L in each JTL constituting the ring oscillator, the threshold of the proper oscillation by the injection of the SFQ pulse could be approximately represented as Ic max U0 =L, where Ic max is the highest Ic of the junctions in the ring oscillator and L is the loop inductance in each stage of the JTL constituting the ring oscillator. As a result, the bias margin could be given as U0 =L ðIc max Ic min Þ. This simple analysis clearly shows that the variation of the Ic value results in the serious decrease in the bias margin. According to this model, the temperature dependence of the bias margin seen in Fig. 8 can be ascribed to the term of Ic max Ic min because the temperature dependence of L is sufficiently weak between 20 and 30 K. The temperature dependence of Ic on the same wafer is expected to show the same feature on the whole because the barrier structures of such junctions are almost the same after passing through the same fabrication process. However, there is a possibility that there are some junctions exhibiting relatively large Ic with low magneticfield modulation. The results of our experiments obtained on the same wafer with the ring oscillator indicate that the temperature dependence of such junctions is weaker than that of high magneticfield modulation exhibiting strong temperature dependence of Ic . We tried to explain the shrinking
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of the bias margin with increasing the temperature by the circuit simulation. However, it is difficult to simulate and fully understand the experimental results because of the deviation from the design for the balance in Ic and the difficulty in confirming the characteristics of all junctions constituting the ring oscillator. Further improvement in reproducibility of the Ic value is necessary even after adopting the multilayer structure proposed in this paper, in order to discuss the performance and the prospect for high-temperature and ultra-highspeed operation of HTS-SFQ circuits in more detail.
5. Summary A novel multilayer available for the HTS-SFQ circuit was fabricated by adopting a NBCO groundplane and stannate isolation layers that show excellent surface morphology with Ra below 1 nm. The junction characteristics of IEJs using the novel multilayer exhibited the magnetic modulation of Ic exceeding 90% and nearly appropriate Ic value of about 0.3 mA at 30 K. The sheet inductances of the counter-electrode and the baseelectrode wiring were 1.1 and 1.3 pH, respectively, within a temperature ranging from 20 to 30 K. It is possible to reduce the sheet inductance of less than 1.0 pH by improving the superconducting characteristics of the groundplane. We also demonstrated the operation of the ring oscillator composed of 10-stage JTL with a closed-loop configuration at 20–30 K. The maximum output voltage of the ring oscillator was 0.06 mV at 30 K and 0.12 mV at 20 K. From these values, the circulation frequency of SFQ was calculated to be 29 GHz at 30 K and was increased up to 57 GHz at 20 K. Therefore, the delay time per stage can be estimated to be 3.4 ps at 30 K and 1.8 ps at 20 K, respectively. It was also pointed out that the large variation in Ic of the junctions constituting the ring oscillator resulted in the shrinking of the bias margin. Although the novel multilayer that improved the surface morphology of insulator/ groundplane bilayer satisfied the characteristics of junctions and superconducting wiring appropriate for the fabrication of SFQ circuits, it would be
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necessary to analyze the electric properties and crystal structure of IEJs to further improve the 1rspread in Ic . Acknowledgements This work was supported by the New Energy and Industrial Technology Development Organization (NEDO) as Collaborative Research and Development of Fundamental Technologies for Superconductivity Applications. References [1] B.H. Moeckly, K. Char, Appl. Phys. Lett. 71 (1997) 2526. [2] K.K. Likharev, V.K. Semenov, IEEE Trans. Appl. Supercond. 1 (1991) 3. [3] D.L. Miller, J.X. Przybysz, J.H. Kang, IEEE Trans. Appl. Supercond. 3 (1993) 2728. [4] Y. Soutome, T. Fukazawa, K. Saitoh, A. Tsukamoto, K. Takagi, IEICE Trans. Electron. E85-C (2002) 759. [5] H. Katsuno, S. Inoue, T. Nagano, J. Yoshida, Appl. Phys. Lett. 79 (2001) 4189.
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