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Impact of load pulse duration on power cycling lifetime of chip interconnection solder joints
MR-12498; No of Pages 5 Microelectronics Reliability xxx (2017) xxx–xxx
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Impact of load pulse duration on power cycling lifetime of chip interconnection solder joints M. Junghaenel ⁎, U. Scheuermann SEMIKRON Elektronik GmbH & Co. KG, Germany
a r t i c l e
i n f o
Article history: Received 19 May 2017 Received in revised form 29 June 2017 Accepted 29 June 2017 Available online xxxx Keywords: Power electronics Reliability Power cycling test Empirical lifetime model Failure mechanisms
a b s t r a c t Thermo-mechanical stress limits the useful life of power modules in the application. Active power cycling tests have been applied for more than three decades to investigate the degradation generated by thermo-mechanical stress in accelerated testing. Different lifetime models were proposed to extrapolate the lifetime from accelerated test results to application conditions. However, these lifetime models did not differentiate between the prominent failure mechanisms of Al wire bond degradation and solder fatigue in classical modules. By combining new, highly reliable interconnection technologies with classical technologies, those failure mechanisms can be investigated separately. In previous publications this concept of separation of failure modes was applied to study the impact of temperature swing and medium temperature on each failure mode in power cycling. In the present study, the impact of power pulse duration on the lifetime of chip solder and Al wire bonds is investigated. The results are another jigsaw piece for the goal of proposing a lifetime model for chip solder interconnections. The empirical data base is furthermore indispensable for the scaling and validation of physic-offailure approaches in the process of lifetime modelling. © 2017 Elsevier Ltd. All rights reserved.
1. Introduction Due to varying power losses dissipated in the semiconductor switches, power electronic modules are subjected to thermal stress during operation. The temperature gradient in the layer system of the module in combination with the different coefficients of thermal expansion of the materials result in mechanical stress which generates degradation of the interconnection layers. This limits lifetime of power electronic modules in application. For a reasonable designed power electronic system, electrical engineers need to know the lifetime of each component. By analysing typical mission profiles of an application, which represent the stress on a system and its components, engineers can estimate lifetime adequately if suitable lifetime models are available. The lifetime of power modules under thermo-mechanical stress have been investigated intensively in the past decades by accelerated DC power cycling test. The lifetime models derived from these studies have a pure empirical nature and are scaled upon a large database of power cycling test results. The first comprehensive lifetime investigation with numerous power cycling tests, which were conducted within the frame of the LESIT project in the early 90s [1], revealed the dependence of the lifetime not only on the temperature swing ΔTj, but also on the medium junction ⁎ Corresponding author at: SEMIKRON Elektronik GmbH & Co. KG, Sigmundstr. 200, 90431 Nuremberg, Germany. E-mail address: [email protected] (M. Junghaenel).
temperature Tjm. In 2008 the CIPS lifetime model was presented [2]. Besides the influence of further operational factors, like the dependency on the load pulse duration ton and the current density in the wire bond stitch, technological characteristics like the voltage class, representing the chip thickness, and the wire bond diameter were also taken into account. However these lifetime models have in common that they do not distinguish between the failure mechanisms which occur in classical power electronic modules under thermo-mechanical stress. These are the degradation of the wire bond interconnection on the topside of the chip, and the solder fatigue of the chip interface to the DBC or of the DBC-baseplate connection. Due to the different thermo-mechanical behaviour of the involved materials and the different nature of the failure mechanisms these failures reveal individual dependencies on the load characteristics. Thus the lifetime limiting failure mechanism in an accelerated test might differ from the lifetime limiting failure mechanism at divergent load conditions. As a consequence the extrapolation of a dependency based on the test results without knowledge of the dominant failure mechanism might lead to wrong lifetime expectations in applications. Today, new highly reliable connection technologies like aluminumcladded copper wires for the topside [3], or the sinter technology for the chip connection to the DBC [4], allow the isolated investigation of the different failure mechanisms by combining a high reliable technology on the one side with a classical technology on the other side. This method of separation of failure modes [5] was used for the investigation
http://dx.doi.org/10.1016/j.microrel.2017.06.081 0026-2714/© 2017 Elsevier Ltd. All rights reserved.
Please cite this article as: M. Junghaenel, U. Scheuermann, Impact of load pulse duration on power cycling lifetime of chip interconnection solder joints, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.06.081
2
M. Junghaenel, U. Scheuermann / Microelectronics Reliability xxx (2017) xxx–xxx
Fig. 1. PC-results of isolated failure mechanisms of classical modules in dependence on temperature swing ΔTj [7].
of the influence of the temperature, i.e. the medium temperature Tjm in [6,7] and the temperature swing ΔTj in [7]. The relation between temperature and lifetime limiting failure mode is illustrated in Fig. 1. Now, an investigation on the impact of the load pulse duration ton on lifetime was conducted and the results are presented in the following. In the course of mission profile analysis the varying thermal stress is reduced to a number of simple stress reversals by appropriate counting methods, like the rainflow counting algorithm [8]. Hereby long term temperature variations as well as superimposed short term temperature cycles are considered. On that account the load pulse duration was largely varied by three orders of magnitude in the present study. This ensures to capture the influence of pulse durations on lifetime more precisely. 2. Experimental approach 2.1. Test vehicles In accordance to the previous investigations in [6,7] DC power cycling tests were performed on two groups of modules by switching a DC load current cyclically on and off. The first group of modules consists of standard and commercially available SKiM63 modules [4]. This module comes in a six-pack configuration comprising three individual phase legs on separated power DBC substrates. Each switch consists of four 1200 V IGBT chips in parallel
Table 1 Power cycling test results in cycles of modules of group 1 and group 2 in dependence on load pulse duration ton.
110K
70K
Tj
ton
Nf, Group 1 6
Nf, Group 2
0.07 s
5.27·10
1.67/2.80·106
0.1 s
3.11·106
2.27·106
0.2 s
1.48·106
1.08/1.44·106
1s
7.94·105
4.12/4.41·105
2s
3.27/3.59·105
3.27/3.59·105
2s
6.71/6.80·104
6.40/7.90·104
7s
-
5.10/5.10·104
10 s
4.67·104
4.67/5.12·104
30 s
3.09·104
4.46·104
60 s
2.77/2.77 104
3.65·104
with a nominal chip current of 75 A each, such that the module has a nominal current rating of 300 A. The SKiM63 is a module without baseplate and is assembled in pressure contact technology. This means that the DBC substrate is directly pressed to the heatsink with a thermal paste interface when mounted. The inside connection technology is characterized by sintered chips and the topside chip connection is realized by aluminum wire bonds. Since the load current terminals are implemented by the pressure contacts and the auxiliary contacts by the spring technology the standard SKiM63 is a 100% solder-free module. For the test vehicles of the second group the SKiM63 module was specially modified: The chips were not sintered but soldered to the DBC, while the topside connection of the chip is realized by aluminum cladded copper wires [3], which exhibit a much higher reliability than standard aluminum bonds. By this approach a separation of failure modes is achieved, since no degradation of the sinter layer is expected for group 1 and only bond lift-off will occur, while the solder fatigue will be the lifetime limiting failure mechanism for group 2. 2.2. Test conditions A series of tests was defined with a large variation of the load pulse duration ton from 0.07 s to 60 s. All tests were performed with modules of both groups simultaneously. The Tjmax was hereby set to Tjmax = 150 °C for all tests. The temperature swing ΔTj was adjusted to ΔTj = 110 K for long load pulses of ton ≥ 2 s in order to shorten the test time, while for shorter load pulses ton ≤ 2 s the temperature swing had to be adjusted to ΔTj = 70 K since a temperature swing of ΔTj = 110 K would have required a load current that exceeds the maximum current rating of the module. The load current was adjusted in dependence of the load pulse duration ton at the beginning of each power cycle test in order to set the desired temperature swing and ranged between 240 A and 425 A. The voltage VGE was used for fine tuning of the temperatures and ranged between 12 V and 17 V. The modules were permanently cooled by water cooling. Cooling temperature was adjusted to set the medium temperature level of the test. As a result of the used test bench, which consists of two branches and which cycles the modules in each branch alternately, the cooling time toff is automatically the adjusted load pulse duration ton. Load and cooling settings where not changed during the whole power cycling test, so that degradation mechanisms had direct impact on the electrical and thermal behaviour of the module. Junction temperatures were measured by the VCE(T)-method that determines the virtual junction temperature which is actually equivalent to the area-related mean temperature of a chip, or in the present case of the paralleled chips, as described in [9]. 3. Test results All tests were conducted until end of life. Absolute lifetime in cycles is listed in Table 1. Since the investigation focused on the solder joint, testing for modules of group 1 was interrupted as soon as one switch of the half-bridge failed if the simultaneously tested module of group 2 had already failed completely. Fig. 2a illustrates the results of the presented test series with ΔTj = 70 K for ton ≤ 2 s and Fig. 2b plots the results of the test series with ΔTj = 110 K for ton ≤ 2 s. The results for the failure mode of bond lift-off in the standard SKiM63 modules of group 1 are depicted by the red squares. As a reference the SKiM63 lifetime model [10] is given as a solid green line for a failure probability of 50%. For short load pulses the experimental results are in good agreement with the prediction by the SKiM63 lifetime model. For long pulses however the experimental results exhibit a decrease in lifetime with increasing load pulse duration, while the SKiM63 lifetime model assumes a rapid stagnation of the lifetime decline. The test results of the soldered modules of group 2 are depicted in blue diamonds. In the range of short load pulses a lower gain in lifetime is perceptible for the solder connection than for the connection by wire
Please cite this article as: M. Junghaenel, U. Scheuermann, Impact of load pulse duration on power cycling lifetime of chip interconnection solder joints, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.06.081
M. Junghaenel, U. Scheuermann / Microelectronics Reliability xxx (2017) xxx–xxx
3
Fig. 2. Test results and preliminary FIT of dependency of the solder lifetime on load pulse duration ton in addition to SKiM63 [8] lifetime model as described in Table 2 for a) ton ≤ 2 s and ΔTj = 70 K and b) ton ≥ 2 s and ΔTj = 110 K. (For interpretation of the references to color in this figure, the reader is referred to the web version of this article.)
bonds. For long load pulses the lifetime decreases, but with declining rate. To model the diminishing influence of the load pulse duration on the lifetime of the solder connection a simple power law is not sufficient. Hence, a fractional rational power law term, as it was used to describe the dependency of the lifetime of the wire bond connection on the pulse duration in the SKiM63 model [10], is assumed. With respect to the different test conditions in dependence on the load pulse duration, the Coffin-Manson factor and the Arrhenius factor, which describe the lifetime as a function of the temperature settings, have to be taken into account. The corresponding parameters, i.e. the exponent α of the Coffin-Manson factor and the activation energy Ea in the Arrhenius relation, are quoted in Fig. 1 for each failure mechanism: n ΔT j ; T jm ; t on ΔT j −α exp
Ea C þ t on −γ ∙ kB ∙T jm Cþ1
The parameters C and γ were adjusted to the test results by a nonlinear regression. The resulting parameters are presented in Table 2 alongside with the parameters of the SKiM63 model which is also considered in Fig. 2. Based on this proposed relation the dependency of the lifetime of the tested solder connections on the load pulse duration is shown dashed in light blue in Fig. 2.
ible. This is an indication for a fracture propagation in the wire and not directly at the interface between bond and chip metallization. No heel crack was observed. By contrast modules of group 2 showed a strong degradation of the solder interconnection underneath the chips. The degradation pattern hereby varied significantly in dependence on the load condition. For long load pulses the lateral temperature gradient over the chip is not pronounced and the discontinuity at the edges of the chip solder results in a stress peak, so that solder degradation starts from the edges and moves towards the chip centre, as exemplified in Fig. 5a for the power cycling test at ton = 10 s and PV = 3 W/mm2. For decreasing load pulses the lateral temperature gradient over the chip is more and more pronounced, also partly due to the higher power density as a result of the higher load currents necessary to reach the desired temperature swing in each test. As a consequence of the high temperature in the solder under the chip centre the thermal and mechanical stress exceeds the stress at the edges of the chip solder, and a degradation of the solder occurs which starts in the chip centre instead of the chip edges [11]. This is illustrated in Fig. 5b for the power cycling test
4. Failure analysis A failure analysis was performed on the tested modules. After power cycle testing the modules were subjected to ultrasonic measurement. As expected no degradation of the sinter layer was found for the standard SKiM63 modules of group 1, see Fig. 3a and b, and bond lift-off was the dominant failure mechanism. Fig. 4 illustrates exemplarily the imprint of two lifted wire bonds. Residues of the aluminum wire bonds are vis-
Table 2 Parameters of relations between lifetime and load pulse duration (ton in s). Model
Relation
Parameters
SKiM63 [10]
C þ t on −γ Cþ1
C = 1.434 γ = 1.208
FIT solder fatigue
C þ t on −γ Cþ1
C = 0.363 γ = 0.741
Fig. 3. Typical ultrasonic image of half-bridge of module of group 1 a) before and b) after power cycle testing.
Please cite this article as: M. Junghaenel, U. Scheuermann, Impact of load pulse duration on power cycling lifetime of chip interconnection solder joints, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.06.081
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M. Junghaenel, U. Scheuermann / Microelectronics Reliability xxx (2017) xxx–xxx
Fig. 6. Ultrasonic image of half-bridges after power cycle testing of soldered modules with aluminum cladded copper bonds in [7] with ton = 2 s and a) ΔTj = 70 K, PV = 2.4 W/mm2, b) ΔTj = 90 K, PV = 3.1 W/mm2, c) ΔTj = 110 K, PV = 3.4 W/mm2, d) ΔTj = 130 K, PV = 4.1 W/mm2. Fig. 4. Image of wire bond lift-off in modules of group 1 for pc-test at ton = 60 s, PV = 3 W/mm2.
at a load pulse duration of ton = 0.2 s and a power density of approximately PV = 4 W/mm2. Since two different test conditions were applied, ΔTj = 70 K and ΔTj = 110 K, the impact of the temperature settings on the degradation pattern is of interest. The ultrasonic measurement of the modules of the test series performed with ton = 2 s and varying ΔTj and Tjm in [7] reveals no distinct differences in the degradation process. As presented in Fig. 6 the degradation of the chip solder started from the chip centre regardless of the chosen temperature swing. The monitored temperature and voltage rate during power cycling test revealed no wire bond lift-off. However, scattered lift-off of aluminum cladded wire bonds were found in analysis as a consequence of the massive destruction and melting of chip metallization due to extreme temperatures at end of life. 5. Discussion of results In the range of short load pulses the lifetime of the solder connection is lower and does not increase as distinctly as the lifetime of the wire
bond connection. The results have shown that different failure mechanisms occur in the solder layer depending on load pulse duration. For short load pulses higher lateral temperature gradients evolved over the chip, resulting in a pronounced temperature maximum in the solder in the area under the chip centre. Degradation process in form of fracture mechanisms starts in the centre of the chip solder, as confirmed by the ultrasonic images, and the thermal resistance of the solder layer increases locally at the point where chip temperature is already highest. This process provokes a positive feedback loop by further increasing the chip temperature in the centre which further increases the stress on the chip solder [11]. In the range of long load pulses the lifetime of the solder interconnection decreases only weakly and even outlasts lifetime of the wire bond connection from a certain load pulse duration on. Power densities were equal for load pulses of ton ≥ 10 s. The lateral temperature gradient is not pronounced at these test conditions, and the stress at the edges of the chip due to the discontinuity results in a degradation of the chip solder which starts from the edges, as shown in the analysis results. As was already discussed by Bayerer et al. [2], the variables of classical empirical lifetime models derived from power cycling test results are not independent, but they are correlated by the nature of a power system and a module setup. This applies also to the correlation between the pulse duration and the power density: decreasing pulse durations require increasing power densities to obtain a constant target temperature swing. Both, the load pulse duration and the power density determine the lateral temperature gradient in the chip and in the chip solder, which in turn influences chip solder degradation. However, the temperature gradient is a factor which cannot be determined without complex simulation and thus is not an option for a variable in empirical lifetime models. The SKiM63 lifetime model clearly overestimates the experimental results for modules of group 1 for load pulses ton N 10 s. This could be attributed to the small database in the investigation [10] and must be reviewed. 6. Conclusion
Fig. 5. Ultrasonic image of half-bridge after power cycle testing of module of group 2 a) for pc-test at ton = 10 s, PV = 3 W/mm2 and b) for pc-test at ton = 0.2 s, PV = 4 W/mm2.
The investigation of the impact of medium junction temperature and temperature swing on the lifetime of the solder connection and the lifetime of the wire bond connection in [6,7] has shown that different parameters are necessary to describe solder fatigue and aluminum wire bond degradation. By applying the method of separation of failure modes both interconnections were investigated independently by power cycling tests. In the present experimental study the influence of load pulse duration was investigated. The results constitute a further step to a lifetime model for chip interconnection solder joints. While for short load pulses the dependency described by the SKiM63 model could be confirmed, a review of the model is suggested to model
Please cite this article as: M. Junghaenel, U. Scheuermann, Impact of load pulse duration on power cycling lifetime of chip interconnection solder joints, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.06.081
M. Junghaenel, U. Scheuermann / Microelectronics Reliability xxx (2017) xxx–xxx
the test results at long load pulses which differ from the SKiM63 lifetime prediction. The failure analysis has revealed a pronounced dependency of solder fatigue on the lateral temperature gradient over the chip. At this point simulation models based on constitutive material models could be a helpful tool to support the results of empirical test studies with thermo-mechanical illustrations of the failure mechanism and its driving factors. The presented study however was conducted to establish an empirical lifetime models for a classical solder interconnection. The actual temperature in the chip solder is not assessed here since it cannot be measured directly and can only be determined by simulation. A time consuming FEM simulation could be conducted to determine transient temperature evolution at different positions inside a module for periodic cyclic tests, but this is not possible for long mission profiles with thousands of different load conditions. The statistical extent of the investigation is limited with one or two data points per failure mechanism and test condition. The pure testing time of more than 50 days for the longest test shows the time-consuming test implementation and the difficulty in the generation of large databases. Additional required time for premeasurements, test bench maintenance etc. is not even considered. Nevertheless the test results are consistent and they give a first indication on the impact of pulse duration on solder fatigue and wire bond degradation without mutual interaction. Classical power electronic modules with a large solder connection to the baseplate and the influence of the baseplate on the comprehensive deformation of the system and the additional solder degradation
5
in the solder layer between DBC and baseplate were not investigated here. References [1] M. Held, P. Jacob, G. Nicoletti, P. Scacco, M.H. Poech, Fast power cycling test of IGBT modules in traction application, Proc. Power Electronics and Drive Systems 1997, pp. 425–430. [2] R. Bayerer, T. Herrmann, T. Licht, J. Lutz, M. Feller, Model for power cycling lifetime of IGBT modules - various factors influencing lifetime, Proc. CIPS, ETG-Fachbericht, 111, 2008, pp. 37–42. [3] R. Schmidt, C. Koenig, P. Prenosil, Novel wire bond material for advanced power module packages, Microelectron. Reliab. 52 (2012) 2283–2288. [4] U. Scheuermann, P. Beckedahl, The road to the next generation power module 100% solder free design, Proc. CIPS, ETG-Fachbericht, 111, 2008, pp. 111–120. [5] R. Schmidt, U. Scheuermann, Separating failure modes in power cycling tests, Proc. CIPS, ETG-Fachbericht, 133, 2012, pp. 97–102. [6] R. Schmidt, F. Zeyss, U. Scheuermann, Impact of absolute junction temperature on power cycling lifetime, Proc. EPE 2013, pp. 1–10. [7] M. Junghaenel, R. Schmidt, J. Strobel, U. Scheuermann, Investigation on isolated failure mechanisms in active power cycle testing, Proc. PCIM Europe 2015, pp. 251–258. [8] K. Mainka, M. Thoben, O. Schilling, Lifetime calculation for power modules, application and theory of models and counting methods, Proc. EPE 2011, pp. 1–8. [9] R. Schmidt, U. Scheuermann, Using the chip as a temperature sensor - the influence of steep lateral temperature gradients on the Vce(T)-measurement, Proc. EPE 2009, pp. 1–9. [10] U. Scheuermann, R. Schmidt, A new lifetime model for advanced power modules with sintered chips and optimized Al wire bonds, Proc. PCIM Europe 2013, pp. 810–817. [11] J. Lutz, H. Schlangenotto, U. Scheuermann, R.D. Doncker, Semiconductor Power Devices - Physics, Characteristics, Reliability, Springer Science & Business Media, Berlin Heidelberg, 2011 403–407.
Please cite this article as: M. Junghaenel, U. Scheuermann, Impact of load pulse duration on power cycling lifetime of chip interconnection solder joints, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.06.081
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Impact of load pulse duration on power cycling lifetime of chip interconnection solder joints M. Junghaenel ⁎, U. Scheuermann SEMIKRON Elektronik GmbH & Co. KG, Germany
a r t i c l e
i n f o
Article history: Received 19 May 2017 Received in revised form 29 June 2017 Accepted 29 June 2017 Available online xxxx Keywords: Power electronics Reliability Power cycling test Empirical lifetime model Failure mechanisms
a b s t r a c t Thermo-mechanical stress limits the useful life of power modules in the application. Active power cycling tests have been applied for more than three decades to investigate the degradation generated by thermo-mechanical stress in accelerated testing. Different lifetime models were proposed to extrapolate the lifetime from accelerated test results to application conditions. However, these lifetime models did not differentiate between the prominent failure mechanisms of Al wire bond degradation and solder fatigue in classical modules. By combining new, highly reliable interconnection technologies with classical technologies, those failure mechanisms can be investigated separately. In previous publications this concept of separation of failure modes was applied to study the impact of temperature swing and medium temperature on each failure mode in power cycling. In the present study, the impact of power pulse duration on the lifetime of chip solder and Al wire bonds is investigated. The results are another jigsaw piece for the goal of proposing a lifetime model for chip solder interconnections. The empirical data base is furthermore indispensable for the scaling and validation of physic-offailure approaches in the process of lifetime modelling. © 2017 Elsevier Ltd. All rights reserved.
1. Introduction Due to varying power losses dissipated in the semiconductor switches, power electronic modules are subjected to thermal stress during operation. The temperature gradient in the layer system of the module in combination with the different coefficients of thermal expansion of the materials result in mechanical stress which generates degradation of the interconnection layers. This limits lifetime of power electronic modules in application. For a reasonable designed power electronic system, electrical engineers need to know the lifetime of each component. By analysing typical mission profiles of an application, which represent the stress on a system and its components, engineers can estimate lifetime adequately if suitable lifetime models are available. The lifetime of power modules under thermo-mechanical stress have been investigated intensively in the past decades by accelerated DC power cycling test. The lifetime models derived from these studies have a pure empirical nature and are scaled upon a large database of power cycling test results. The first comprehensive lifetime investigation with numerous power cycling tests, which were conducted within the frame of the LESIT project in the early 90s [1], revealed the dependence of the lifetime not only on the temperature swing ΔTj, but also on the medium junction ⁎ Corresponding author at: SEMIKRON Elektronik GmbH & Co. KG, Sigmundstr. 200, 90431 Nuremberg, Germany. E-mail address: [email protected] (M. Junghaenel).
temperature Tjm. In 2008 the CIPS lifetime model was presented [2]. Besides the influence of further operational factors, like the dependency on the load pulse duration ton and the current density in the wire bond stitch, technological characteristics like the voltage class, representing the chip thickness, and the wire bond diameter were also taken into account. However these lifetime models have in common that they do not distinguish between the failure mechanisms which occur in classical power electronic modules under thermo-mechanical stress. These are the degradation of the wire bond interconnection on the topside of the chip, and the solder fatigue of the chip interface to the DBC or of the DBC-baseplate connection. Due to the different thermo-mechanical behaviour of the involved materials and the different nature of the failure mechanisms these failures reveal individual dependencies on the load characteristics. Thus the lifetime limiting failure mechanism in an accelerated test might differ from the lifetime limiting failure mechanism at divergent load conditions. As a consequence the extrapolation of a dependency based on the test results without knowledge of the dominant failure mechanism might lead to wrong lifetime expectations in applications. Today, new highly reliable connection technologies like aluminumcladded copper wires for the topside [3], or the sinter technology for the chip connection to the DBC [4], allow the isolated investigation of the different failure mechanisms by combining a high reliable technology on the one side with a classical technology on the other side. This method of separation of failure modes [5] was used for the investigation
http://dx.doi.org/10.1016/j.microrel.2017.06.081 0026-2714/© 2017 Elsevier Ltd. All rights reserved.
Please cite this article as: M. Junghaenel, U. Scheuermann, Impact of load pulse duration on power cycling lifetime of chip interconnection solder joints, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.06.081
2
M. Junghaenel, U. Scheuermann / Microelectronics Reliability xxx (2017) xxx–xxx
Fig. 1. PC-results of isolated failure mechanisms of classical modules in dependence on temperature swing ΔTj [7].
of the influence of the temperature, i.e. the medium temperature Tjm in [6,7] and the temperature swing ΔTj in [7]. The relation between temperature and lifetime limiting failure mode is illustrated in Fig. 1. Now, an investigation on the impact of the load pulse duration ton on lifetime was conducted and the results are presented in the following. In the course of mission profile analysis the varying thermal stress is reduced to a number of simple stress reversals by appropriate counting methods, like the rainflow counting algorithm [8]. Hereby long term temperature variations as well as superimposed short term temperature cycles are considered. On that account the load pulse duration was largely varied by three orders of magnitude in the present study. This ensures to capture the influence of pulse durations on lifetime more precisely. 2. Experimental approach 2.1. Test vehicles In accordance to the previous investigations in [6,7] DC power cycling tests were performed on two groups of modules by switching a DC load current cyclically on and off. The first group of modules consists of standard and commercially available SKiM63 modules [4]. This module comes in a six-pack configuration comprising three individual phase legs on separated power DBC substrates. Each switch consists of four 1200 V IGBT chips in parallel
Table 1 Power cycling test results in cycles of modules of group 1 and group 2 in dependence on load pulse duration ton.
110K
70K
Tj
ton
Nf, Group 1 6
Nf, Group 2
0.07 s
5.27·10
1.67/2.80·106
0.1 s
3.11·106
2.27·106
0.2 s
1.48·106
1.08/1.44·106
1s
7.94·105
4.12/4.41·105
2s
3.27/3.59·105
3.27/3.59·105
2s
6.71/6.80·104
6.40/7.90·104
7s
-
5.10/5.10·104
10 s
4.67·104
4.67/5.12·104
30 s
3.09·104
4.46·104
60 s
2.77/2.77 104
3.65·104
with a nominal chip current of 75 A each, such that the module has a nominal current rating of 300 A. The SKiM63 is a module without baseplate and is assembled in pressure contact technology. This means that the DBC substrate is directly pressed to the heatsink with a thermal paste interface when mounted. The inside connection technology is characterized by sintered chips and the topside chip connection is realized by aluminum wire bonds. Since the load current terminals are implemented by the pressure contacts and the auxiliary contacts by the spring technology the standard SKiM63 is a 100% solder-free module. For the test vehicles of the second group the SKiM63 module was specially modified: The chips were not sintered but soldered to the DBC, while the topside connection of the chip is realized by aluminum cladded copper wires [3], which exhibit a much higher reliability than standard aluminum bonds. By this approach a separation of failure modes is achieved, since no degradation of the sinter layer is expected for group 1 and only bond lift-off will occur, while the solder fatigue will be the lifetime limiting failure mechanism for group 2. 2.2. Test conditions A series of tests was defined with a large variation of the load pulse duration ton from 0.07 s to 60 s. All tests were performed with modules of both groups simultaneously. The Tjmax was hereby set to Tjmax = 150 °C for all tests. The temperature swing ΔTj was adjusted to ΔTj = 110 K for long load pulses of ton ≥ 2 s in order to shorten the test time, while for shorter load pulses ton ≤ 2 s the temperature swing had to be adjusted to ΔTj = 70 K since a temperature swing of ΔTj = 110 K would have required a load current that exceeds the maximum current rating of the module. The load current was adjusted in dependence of the load pulse duration ton at the beginning of each power cycle test in order to set the desired temperature swing and ranged between 240 A and 425 A. The voltage VGE was used for fine tuning of the temperatures and ranged between 12 V and 17 V. The modules were permanently cooled by water cooling. Cooling temperature was adjusted to set the medium temperature level of the test. As a result of the used test bench, which consists of two branches and which cycles the modules in each branch alternately, the cooling time toff is automatically the adjusted load pulse duration ton. Load and cooling settings where not changed during the whole power cycling test, so that degradation mechanisms had direct impact on the electrical and thermal behaviour of the module. Junction temperatures were measured by the VCE(T)-method that determines the virtual junction temperature which is actually equivalent to the area-related mean temperature of a chip, or in the present case of the paralleled chips, as described in [9]. 3. Test results All tests were conducted until end of life. Absolute lifetime in cycles is listed in Table 1. Since the investigation focused on the solder joint, testing for modules of group 1 was interrupted as soon as one switch of the half-bridge failed if the simultaneously tested module of group 2 had already failed completely. Fig. 2a illustrates the results of the presented test series with ΔTj = 70 K for ton ≤ 2 s and Fig. 2b plots the results of the test series with ΔTj = 110 K for ton ≤ 2 s. The results for the failure mode of bond lift-off in the standard SKiM63 modules of group 1 are depicted by the red squares. As a reference the SKiM63 lifetime model [10] is given as a solid green line for a failure probability of 50%. For short load pulses the experimental results are in good agreement with the prediction by the SKiM63 lifetime model. For long pulses however the experimental results exhibit a decrease in lifetime with increasing load pulse duration, while the SKiM63 lifetime model assumes a rapid stagnation of the lifetime decline. The test results of the soldered modules of group 2 are depicted in blue diamonds. In the range of short load pulses a lower gain in lifetime is perceptible for the solder connection than for the connection by wire
Please cite this article as: M. Junghaenel, U. Scheuermann, Impact of load pulse duration on power cycling lifetime of chip interconnection solder joints, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.06.081
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Fig. 2. Test results and preliminary FIT of dependency of the solder lifetime on load pulse duration ton in addition to SKiM63 [8] lifetime model as described in Table 2 for a) ton ≤ 2 s and ΔTj = 70 K and b) ton ≥ 2 s and ΔTj = 110 K. (For interpretation of the references to color in this figure, the reader is referred to the web version of this article.)
bonds. For long load pulses the lifetime decreases, but with declining rate. To model the diminishing influence of the load pulse duration on the lifetime of the solder connection a simple power law is not sufficient. Hence, a fractional rational power law term, as it was used to describe the dependency of the lifetime of the wire bond connection on the pulse duration in the SKiM63 model [10], is assumed. With respect to the different test conditions in dependence on the load pulse duration, the Coffin-Manson factor and the Arrhenius factor, which describe the lifetime as a function of the temperature settings, have to be taken into account. The corresponding parameters, i.e. the exponent α of the Coffin-Manson factor and the activation energy Ea in the Arrhenius relation, are quoted in Fig. 1 for each failure mechanism: n ΔT j ; T jm ; t on ΔT j −α exp
Ea C þ t on −γ ∙ kB ∙T jm Cþ1
The parameters C and γ were adjusted to the test results by a nonlinear regression. The resulting parameters are presented in Table 2 alongside with the parameters of the SKiM63 model which is also considered in Fig. 2. Based on this proposed relation the dependency of the lifetime of the tested solder connections on the load pulse duration is shown dashed in light blue in Fig. 2.
ible. This is an indication for a fracture propagation in the wire and not directly at the interface between bond and chip metallization. No heel crack was observed. By contrast modules of group 2 showed a strong degradation of the solder interconnection underneath the chips. The degradation pattern hereby varied significantly in dependence on the load condition. For long load pulses the lateral temperature gradient over the chip is not pronounced and the discontinuity at the edges of the chip solder results in a stress peak, so that solder degradation starts from the edges and moves towards the chip centre, as exemplified in Fig. 5a for the power cycling test at ton = 10 s and PV = 3 W/mm2. For decreasing load pulses the lateral temperature gradient over the chip is more and more pronounced, also partly due to the higher power density as a result of the higher load currents necessary to reach the desired temperature swing in each test. As a consequence of the high temperature in the solder under the chip centre the thermal and mechanical stress exceeds the stress at the edges of the chip solder, and a degradation of the solder occurs which starts in the chip centre instead of the chip edges [11]. This is illustrated in Fig. 5b for the power cycling test
4. Failure analysis A failure analysis was performed on the tested modules. After power cycle testing the modules were subjected to ultrasonic measurement. As expected no degradation of the sinter layer was found for the standard SKiM63 modules of group 1, see Fig. 3a and b, and bond lift-off was the dominant failure mechanism. Fig. 4 illustrates exemplarily the imprint of two lifted wire bonds. Residues of the aluminum wire bonds are vis-
Table 2 Parameters of relations between lifetime and load pulse duration (ton in s). Model
Relation
Parameters
SKiM63 [10]
C þ t on −γ Cþ1
C = 1.434 γ = 1.208
FIT solder fatigue
C þ t on −γ Cþ1
C = 0.363 γ = 0.741
Fig. 3. Typical ultrasonic image of half-bridge of module of group 1 a) before and b) after power cycle testing.
Please cite this article as: M. Junghaenel, U. Scheuermann, Impact of load pulse duration on power cycling lifetime of chip interconnection solder joints, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.06.081
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Fig. 6. Ultrasonic image of half-bridges after power cycle testing of soldered modules with aluminum cladded copper bonds in [7] with ton = 2 s and a) ΔTj = 70 K, PV = 2.4 W/mm2, b) ΔTj = 90 K, PV = 3.1 W/mm2, c) ΔTj = 110 K, PV = 3.4 W/mm2, d) ΔTj = 130 K, PV = 4.1 W/mm2. Fig. 4. Image of wire bond lift-off in modules of group 1 for pc-test at ton = 60 s, PV = 3 W/mm2.
at a load pulse duration of ton = 0.2 s and a power density of approximately PV = 4 W/mm2. Since two different test conditions were applied, ΔTj = 70 K and ΔTj = 110 K, the impact of the temperature settings on the degradation pattern is of interest. The ultrasonic measurement of the modules of the test series performed with ton = 2 s and varying ΔTj and Tjm in [7] reveals no distinct differences in the degradation process. As presented in Fig. 6 the degradation of the chip solder started from the chip centre regardless of the chosen temperature swing. The monitored temperature and voltage rate during power cycling test revealed no wire bond lift-off. However, scattered lift-off of aluminum cladded wire bonds were found in analysis as a consequence of the massive destruction and melting of chip metallization due to extreme temperatures at end of life. 5. Discussion of results In the range of short load pulses the lifetime of the solder connection is lower and does not increase as distinctly as the lifetime of the wire
bond connection. The results have shown that different failure mechanisms occur in the solder layer depending on load pulse duration. For short load pulses higher lateral temperature gradients evolved over the chip, resulting in a pronounced temperature maximum in the solder in the area under the chip centre. Degradation process in form of fracture mechanisms starts in the centre of the chip solder, as confirmed by the ultrasonic images, and the thermal resistance of the solder layer increases locally at the point where chip temperature is already highest. This process provokes a positive feedback loop by further increasing the chip temperature in the centre which further increases the stress on the chip solder [11]. In the range of long load pulses the lifetime of the solder interconnection decreases only weakly and even outlasts lifetime of the wire bond connection from a certain load pulse duration on. Power densities were equal for load pulses of ton ≥ 10 s. The lateral temperature gradient is not pronounced at these test conditions, and the stress at the edges of the chip due to the discontinuity results in a degradation of the chip solder which starts from the edges, as shown in the analysis results. As was already discussed by Bayerer et al. [2], the variables of classical empirical lifetime models derived from power cycling test results are not independent, but they are correlated by the nature of a power system and a module setup. This applies also to the correlation between the pulse duration and the power density: decreasing pulse durations require increasing power densities to obtain a constant target temperature swing. Both, the load pulse duration and the power density determine the lateral temperature gradient in the chip and in the chip solder, which in turn influences chip solder degradation. However, the temperature gradient is a factor which cannot be determined without complex simulation and thus is not an option for a variable in empirical lifetime models. The SKiM63 lifetime model clearly overestimates the experimental results for modules of group 1 for load pulses ton N 10 s. This could be attributed to the small database in the investigation [10] and must be reviewed. 6. Conclusion
Fig. 5. Ultrasonic image of half-bridge after power cycle testing of module of group 2 a) for pc-test at ton = 10 s, PV = 3 W/mm2 and b) for pc-test at ton = 0.2 s, PV = 4 W/mm2.
The investigation of the impact of medium junction temperature and temperature swing on the lifetime of the solder connection and the lifetime of the wire bond connection in [6,7] has shown that different parameters are necessary to describe solder fatigue and aluminum wire bond degradation. By applying the method of separation of failure modes both interconnections were investigated independently by power cycling tests. In the present experimental study the influence of load pulse duration was investigated. The results constitute a further step to a lifetime model for chip interconnection solder joints. While for short load pulses the dependency described by the SKiM63 model could be confirmed, a review of the model is suggested to model
Please cite this article as: M. Junghaenel, U. Scheuermann, Impact of load pulse duration on power cycling lifetime of chip interconnection solder joints, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.06.081
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the test results at long load pulses which differ from the SKiM63 lifetime prediction. The failure analysis has revealed a pronounced dependency of solder fatigue on the lateral temperature gradient over the chip. At this point simulation models based on constitutive material models could be a helpful tool to support the results of empirical test studies with thermo-mechanical illustrations of the failure mechanism and its driving factors. The presented study however was conducted to establish an empirical lifetime models for a classical solder interconnection. The actual temperature in the chip solder is not assessed here since it cannot be measured directly and can only be determined by simulation. A time consuming FEM simulation could be conducted to determine transient temperature evolution at different positions inside a module for periodic cyclic tests, but this is not possible for long mission profiles with thousands of different load conditions. The statistical extent of the investigation is limited with one or two data points per failure mechanism and test condition. The pure testing time of more than 50 days for the longest test shows the time-consuming test implementation and the difficulty in the generation of large databases. Additional required time for premeasurements, test bench maintenance etc. is not even considered. Nevertheless the test results are consistent and they give a first indication on the impact of pulse duration on solder fatigue and wire bond degradation without mutual interaction. Classical power electronic modules with a large solder connection to the baseplate and the influence of the baseplate on the comprehensive deformation of the system and the additional solder degradation
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in the solder layer between DBC and baseplate were not investigated here. References [1] M. Held, P. Jacob, G. Nicoletti, P. Scacco, M.H. Poech, Fast power cycling test of IGBT modules in traction application, Proc. Power Electronics and Drive Systems 1997, pp. 425–430. [2] R. Bayerer, T. Herrmann, T. Licht, J. Lutz, M. Feller, Model for power cycling lifetime of IGBT modules - various factors influencing lifetime, Proc. CIPS, ETG-Fachbericht, 111, 2008, pp. 37–42. [3] R. Schmidt, C. Koenig, P. Prenosil, Novel wire bond material for advanced power module packages, Microelectron. Reliab. 52 (2012) 2283–2288. [4] U. Scheuermann, P. Beckedahl, The road to the next generation power module 100% solder free design, Proc. CIPS, ETG-Fachbericht, 111, 2008, pp. 111–120. [5] R. Schmidt, U. Scheuermann, Separating failure modes in power cycling tests, Proc. CIPS, ETG-Fachbericht, 133, 2012, pp. 97–102. [6] R. Schmidt, F. Zeyss, U. Scheuermann, Impact of absolute junction temperature on power cycling lifetime, Proc. EPE 2013, pp. 1–10. [7] M. Junghaenel, R. Schmidt, J. Strobel, U. Scheuermann, Investigation on isolated failure mechanisms in active power cycle testing, Proc. PCIM Europe 2015, pp. 251–258. [8] K. Mainka, M. Thoben, O. Schilling, Lifetime calculation for power modules, application and theory of models and counting methods, Proc. EPE 2011, pp. 1–8. [9] R. Schmidt, U. Scheuermann, Using the chip as a temperature sensor - the influence of steep lateral temperature gradients on the Vce(T)-measurement, Proc. EPE 2009, pp. 1–9. [10] U. Scheuermann, R. Schmidt, A new lifetime model for advanced power modules with sintered chips and optimized Al wire bonds, Proc. PCIM Europe 2013, pp. 810–817. [11] J. Lutz, H. Schlangenotto, U. Scheuermann, R.D. Doncker, Semiconductor Power Devices - Physics, Characteristics, Reliability, Springer Science & Business Media, Berlin Heidelberg, 2011 403–407.
Please cite this article as: M. Junghaenel, U. Scheuermann, Impact of load pulse duration on power cycling lifetime of chip interconnection solder joints, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.06.081