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Inductively coupled plasma etching of tapered via in silicon for MEMS integration
Microelectronic Engineering 141 (2015) 261–266
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Inductively coupled plasma etching of tapered via in silicon for MEMS integration Zhong Ren ⇑, Mark E. McNie Oxford Instruments Plasma Technology, Yatton BS49 4AP, United Kingdom
a r t i c l e
i n f o
Article history: Received 29 October 2014 Received in revised form 23 March 2015 Accepted 27 March 2015 Available online 13 April 2015 Keywords: Inductively coupled plasma (ICP) Deep silicon etch Tapered via Through silicon via Micro-electro-mechanical systems (MEMS)
a b s t r a c t An ICP plasma etching technique for fabrication of tapered vias on silicon substrates has been developed by means of single patterning and etching process. Experimentally, effects of parameters including ICP power, chamber pressure, gas ratio and RF bias power were investigated for their impact on etch rate, selectivity, profile and surface roughness. Monotonic profile angles in the range of 60–80° have been achieved on 10–50 lm wide vias through adjustment of the C4F8/SF6 ratio and optimization on other key parameters. We found that addition of O2 controlled lateral etch rate only weakly, except when running the process at cryogenic temperature. Adjustment of the process powers was a significant factor in controlling sidewall roughness. Ó 2015 Elsevier B.V. All rights reserved.
1. Introduction There is a demand for increasing levels of integration and function density to meet the requirements of consumer applications, such as CMOS and MEMS components for high memory, high processing speeds and advanced functions in smart phones and other portable equipment. Compared to traditional wire-bonding methods, through-silicon vias (TSVs) provide a short interconnect path with a high density [1,2]. Therefore, in recent years conductive TSVs have become an important emerging technology for electrical connection of stacked devices in semiconductor industry as alternative to conventional wire bonding [1] and to connect and control stacked MEMS or combined MEMS-CMOS modules in order to save space (see Fig. 1). For increased throughput and simplified etch requirements, silicon wafers can be thinned to 50–100 lm thick with a handle wafer for high density TSV applications. This reduces the aspect ratio (AR) required to etch TSVs and subsequent thin film depositing steps. Typical sizes of TSVs are in the range 5–50 lm in diameter and 50–500 lm depth. State-of-the-art wafer-level bonding techniques are able to integrate heterogeneous materials (e.g. III–V compounds, ferroelectric, etc) on a silicon base chip with multiple functions [2]. These pioneering ideas are also opening new research frontier for MEMS and optoelectronic integration. A controllable
⇑ Corresponding author. E-mail address: [email protected] (Z. Ren). http://dx.doi.org/10.1016/j.mee.2015.03.071 0167-9317/Ó 2015 Elsevier B.V. All rights reserved.
wide-angle range TSV (60–85°) technique with a wide material compatibility in order to facilitate void-free filling the via with contact metal is a preferred approach in this scenario. The Bosch deep silicon etch (DSiE) process [3] is usually used to etch TSVs. This uses a high density plasma with cycling deposition and etch steps to provide a vertical profile (typical 88–90°) capable of high aspect ratios (AR) at high rate. The achievable angular range, however, is too limited to address tapered profile requirements. Through an isotropic etch, a tapered profile (<85°) can be achieved [4] but typically with an overhang at top of via – see Fig. 2. This overhang would result in void formation in subsequent seeding and filling steps. To realize a void-free via, this overhang may be removed by means of a subsequent maskless etch step [4,5], but it results in the loss of a few microns silicon on the surface and enlarges the critical dimension (CD) of the TSV [5]. Moreover the process may not be tolerated by unprotected device areas on the surface. Recently, it has been shown that a SF6-O2 chemistry may be used to realize an 80° via profile, but a 70° profile has proven difficult to achieve [6,7]. An anisotropic wet etch that is selective to the <1 1 1> planes, such as KOH, EDP or TMAH, may achieve a tapered profile but at a fixed angle 54.74° for <1 0 0> silicon wafers [8]. It is also limited to low AR, requires additional alignment to the crystalline plane and has restrictions on geometry (circular features being particularly challenging and often requiring corner compensation). The focus of the work reported here was to develop techniques to achieve selectable tapered profile on an etched TSV profile by means of ICP etching. As a result, monotonic profiles in the range
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Fig. 1. Illustration of MEMS 3D integration and wafer-level packaging with a typical TSV technology.
of 60–80° for subsequent void-free filling have been successfully achieved on 10–50 lm wide vias. 2. Experimental Etch experiments were carried out in an ICP etch system (Oxford Instruments PlasmaPro 100 Estrelas) as schematic of which is shown in Fig. 3 using a SF6-C4F8 ‘‘mixed gas’’ chemistry. 4.5 lm thick photoresist (PR) masks were patterned on standard <1 0 0> silicon wafers using conventional photolithography. PECVD silicon oxide (SiO2) was deposited on additional silicon wafers at 300 °C in order to check the etch selectivity to SiO2. ICP chamber pressures from 25 to 120 mTorr and total flows in the range of 100–1000 sccm were selected. The ICP source frequency was 2 MHz, and its power was set in the range of
Fig. 3. Schematic of an ICP etch system.
1000–5000 W in order to generate a high density of fluorine (F) radicals in the plasma. RF bias powers in the range of 10 to 200 W were applied from either 13.56 MHz high frequency (HF) or 350 kHz low frequency (LF) generators to the lower electrode with an electrostatic chuck (ESC) to generate a self-biasing voltage to vertically attract ions from the plasma to the wafer surface. The DC bias voltage values mentioned in this paper were those supplied by the analog meters and software of the tools used [9]. The wafers were chucked on the lower electrode set at a temperature of 0 °C and controlled to within ±1 °C. After etching, etch rate, selectivity, profile and surface morphology were investigated by means of a field-emission scanning electron microscopy (SEM) in order to develop the tapered via etch processes. 3. Results and discussion In this paper, we described the development and characterization of plasma etching processes with various process conditions. A study was performed to analyze the effect of these key factors on the results. 3.1. Effect of chamber pressure and gas flow Both etch rate and selectivity are calculated and plotted in Fig. 4(a) and (b). Higher pressure with a high SF6 gas flow gave a faster rate and a higher selectivity because it supplied higher F radical concentrations which enhanced the chemical reaction with Si. As a result, an etch rate in excess of 10 lm/min was obtained on a 63° profile TSV etch, with sidewall roughness of <1 lm, as shown in Fig. 4(c). However, it was challenging to achieve steeper sidewall profiles due to a high lateral etch rate. 3.2. Effect of ICP source power
Fig. 2. Tapered via fabrication by two-step etching (a) after high-rate Bosch etch (18 lm/min); (b) subsequent SF6/O2 isotropic etch, 80° profile at a 30 lm via, but overhang at top.
Fig. 5(a) and (b) indicate that raising ICP power also dramatically increases etch rate in the vertical direction but simultaneously decreases selectivity to mask materials. This decrease of selectivity could limit attaining the desired via etch depth. This is attributed to high ICP source power enhancing the dissociation and ionization of both SF6 and C4F8. The increase of radicals and ions from SF6 was higher than that from the polymer (C4F8)
Z. Ren, M.E. McNie / Microelectronic Engineering 141 (2015) 261–266
263
achievable profiles in the range of 58–76° for 50 lm wide vias, as shown in Fig. 6. When more polymer was deposited on sidewall [10], it effectively suppressed the lateral etch rate. This helped to achieve a steeper profile but decreased vertical etch rate and selectivity. On the other hand, the sidewall became significantly rougher (3 lm) when profile was more than 68°, as shown in Fig. 7. This was due to a reduction of the isotropic etch in the lateral direction and a lack of necessary ion bombardment to effectively remove the polymer in the areas shadowed by the undercutting of the mask. We considered that oxygen ions and radicals would chemically react with Si and then form a thin oxide layer on exposed surface. That would reduce lateral etch rate because of a high etching selectivity of Si to SiO2. Therefore, 5% oxygen was mixed in process gases in order to achieve profile of 70–80° but also improve sidewall roughness. But, Fig. 8 does not show an expected result on profile control, but contrary to what one might suppose, addition of oxygen slightly increased the lateral etch rate. A possible cause was that oxygen species also reacted with CFx polymer at the same time, so that it resulted in less passivation on etched sidewalls. Further increasing oxygen flow would significantly decrease selectivity to PR mask because it has to increase RF bias power at the same time. Key points, using SiF6-O2 chemistry at room temperature, has been systematically discussed in Li’s paper [7].
Fig. 4. (a) and (b) Variation of etch rate and selectivity to both PR and SiO2 with chamber pressures under constant ICP and RF bias powers; (c) 63° sidewall profile of a 50 lm via.
because a gas ratio of SF6:C4F8 was about 6:1. These combined to enhance the physical etching of both the PR and SiO2 masks. 3.3. Effect of gas ratio and addition of oxygen Profile angles in the vias can be controlled by adjustment of C4F8/SF6 gas ratio to control F concentration and polymer formation in the plasma. A series of experiments demonstrated
Fig. 5. (a) and (b) Variation of etch rate and selectivity to both PR and SiO2 with ICP power under constant pressure and gas ratio.
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Fig. 6. Sidewall angle change on TSV profile with increase of C4F8 ratio at a total flow of 624 sccm.
Fig. 8. (a) and (b) Variation of etch rate and selectivity to both PR and SiO2 with ICP power under a constant pressure.
Fig. 7. 76° sidewall profile of a 50 lm via.
Decreasing the temperature enables an SF6-O2 chemistry to form enough SiFxOy polymer during Si etching at a cryogenic temperatures. This condensate offers sidewall protection from the SF6 chemical attack, similar to the role C4F8 plays in Bosch etching. Anisotropic silicon etching can thus be realized, resulting in geometries in which the verticality of the sidewalls is tightly controlled by the passivation rate. Although the etch rate and the passivation rate equations are coupled, various mechanisms for controlling the passivation rate are also separable from the etching rate equation, such as silicon surface temperature and oxygen concentration in the etching plasma. [11]. This enables a sloped profile in via etch process without any mask undercutting, in the range 84–90° – an example is shown in Fig. 9. 3.4. Effect of RF bias power and frequency In Fig. 10(a) and (b), raising RF power (DC bias) changes the etch rate and wall angle only slightly. Higher bias decreased selectivity to masks due to high ion energy. The selectivity was lower for LF bias compared to RF bias for the same bias power, indicating that low frequency contributes a higher fraction of its energy to ion bombardment than 13.56 MHz RF bias. LF RF power with the associated higher bias did however improve surface roughness. The mechanism could be largely related to collision among SFx ions in relatively high pressure
Fig. 9. 84° sidewall profile at a 20 lm via which was achieved by a SF6-O2 process at 100 °C table temperature.
plasma that results in scatter in all directions coupled with ions being able to responding vertically at the exciting LF frequency. The net results are less vertical directionality so that a portion of the ions can enter the shadowed area under the mask and remove polymer better from the surface.
Z. Ren, M.E. McNie / Microelectronic Engineering 141 (2015) 261–266
Fig. 10. (a) and (b) Variation of etch rate and selectivity to both PR and SiO2 with RF bias power under constant ICP power and chamber pressure.
265
Fig. 12. (a) 72° sidewall profiles at a 50 lm via; (b) roughness on sidewall, without any overhang at top.
was successfully realized in a 50 lm wide via with an etch rate of 2 lm/min, a sidewall roughness of <300 nm and no overhang at the top of via – as shown in Fig. 12. Profile curvature was dominated by vertical: lateral etch balance. High aspect ratio vias decrease transport and diffusion effectiveness for etchants and etch by-products. Therefore, a multi-step process with evolving parameters may be employed to effectively maintain this balance with etching depth. 4. Conclusion
Fig. 11. Sidewall curvature and surface roughness change with different ICP power levels.
3.5. Sidewall morphology Usually, monotonic profile angles are always expected for voidfree metal filling. Using a low ICP power with optimization of the aforementioned parameters is advantageous in realizing a low sidewall roughness and curvature – see Fig. 11. A 72° profile via
The ICP plasma dry etching technique for fabrication of tapered vias on Si substrates has been developed by means of a single patterning and etching process, suitable for subsequent void-free filling. Processes using a mixed gas chemistry (SF6/C4F8) have been optimized in terms of the operational parameters such as ICP power, chamber pressure, gas ratio and RF bias power. Monotonic profile angles in the range of 60–80° have been achieved on 10–50 lm wide vias through adjustment of the C4F8/ SF6 ratio. Adjusting the process power also helped sidewall roughness. As a result, an etch rate of 10 lm/min was obtained on 63° profile TSV etch, with sidewall roughness of <1 lm; a 72° profile via was also realized on 20–50 lm wide vias with sidewall roughness of <300 nm and no overhang. This technique will be widely used for MEMS 3D integration and packaging applications such as CMOS cameras where non-vertical vias are required.
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Z. Ren, M.E. McNie / Microelectronic Engineering 141 (2015) 261–266
Acknowledgments The authors would like to acknowledge both Michael Steel and Colin Welch (Oxford Instruments) for helpful suggestions and Dr. Mike Cooke and Dr. Leslie Lea (Oxford Instruments) for discussions about plasma physics. References [1] J. Leib, F. Bieck, U. Hansen, K. Looi, H. Ngo, V. Seidemann, D. Shariff, D. Studzinski, N. Suthiwongsunthorn, K. Tan, R. Wilke, K. Yam, M. Töpper, IEEE Trans. Adv. Packag. 33 (3) (2010) 713–721. [2] D. Tezcan, N. Pham, B. Majeed, P. Moor, W. Ruythooren, K. Baert, in: Electronic Components and Technology Conference, 2007, pp. 643–647.
[3] F. Laermer, A. Schilp, Verfahren zum anisotropen atzen von silicium, German Patent DE-4241045, 1994. [4] Niclas Roxhed, Patrick Griss, Goran Stemme, J. Micromech. Microeng. 17 (2007) 1087–1092. [5] N. Raganathan, D.Y. Lee, L. Ebin, N. Balasubramanian, K. Prasad, K.L. Pey, J. Micromech. Microeng. 18 (2008) 115028. [6] R.F. Figueroa, S. Spiesshoefer, J. Vac. Sci. Technol. A 23 (5) (2005) 2226–2229. [7] R. Li, Y. Lamy, W.F.A. Besling, F. Roozeboom, P.M. Sarro, J. Micromech. Microeng. 18 (2008) 125023. [8] H. Seidel, L. Csepregi, A. Heuberger, H. Baumgartel, J. Electrochem. Soc. 137 (11) (1990) 3614–3626. [9] M.J. Cooke, G. Hassall, Plasma Sources Sci. Technol. 11 (2002) A74–79. [10] M. Schaepkens, I. Martini, E.A. Sanjuan, X. Li, G.S. Oehriein, W.L. Perry, H.M. Anderson, J. Vac. Sci. Technol. A 19 (6) (2001) 2946–2957. [11] C.C. Welch, A.L. Goodyear, T. Wahlbrink, M.C. Lemme, T. Mollenhauer, Microelectron. Eng. 83 (2006) 1170–1173.
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Inductively coupled plasma etching of tapered via in silicon for MEMS integration Zhong Ren ⇑, Mark E. McNie Oxford Instruments Plasma Technology, Yatton BS49 4AP, United Kingdom
a r t i c l e
i n f o
Article history: Received 29 October 2014 Received in revised form 23 March 2015 Accepted 27 March 2015 Available online 13 April 2015 Keywords: Inductively coupled plasma (ICP) Deep silicon etch Tapered via Through silicon via Micro-electro-mechanical systems (MEMS)
a b s t r a c t An ICP plasma etching technique for fabrication of tapered vias on silicon substrates has been developed by means of single patterning and etching process. Experimentally, effects of parameters including ICP power, chamber pressure, gas ratio and RF bias power were investigated for their impact on etch rate, selectivity, profile and surface roughness. Monotonic profile angles in the range of 60–80° have been achieved on 10–50 lm wide vias through adjustment of the C4F8/SF6 ratio and optimization on other key parameters. We found that addition of O2 controlled lateral etch rate only weakly, except when running the process at cryogenic temperature. Adjustment of the process powers was a significant factor in controlling sidewall roughness. Ó 2015 Elsevier B.V. All rights reserved.
1. Introduction There is a demand for increasing levels of integration and function density to meet the requirements of consumer applications, such as CMOS and MEMS components for high memory, high processing speeds and advanced functions in smart phones and other portable equipment. Compared to traditional wire-bonding methods, through-silicon vias (TSVs) provide a short interconnect path with a high density [1,2]. Therefore, in recent years conductive TSVs have become an important emerging technology for electrical connection of stacked devices in semiconductor industry as alternative to conventional wire bonding [1] and to connect and control stacked MEMS or combined MEMS-CMOS modules in order to save space (see Fig. 1). For increased throughput and simplified etch requirements, silicon wafers can be thinned to 50–100 lm thick with a handle wafer for high density TSV applications. This reduces the aspect ratio (AR) required to etch TSVs and subsequent thin film depositing steps. Typical sizes of TSVs are in the range 5–50 lm in diameter and 50–500 lm depth. State-of-the-art wafer-level bonding techniques are able to integrate heterogeneous materials (e.g. III–V compounds, ferroelectric, etc) on a silicon base chip with multiple functions [2]. These pioneering ideas are also opening new research frontier for MEMS and optoelectronic integration. A controllable
⇑ Corresponding author. E-mail address: [email protected] (Z. Ren). http://dx.doi.org/10.1016/j.mee.2015.03.071 0167-9317/Ó 2015 Elsevier B.V. All rights reserved.
wide-angle range TSV (60–85°) technique with a wide material compatibility in order to facilitate void-free filling the via with contact metal is a preferred approach in this scenario. The Bosch deep silicon etch (DSiE) process [3] is usually used to etch TSVs. This uses a high density plasma with cycling deposition and etch steps to provide a vertical profile (typical 88–90°) capable of high aspect ratios (AR) at high rate. The achievable angular range, however, is too limited to address tapered profile requirements. Through an isotropic etch, a tapered profile (<85°) can be achieved [4] but typically with an overhang at top of via – see Fig. 2. This overhang would result in void formation in subsequent seeding and filling steps. To realize a void-free via, this overhang may be removed by means of a subsequent maskless etch step [4,5], but it results in the loss of a few microns silicon on the surface and enlarges the critical dimension (CD) of the TSV [5]. Moreover the process may not be tolerated by unprotected device areas on the surface. Recently, it has been shown that a SF6-O2 chemistry may be used to realize an 80° via profile, but a 70° profile has proven difficult to achieve [6,7]. An anisotropic wet etch that is selective to the <1 1 1> planes, such as KOH, EDP or TMAH, may achieve a tapered profile but at a fixed angle 54.74° for <1 0 0> silicon wafers [8]. It is also limited to low AR, requires additional alignment to the crystalline plane and has restrictions on geometry (circular features being particularly challenging and often requiring corner compensation). The focus of the work reported here was to develop techniques to achieve selectable tapered profile on an etched TSV profile by means of ICP etching. As a result, monotonic profiles in the range
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Z. Ren, M.E. McNie / Microelectronic Engineering 141 (2015) 261–266
Fig. 1. Illustration of MEMS 3D integration and wafer-level packaging with a typical TSV technology.
of 60–80° for subsequent void-free filling have been successfully achieved on 10–50 lm wide vias. 2. Experimental Etch experiments were carried out in an ICP etch system (Oxford Instruments PlasmaPro 100 Estrelas) as schematic of which is shown in Fig. 3 using a SF6-C4F8 ‘‘mixed gas’’ chemistry. 4.5 lm thick photoresist (PR) masks were patterned on standard <1 0 0> silicon wafers using conventional photolithography. PECVD silicon oxide (SiO2) was deposited on additional silicon wafers at 300 °C in order to check the etch selectivity to SiO2. ICP chamber pressures from 25 to 120 mTorr and total flows in the range of 100–1000 sccm were selected. The ICP source frequency was 2 MHz, and its power was set in the range of
Fig. 3. Schematic of an ICP etch system.
1000–5000 W in order to generate a high density of fluorine (F) radicals in the plasma. RF bias powers in the range of 10 to 200 W were applied from either 13.56 MHz high frequency (HF) or 350 kHz low frequency (LF) generators to the lower electrode with an electrostatic chuck (ESC) to generate a self-biasing voltage to vertically attract ions from the plasma to the wafer surface. The DC bias voltage values mentioned in this paper were those supplied by the analog meters and software of the tools used [9]. The wafers were chucked on the lower electrode set at a temperature of 0 °C and controlled to within ±1 °C. After etching, etch rate, selectivity, profile and surface morphology were investigated by means of a field-emission scanning electron microscopy (SEM) in order to develop the tapered via etch processes. 3. Results and discussion In this paper, we described the development and characterization of plasma etching processes with various process conditions. A study was performed to analyze the effect of these key factors on the results. 3.1. Effect of chamber pressure and gas flow Both etch rate and selectivity are calculated and plotted in Fig. 4(a) and (b). Higher pressure with a high SF6 gas flow gave a faster rate and a higher selectivity because it supplied higher F radical concentrations which enhanced the chemical reaction with Si. As a result, an etch rate in excess of 10 lm/min was obtained on a 63° profile TSV etch, with sidewall roughness of <1 lm, as shown in Fig. 4(c). However, it was challenging to achieve steeper sidewall profiles due to a high lateral etch rate. 3.2. Effect of ICP source power
Fig. 2. Tapered via fabrication by two-step etching (a) after high-rate Bosch etch (18 lm/min); (b) subsequent SF6/O2 isotropic etch, 80° profile at a 30 lm via, but overhang at top.
Fig. 5(a) and (b) indicate that raising ICP power also dramatically increases etch rate in the vertical direction but simultaneously decreases selectivity to mask materials. This decrease of selectivity could limit attaining the desired via etch depth. This is attributed to high ICP source power enhancing the dissociation and ionization of both SF6 and C4F8. The increase of radicals and ions from SF6 was higher than that from the polymer (C4F8)
Z. Ren, M.E. McNie / Microelectronic Engineering 141 (2015) 261–266
263
achievable profiles in the range of 58–76° for 50 lm wide vias, as shown in Fig. 6. When more polymer was deposited on sidewall [10], it effectively suppressed the lateral etch rate. This helped to achieve a steeper profile but decreased vertical etch rate and selectivity. On the other hand, the sidewall became significantly rougher (3 lm) when profile was more than 68°, as shown in Fig. 7. This was due to a reduction of the isotropic etch in the lateral direction and a lack of necessary ion bombardment to effectively remove the polymer in the areas shadowed by the undercutting of the mask. We considered that oxygen ions and radicals would chemically react with Si and then form a thin oxide layer on exposed surface. That would reduce lateral etch rate because of a high etching selectivity of Si to SiO2. Therefore, 5% oxygen was mixed in process gases in order to achieve profile of 70–80° but also improve sidewall roughness. But, Fig. 8 does not show an expected result on profile control, but contrary to what one might suppose, addition of oxygen slightly increased the lateral etch rate. A possible cause was that oxygen species also reacted with CFx polymer at the same time, so that it resulted in less passivation on etched sidewalls. Further increasing oxygen flow would significantly decrease selectivity to PR mask because it has to increase RF bias power at the same time. Key points, using SiF6-O2 chemistry at room temperature, has been systematically discussed in Li’s paper [7].
Fig. 4. (a) and (b) Variation of etch rate and selectivity to both PR and SiO2 with chamber pressures under constant ICP and RF bias powers; (c) 63° sidewall profile of a 50 lm via.
because a gas ratio of SF6:C4F8 was about 6:1. These combined to enhance the physical etching of both the PR and SiO2 masks. 3.3. Effect of gas ratio and addition of oxygen Profile angles in the vias can be controlled by adjustment of C4F8/SF6 gas ratio to control F concentration and polymer formation in the plasma. A series of experiments demonstrated
Fig. 5. (a) and (b) Variation of etch rate and selectivity to both PR and SiO2 with ICP power under constant pressure and gas ratio.
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Fig. 6. Sidewall angle change on TSV profile with increase of C4F8 ratio at a total flow of 624 sccm.
Fig. 8. (a) and (b) Variation of etch rate and selectivity to both PR and SiO2 with ICP power under a constant pressure.
Fig. 7. 76° sidewall profile of a 50 lm via.
Decreasing the temperature enables an SF6-O2 chemistry to form enough SiFxOy polymer during Si etching at a cryogenic temperatures. This condensate offers sidewall protection from the SF6 chemical attack, similar to the role C4F8 plays in Bosch etching. Anisotropic silicon etching can thus be realized, resulting in geometries in which the verticality of the sidewalls is tightly controlled by the passivation rate. Although the etch rate and the passivation rate equations are coupled, various mechanisms for controlling the passivation rate are also separable from the etching rate equation, such as silicon surface temperature and oxygen concentration in the etching plasma. [11]. This enables a sloped profile in via etch process without any mask undercutting, in the range 84–90° – an example is shown in Fig. 9. 3.4. Effect of RF bias power and frequency In Fig. 10(a) and (b), raising RF power (DC bias) changes the etch rate and wall angle only slightly. Higher bias decreased selectivity to masks due to high ion energy. The selectivity was lower for LF bias compared to RF bias for the same bias power, indicating that low frequency contributes a higher fraction of its energy to ion bombardment than 13.56 MHz RF bias. LF RF power with the associated higher bias did however improve surface roughness. The mechanism could be largely related to collision among SFx ions in relatively high pressure
Fig. 9. 84° sidewall profile at a 20 lm via which was achieved by a SF6-O2 process at 100 °C table temperature.
plasma that results in scatter in all directions coupled with ions being able to responding vertically at the exciting LF frequency. The net results are less vertical directionality so that a portion of the ions can enter the shadowed area under the mask and remove polymer better from the surface.
Z. Ren, M.E. McNie / Microelectronic Engineering 141 (2015) 261–266
Fig. 10. (a) and (b) Variation of etch rate and selectivity to both PR and SiO2 with RF bias power under constant ICP power and chamber pressure.
265
Fig. 12. (a) 72° sidewall profiles at a 50 lm via; (b) roughness on sidewall, without any overhang at top.
was successfully realized in a 50 lm wide via with an etch rate of 2 lm/min, a sidewall roughness of <300 nm and no overhang at the top of via – as shown in Fig. 12. Profile curvature was dominated by vertical: lateral etch balance. High aspect ratio vias decrease transport and diffusion effectiveness for etchants and etch by-products. Therefore, a multi-step process with evolving parameters may be employed to effectively maintain this balance with etching depth. 4. Conclusion
Fig. 11. Sidewall curvature and surface roughness change with different ICP power levels.
3.5. Sidewall morphology Usually, monotonic profile angles are always expected for voidfree metal filling. Using a low ICP power with optimization of the aforementioned parameters is advantageous in realizing a low sidewall roughness and curvature – see Fig. 11. A 72° profile via
The ICP plasma dry etching technique for fabrication of tapered vias on Si substrates has been developed by means of a single patterning and etching process, suitable for subsequent void-free filling. Processes using a mixed gas chemistry (SF6/C4F8) have been optimized in terms of the operational parameters such as ICP power, chamber pressure, gas ratio and RF bias power. Monotonic profile angles in the range of 60–80° have been achieved on 10–50 lm wide vias through adjustment of the C4F8/ SF6 ratio. Adjusting the process power also helped sidewall roughness. As a result, an etch rate of 10 lm/min was obtained on 63° profile TSV etch, with sidewall roughness of <1 lm; a 72° profile via was also realized on 20–50 lm wide vias with sidewall roughness of <300 nm and no overhang. This technique will be widely used for MEMS 3D integration and packaging applications such as CMOS cameras where non-vertical vias are required.
266
Z. Ren, M.E. McNie / Microelectronic Engineering 141 (2015) 261–266
Acknowledgments The authors would like to acknowledge both Michael Steel and Colin Welch (Oxford Instruments) for helpful suggestions and Dr. Mike Cooke and Dr. Leslie Lea (Oxford Instruments) for discussions about plasma physics. References [1] J. Leib, F. Bieck, U. Hansen, K. Looi, H. Ngo, V. Seidemann, D. Shariff, D. Studzinski, N. Suthiwongsunthorn, K. Tan, R. Wilke, K. Yam, M. Töpper, IEEE Trans. Adv. Packag. 33 (3) (2010) 713–721. [2] D. Tezcan, N. Pham, B. Majeed, P. Moor, W. Ruythooren, K. Baert, in: Electronic Components and Technology Conference, 2007, pp. 643–647.
[3] F. Laermer, A. Schilp, Verfahren zum anisotropen atzen von silicium, German Patent DE-4241045, 1994. [4] Niclas Roxhed, Patrick Griss, Goran Stemme, J. Micromech. Microeng. 17 (2007) 1087–1092. [5] N. Raganathan, D.Y. Lee, L. Ebin, N. Balasubramanian, K. Prasad, K.L. Pey, J. Micromech. Microeng. 18 (2008) 115028. [6] R.F. Figueroa, S. Spiesshoefer, J. Vac. Sci. Technol. A 23 (5) (2005) 2226–2229. [7] R. Li, Y. Lamy, W.F.A. Besling, F. Roozeboom, P.M. Sarro, J. Micromech. Microeng. 18 (2008) 125023. [8] H. Seidel, L. Csepregi, A. Heuberger, H. Baumgartel, J. Electrochem. Soc. 137 (11) (1990) 3614–3626. [9] M.J. Cooke, G. Hassall, Plasma Sources Sci. Technol. 11 (2002) A74–79. [10] M. Schaepkens, I. Martini, E.A. Sanjuan, X. Li, G.S. Oehriein, W.L. Perry, H.M. Anderson, J. Vac. Sci. Technol. A 19 (6) (2001) 2946–2957. [11] C.C. Welch, A.L. Goodyear, T. Wahlbrink, M.C. Lemme, T. Mollenhauer, Microelectron. Eng. 83 (2006) 1170–1173.