Integrated display components. Review of the international status and trends

190

\~ or]d A hs! rac Is oil M icroclecl ronic~, and 14ella bilii~

The third approach employs the concept of celhilar automata in failure detection and switching flmctions. Finally, the fourth design approach pro\tale,, an uutomatic shift from 2 otlt of 3 lo 2 0 t l l of 2. \~
Pluribus--an operational fault-tolerant multiprocessor. DAVID KA'fSUKI, ERII" S. ELSAM, WIllIAM F. M,~N,',,. ERIC S. ROBERTS, JOIIN G. ROBI'-:SON. I'. SIANI.E; SK(IWRONSKI and ERt(" W. WoI.l. Pr,,c IEEI'. 66, {10t 1146 (October I978). The uuthors describe the Pluribus nmliiprocessor system, outline severa] lechnictucr, used to achie,,e fault-tolerance, describe their lield experience Io date. and mention some potenliul applications. The Pluribtls syblcnl places the major responsibility for recovel \ from failures on the software. Failing hardware modules are removed from the system, spare modules are substituted where available, and appropriate initialization is performed. In applications where the goal is maxintum availability rather thun totally fault-free operation, this approach represents a considerable savings in complexity and cost over Iradilional implementations. The software-based reliability approach has bccn extended to provide error-handling and rccnver~ mccllanisms for the system software structures us well. A nulnber of Pluribus systems have been built and ale currcnth in operation. Experience with these systems has gi\en us confidence in their perfornlancc and nlainlamabilil 3, and leads us to suggest other applications thai inighi bcnulh from this appl-oacll.

F T M P - - a highly reliable fault-tolerant multiprocessor for aircraft. AI.BERI L. HOPKINS, Jr., T. BASU, SMrIH, Ill and JAYNARA;'Att H. [.ALA. Pro~. IEEE 66, (101 1221 (October 197g). F T M P is a digital computer architccl.urc \ditch has evolved over a ten-year period in connection with several life-critical aerospace applications. Most recenlly il ha.', been proposed as a fault-tolerant central computer for civil transport aircraft applications. A working emulation has been operating for some time, and the fir>l cngineering prototype is scheduled to bc completed in late 1970. F T M P is designed to have a failure raic dl.ic It) random causes of the order of 10 i. faihlres pcr hirer, on ten-hour flights where no airborne llmintenuncc is a~ailable. The preferred maintenance interval is of the order of hundreds of flight hours, and the probability that nmintenance will be required earlier thun the preferred inlcrxal is desired to be at most u few percent. The design is based on independent processor-cache memory modules and c o m m o n lllelllOfy modules which communicate via redundant serial bnses. All information processing and transmission is conducted in triplicate so that local \oters in each module can c Modules can be retired u n d e r reassigned ill any conliguration. Reconfiguration is curried Otll routmely from second to second to search for latent faults in the \oting and reconfiguration elements. Job assignments arc all made on a floating basis, so that any processor triad ix eligible to exectite any job step. The core sofl\~are in the f i l M l ' will handle all fault detection, diagno~,is, and l'CCovcly ill such a way that upplicalions progranls do nol need to bc involved Failure-rate models and numerical restihs are described for both permanent and intermittent fauhs. A dispatch probability model is also presented Fxpericnce with an experimental emulation is described.

SIFT: design and analysis of a fault-toleraut computer tot aircraft control. JOIIN H. ~ ' I N S l F ; . l l S l IF l.~\Ml'ln¢ I. I',l k Gl)ll)l~l!P, tk ~'[11 ION W. GRtFN, KARl N [.1',[I ! I) M. ~'1111 IXR-,~MI[II. R¢.)111141 [, NllOSt.\l-. alld (.'It,\RIt{N it, \\rI'INSI()tK. IJt't~t. IItH? 66, (]()l 124~i (Oct,>bci !')7Ni.

SIFT ISoftware hnplementcd I.atllt 1 olcrancc)i> an ultrareliable computer for critical aircraft control applications that achieves fault tolerance by the replicaiioll of tasks a m o n g processing units. The n];lin processing tUlltS ttrt_' offthe-shelf minicoraptlters. ~; ith slandard micl.computer,, ser\ing as the h/terfacc to the I () s\>lCln I a u l t I,a)hiiinrl is achie',cd b\ usin 7 a spc~.ially ,Ic>igned icdtll~diint htl,, s~+stenl to inler,,:onnccl the proces>ing units. EiToi delmctlon and anulysis and ~,y',tcm reconligUlUlion are performed b7 softv, ure. lierati'.¢ tasks arc redundantly executed, and the resLIlis of each iteration arc \oleo llpon bctiwe being nscd. Thus. any single failure in a prc)cessillg mill nr bus olin be Iolerated ~sith lrip]ication of tasks, und silbseqtlenl fuihn-es can bc tolerated aftcr rcconfiguration. Independent exectltion b} sepalal.e processors II]Calls thai the f,rnccssor~ need onl 3 he to{~sch synchroniicd, und a nu~ct lau[ttolerant ~,vnclnoniialion int-'thod ix de>clibcd fl,c SIFI sofl\~.are is highl~ '-;tri.lcturcd alld i!i fofnlall\ spc:cilicd rising the SR l-developed SPE( 'IA 1. ]allguagc. The col i-eclncss of SIET is to bc proved usmg a hiennch~ ,,i J})rlna] 111odcls. '\ Mal'ko~ model ix used t',oth to Linal\,/c thc reliabilit_\ of tilt_' "QslCln and {t> s c l \ c tlS lht' J\)i!lla{ requirement for the SIF'T design..,\xioms are given t,, characterile the high-level behavior of the systcm, n-ore which a correctness slatenlent ha~, been pro\ed. ~n engineering lesl ~ersion of SII-:'T ix currenlt 3 being buill

Fault-tolerant design of local ESS processors. 'A. N. -I¢!~ Prec. IEEE 66, II0t 1126 IOctobcr It~78). The stored program control of Bell System Flectronic Switching S~slems (ESS~ has been under development since 1953. During this period, the No. I ESS, the No. 2 ESS. and the Nt~. 3 ISS ha~c been dc~eloped and used extensively by Bell System operating companies to provide commercial lclephone ser\i~:e. These s'~stcms serxe a[] lypcs of telephnnc oltices: f h e largc-capaci O No. 1 ['SS serves metropolitan offices, the medium-capacity No. 2 ESS ~as designed for suburban offices, and the No. 3 ESS can bc found in many small rural oflices. Fhe fault tolerant design of IrSS processors pzovides the same highly dependable telephone service established by the prexious electro-lnechanical systems. Pertinent processor architecture features used to uchicve f S S reliability objectives are discussed \ detailed discussion of the maintcncincc design nf lht_, I,\ l)l()CCSXt)l- i,, also inchidcd.

A case stud)' of C. romp, Cm*, and ( . vmp: part i - Experiences with fault tolerance in multiproce~or systems. DANIEI, P. SIIWIOREK, VITIAI KINL HFNRY ]~ASIIBURN, SIEPHI/N M('('ONNt!I. und MIf'HAtl. FSA(I. Dt'nt. IEIzE 66,

I lOI 1178 (October 1078). Three multiprocessor systems designed, implemented, and currently operational at ('arnegie Mellon University are compared and central, ted. The design goals and architectures are summarized with a special focus on reliability features. Experiences gamed in design and operation ure discussed Finally. reliability data. ~ith a focus on trunsienl faihlrcs, measured fl'om each system are presenled and discussed

4. M I C R O E L E C T R O N I C S Integrated display components. Review of the international status and trends. W. }tEIDtIORN. .Vachrichtentechnik Eh'ktt'otlik 28, (9) 35(~ ll97SI. {In (JCflnanL ()v~ing to the

GENERAL

growing technical possibilities of microelectronic circuits a continuous increase of the information capacity of display c o m p o n e n l s ix reqnired. B) s y s t e m a l i : h l g the c o m p o n e n t

World Abstracts on Microelectronics and Reliability complex with a high information capacity an attempt is made to estimate the further trend of development on the basis of the status attained. Possible variants of realizing information displays include the consideration of the plasma display, injection luminescence, electroluminescence, liquid crystals, and vacuum tube. Common market eyes VLSI effort. JAMESSMITH. Electronics p. 92 (28 September 1978). It is almost impossible to get factional national electronics producers together on advanced projects in computers or microelectronics, but Common Market experts are trying anyway. Their goal: to remedy Western Europe's dangerously growing gap in very-large-scale integrated-circuit technology. Microcomputers do on-chip a-d conversion. Electronics p. 67 (20 July 1978). One-chip controllers from two Japanese companies have software to accomplish analog-to-digital conversion. Techmology update. Electronics p. 110 (26 October 1978). Semiconductor technology continues to be the engine that drives electronics past existing limits. And 1978 has proved no exception, as semiconductor manufacturers pass the threshold of a new era ushered in by very large-scale integration. The announcement of the first 64-K randomaccess memory and the entry into the 16-bit realm by micro-computer chip families signal the advent of devices with unprecedented density and performance. The ultimate effect stretches the imagination, but already the capabilities afforded by VLSI are breaking new ground as minicomputer manufacturers turn to new architectures built around high-performance chips, as communications engineers plan systems with the growing supply of chip codecs, as instruments that intelligently measure and manipulate signals proliferate, and as talking toys delight and enlighten children. All these presage another remarkable year ahead. Second-generation microcontrollers take on dedicatedfunction tasks. JOHN BEASTON. Electronics p. 127 (23 November 1978). Two new series further reduce demands on microcomputer system's CPU, increasing system throughput and reliability while simplifying design.

5. M I C R O E L E C T R O N I C S

Equipment costs worry chip makers. WILLIAM F. ARNOLD. Electronics p. 87 (23 November 1978). Added to the costs of R & D needed to keep up with VLSI, prices could cause next shakeout of semiconductor companies. Tackling the very large-scale problems of VLSi: a special report. RAYMOND P. CAPECE. Electronics p. 111 (23 November 1978). From tens of devices per chip Io tens of thousands the increase over the last few years in the number of transistors in an integrated circuit has been nothing less than explosive. But the growth process has been evolutionary, not revolutionary. Continual process improvements and the confidence gained with the production of hundreds of thousands of chips per month have enabled manufacturers to shrink transistor dimensions and increase producible die sizes. But now the increasing complexity of logic circuits, layout topology, and lithographic processes have compounded to create a design-management problem of mammoth proportions. Anticipating unprecedented design problems and greater risks of investment capital, manpower, and development time than ever before, leading-edge semiconductor manufacturers have initiated long-term programs to address the challenge of what has come to be called very largescale integration. A prognosis of the impending intercontinental LSI battle. IAN M. MACKINTOSH. Microelectron. J. 9, (2) 24 (1978). Ever since the inventions of the integrated circuit and the silicon planar process, American semiconductor producers have dominated the world markets for ICs. especially at the leading-edge of each new generation of technology. This is certainly the ease today for products of LSI complexity. However, there are increasing signs that things might be changing. For example, competitive memory products are now being produced in substantial quantities in Japan, and there is a growing interest by European companies in acquiring a stake in US semiconductor companies. A key question, therefore, is whether the global domination by American IC companies will be seriously threatened, particularly as the VLSI era approaches, and it is to au examination of the major facets of this question that this paper is directed.

DESIGN

Recombination level selection criteria for lifetime r&luction in integrated circuits. B. JAYANT BALIGA. Solid-St. Electron. 21, 1033 (1978). In the past, lifetime control in integrated circuits has been done on an empirical basis. This paper introduces selection criteria for recombination centers which are to be used for reducing minority carrier lifetime in integrated circuits. It is shown that the recombination level should have a large lifetime ratio (rsc/~,D in order to obtain minority carrier lifetime reduction with minimal increase in the leakage current, and should possess large capture cross section values in order to minimize compensation effects. Using these criteria, preferred locations for the recombination center have been defined for both p and n type silicon, and the trade-off between reduction of lifetime and increase in leakage current has been shown to degrade with increase in resistivity and ambient temperature. These criteria have also allowed a quantitative comparison between various lifetime control techniques for the first time, and platinum doping has been identified as the most favorable lifetime control process at the present time.

191

AND

CONSTRUCTION

A van der Pauw resistor structure for determining mask superposition errors on semiconductor slices. DAVID S. PERLOFF. Solid-St. Electron. 21, 1013 (1978. A symmetric eight-point van der Pauw resistor structure is described which makes it possible to determine the x- and ),-axis vector components of mask superposition error on specially processed semiconductor slices. The structure is fabricated by first delineating a corner-contacted square van der Pauw resistor geometry. A second masking step adds sensor arms at the midpoints of the sides of the square body if the two masks have been correctly superimposed. The actual location of the sensor arms is determined by carrying out a series of four-point resistance measurements after doping the structure. Control geometries, in which the eight sensor arms are delineated on the same masking step, are used to investigate the accuracy and precision of the measurement technique. It is found that the vector components of mask superposition error can be determined, in the absence of mask-to-mask registration errors, with an absolute accuracy in the range _+O.101Lm and standard error below 0.015/tm. Examples of vector displacement maps are pre-