- Email: [email protected]
Integrated on-chip solid state capacitor based on vertically aligned carbon nanofibers, grown using a CMOS temperature compatible process
Solid State Electronics 139 (2018) 75–79
Contents lists available at ScienceDirect
Solid State Electronics journal homepage: www.elsevier.com/locate/sse
Integrated on-chip solid state capacitor based on vertically aligned carbon nanofibers, grown using a CMOS temperature compatible process
MARK
⁎
Amin M. Saleema,b, , Rickard Anderssona, Vincent Desmarisa, Peter Enokssona,b a b
Smoltek AB, Regnbågsgatan 3, Gothenburg SE-41755, Sweden Department of Microtechnology and Nanoscience, Chalmers University of Technology, Gothenburg SE-41755, Sweden
A R T I C L E I N F O
A B S T R A C T
The review of this paper was arranged by Prof. A. Zaslavsky
Complete miniaturized on-chip integrated solid-state capacitors have been fabricated based on conformal coating of vertically aligned carbon nanofibers (VACNFs), using a CMOS temperature compatible microfabrication processes. The 5 µm long VACNFs, operating as electrode, are grown on a silicon substrate and conformally coated by aluminum oxide dielectric using atomic layer deposition (ALD) technique. The areal (footprint) capacitance density value of 11–15 nF/mm2 is realized with high reproducibility. The CMOS temperature compatible microfabrication, ultra-low profile (less than 7 µm thickness) and high capacitance density would enables direct integration of micro energy storage devices on the active CMOS chip, multi-chip package and passives on silicon or glass interposer. A model is developed to calculate the surface area of VACNFs and the effective capacitance from the devices. It is thereby shown that 71% of surface area of the VACNFs has contributed to the measured capacitance, and by using the entire area the capacitance can potentially be increased.
Keywords: CNFs CMOS Capacitor On-chip Integrated
1. Introduction The public demand to have even smarter, thin, small and lightweight electronic devices with enhanced performance and data processing speed requires further miniaturization of micro-devices and also more devices on the active CMOS chip. Technologically, it translates to a need for high energy density capacitors integrated directly on CMOS chip to power up on-chip devices, and for decoupling purposes with minimized current path. In fact, the industry is currently deploying 3-D and 2.5-D integration technologies containing devices including energy sources on passive silicon or glass interposer which are required to power up the devices present on the CMOS chip or interposer. In addition, the simultaneous switching of the devices on the chip draws high current, which results in the drop of power supply voltage below the threshold level, creating ripples in the power. Therefore, decoupling capacitors are used which compensate the voltage by releasing energy when the voltage drops below the tolerable level. Moreover these capacitors can also bypass the high frequency noise. The decoupling capacitors should be mounted close to the power terminals of the devices to minimize the current path for better efficiency [1]. In fact, the long current path generates an equivalent series inductance (ESL), which generates impedance variation in power delivery causing the capacitor to be less effective.
⁎
Corresponding author at: Smoltek AB, Regnbågsgatan 3, Gothenburg SE-41755, Sweden. E-mail address: [email protected] (A.M. Saleem).
http://dx.doi.org/10.1016/j.sse.2017.10.037 Received 11 October 2017; Accepted 14 October 2017 Available online 16 October 2017 0038-1101/ © 2017 Elsevier Ltd. All rights reserved.
Electrochemical double layer capacitors (EDLC), also called supercapacitors, are good candidates because of their high areal specific capacitance [2]. High surface area, conductive and chemically inert materials such as carbon nanomaterials [3] are used as electrode materials in the supercapacitor, and liquid or sol-gel electrolytes as source of ions [4]. The energy is stored by physical adsorption of ions at the surface of electrode materials creating a very thin (a few angstrom) layer of dielectric, thus providing high specific capacitance and long cycle-life (approx. 1 million). However, the liquid electrolytes are often toxic and corrosive, and their integration directly on CMOS chips presents a big challenge. Solid polymer-gel electrolytes based supercapacitors have potential for direct integration on the chip in which the electrolyte and electrode materials are embedded inside the gel thus creating a packaging of supercapacitor. The physical separation of the electrodes helps to eliminate the need of separator materials however the electrolytes face low ionic conductivity problem at room temperature [4]. On the other hand, traditional parallel plate capacitor architecture combined with thin (few nm in thickness) solid dielectric layer and high surface area electrode can also give high areal capacitance at particular footprint area. High areal specific capacitance 58 nF/mm2 was achieved by making deep trenches in silicon [5]. Both the insulator to isolate the substrate from the capacitor and the dielectric materials are deposited by LPCVD technique. However, the trenches are fabricated using Bosch
Solid State Electronics 139 (2018) 75–79
A.M. Saleem et al.
rate of 20/500 ms, Fig. 1d. To define the top electrode, a stack of metals Ti/Au (30/1000 nm in thickness) was sputtered followed by photolithography leaving the resist at the top electrode location. Finally the bare Titanium/gold layers are etched away by wet and dry etching technique, Fig. 1e. The intended capacitance to be measured is shown in Fig. 2a, however the thick oxide between the probe pads and the silicon substrate can build capacitors connected in series, which could be the potential source of parasitic capacitance, Fig. 2b. To measure the parasitic capacitance of the formed capacitor, capacitors of different dimensions are fabricated. By extrapolating capacitance vs area plot, the parasitic capacitance can be extracted. The basic reference parallel plate capacitors without carbon nanofibers are also fabricated for comparison. The scanning electron microscopy (SEM) analysis of VACNFs after growth and dielectric coating was performed using JEOL JSM-6301F. The images were taken at 40° tilt angle to see the morphology, and to measure the length of VACNFs. Finally, the capacitance of the capacitor was measured at 1 kHz frequency using a LCR meter coupled to two tungsten probes, one of which punched though the ALD layer to contact the bottom electrode.
process, which is time consuming, expensive and also irreversible if any problem occurs during trenches fabrication. Moreover, deep trenches in the silicon substrate make the chip mechanically weaker and vulnerable to defects due to warpage. The atomic layer deposition (ALD) is another technique to deposit dielectric which deposits materials layer by layer giving better step coverage, morphology and textures of the deposited film. The ALD technique can enhance the capacitance by utilizing the surface area inside the small pores. The specific capacitance of 440 nF/ mm2 is achieved from the deep trenches by depositing aluminum oxide (Al2O3) dielectric and titanium nitride (TiN) top metal using ALD technique in multilayer capacitor [6]. Multilayer capacitors are also made in trenches with an improved LPCVD method, and even higher specific capacitance 527 nF/mm2 is obtained [7]. Recently IPDiA (now Murata) has shown 500 nF/mm2 capacitor integrated in the silicon interposer with minimum die thickness 100 µm [8]. Carbon nanostructures are also investigated to make solid state capacitor, in combination to the deposition of thin dielectric layer using ALD. However the temperature growth of the carbon nanotubes prevents their direct growth on CMOS chip whereas the transfer process adds extra cost to final product. Therefore, until such approach comes at the cost of additional fabrication step, since the growth temperature of the carbon nanostructures is traditionally well above CMOS compatible temperature. For example, the carbon nanotubes (CNTs) were first grown at 700–750 °C on silicon substrate and then transferred on the desired substrate. The dielectric thickness of 15–40 nm gives specific capacitance of ∼120 nF/mm2 at 100–10 kHz frequency [9]. The shorter CNTs (ca. 2 µm in length) grown at lower temperature 500 °C were also used to make capacitor in which both the Al2O3 dielectric and TiN top metal of thickness 15 nm each were deposited by ALD. The specific capacitance value was high ∼42 nF/mm2 however the original device size (0.0025 mm2) was small and corresponding capacitance (106 pF) was not practical [10]. In the present work, solid state capacitors based on vertically aligned carbon nanofibers (VACNFs) that can be grown directly on the active CMOS chip and hence integrated, are demonstrated [11]. The fabrication can be carried out using a proven CMOS compatible process [12]. The specific capacitance 10–15 nF/mm2 is obtained at 1 kHz frequency.
3. Results and discussion The tilted view SEM images show that CNFs are different both in length and shape, Fig. 3a. The thin CNFs are sparse with length 4.6–5 µm, however the lengths of shorter CNFs are 1.9–2.3 µm. The ALD deposition of Al2O3 shows that dielectric is coated homogeneously and uniformly, without damaging both CNFs and dielectric, Fig. 3b, also previously shown using HRTEM [14]. The top view of the CNFs after dielectric coating and top metal coating clearly show the difference in the diameters, Fig. 3c. Fig. 4a shows the SEM image of a complete three dimensional solid state capacitor which is intended to be integrated directly on CMOS chip. Because of the CMOS temperature compatible processing, the layout of the capacitor can easily be tailored without further processing step. Moreover, the profile of the capacitor is less than 7 um making it an ultra-low profile capacitor which can easily be integrated into multi-chip packages and future interposer technology (see Table 1). The capacitances measured at 1 kHz frequency for different footprint areas capacitors are given in Fig. 4b. The equivalent parallel resistances, measured by the LCR were typically 1.9 MΩ, indicating a rather suitable conformal (I.e. void-free) deposition of the Al2O3. We therefore can see that the capacitance with CNFs is 7–9 times higher than the capacitance of a parallel plate capacitance with the same footprint area showing the real 3D capacitive effect of CNFs. A complete integrated solid state capacitor of capacitance up to 8 nF is fabricated and verified. In addition, a parasitic capacitance of very small value (185 pF) is observed by extrapolating capacitance Vs capacitor area plot, which could potentially originate from the parasitic capacitor between contact pads or bottom electrode and silicon substrate through the silicon oxide as discussed earlier. To verify that, the parasitic capacitance is from probe pads and silicon substrate is calculated. The dimensions of the single probe pad are105 µm × 105 µm and there are two dielectric layers of silicon oxide and aluminum oxide with thicknesses around 400 nm and 50 nm respectively and only silicon oxide under second pad, Fig. 2b. All three parasitic capacitors are connected in series resulting in very small capacitance values 121 fF. Furthermore the
2. Experiments A complete fabrication of on-chip integrated dielectric solid state capacitor is shown in Fig. 1. A 4-in. oxidized (500 nm SiO2) p-type silicon wafer was used as a substrate. The bottom current collector (CC) including a probing pad was defined by photolithography, followed by a sputtered metal stack of Ti/Au (20/50 nm in thicknesses) and lift-off. The metal catalyst, required to grow carbon nanofibers, was then deposited using electron beam evaporation. Vertically aligned CNFs are grown on the bottom current collector using a direct current plasma enhanced chemical vapor deposition (DC-PECVD) method at a monitored sample temperature of 390 °C and a plasma current of 300 mA, similar to [13]. A combination of acetylene and ammonia gas was used for growth of the VACNFs where the acetylene is a carbon source and ammonia is a carrier gas which also etches back the amorphous carbon. Thermal ALD technique was used for conformal coating of dielectric Al2O3 on VACNFs. The precursor trimethylealuminium (TMA) and water were used to deposit 50 nm thick layer of Al2O3 at substrate temperature of 300 °C at a pressure of 80 mtorr and a pulsing/purging
Fig. 1. (a) fabrication of bottom current collector, (b) catalyst deposition, (c) VACNFs growth, (d) conformation coating of dielectric, and (e) top current collector deposition.
76
Solid State Electronics 139 (2018) 75–79
A.M. Saleem et al.
Fig. 2. Schematic diagram of (a) measured capacitance and (b) parasitic series capacitance.
and the shorter (hS: 2 μm) CNFs. The numbers of longer (nL) and shorter (nS) CNFs are counted from the SEM picture where the shorter and longer CNFs are marked with circles and squares respectively, Fig. 3c, and total numbers of longer (NL) and shorter (NS) CNFs on area A are counted. The total CNFs surface area and empty metal area are then calculated using Eqs. (1) and (2).
difference between the measured capacitance and parallel plate capacitance for the devices without fibers (Table 2) is smaller than 5%, which is within the measurement accuracy of the data. Therefore the eventual contribution parasitic of a capacitance between the bottom electrodes of the capacitors and the Silica on substrate can be considered negligible, especially for capacitors made out of CNFs. A model is suggested to estimate the surface area of the VACNFs contributing to the capacitance, Table 2. A 420 × 630 µm2 area (A) capacitor is used for this purpose and the CNFs in contact with this area are active for capacitance. For an ordinary parallel plate capacitor without CNFs the calculated capacitance (423 pF) and measured capacitance (398 pF) have almost same values. However the total capacitance in CNFs based capacitor is the sum of capacitance from the CNFs and the empty bottom CC layer between the CNFs. The areas contributing to the total capacitance are shown by dashed lines marked with circle 1, 2 and 3 in the schematic diagram, Fig. 5. To calculate the capacitance due to bottom CC surface, the empty metal area is calculated by subtracting the CNFs area in contact with bottom CC from the capacitor footprint area. To proceed for calculation, all the CNFs are considered as uniform cylinders of same radius (r: 100 nm), and the average lengths are taken for the longer (hL: 4.8 μm)
Total surface area of the CNFs = NL × (2π rhL + π 2r ) + Ns × (2π rhS + πr 2)
(1)
Total CNFs(N) = NL + NS Since the radius of all CNFs is same
Empty metal area = A−CNFs area( N× πr 2)
(2)
The contact area of the CNFs is 35,413 µm2 and unfilled surface area of the bottom metal attained using Eq. (2) is 229,187 µm2 and finally the surface area of CNFs is 2,718,933 µm2, see Table 2. The calculated capacitances contributed by CNFs and unfilled CC area are 4.34 nF and 366 pF respectively. The calculated capacitance from the empty metal area is 12 times lower than the capacitance from the CNFs. The calculated capacitance from the unfilled area is subtracted from the
Fig. 3. SEM images of (a) VACNFs, (b) Al2O3 coated CNFs, and (c) Al2O3 and top metal coated CNFs top view.
77
Solid State Electronics 139 (2018) 75–79
A.M. Saleem et al.
Fig. 4. (a) A complete Solid state capacitor (b) capacitance measurement on CNFs and parallel capacitors.
Table 1 Average capacitance vs footprint area.
VACNFs electrode
Area (mm2)
Footprint area factor
Capacitance from CNFs (nF)
Parallel plate capacitance (nF)
0.088 0.088 0.265 0.265 0.352 0.529 0.706
1 1 3 3 4 6 8
0.990 1.180 3.450 3.160 4.250 6.540 8.0
0.133 0.132 0.398 0.397
Table 2 Values to calculate surface area of CNFs and capacitance from CNFs. X dimension of parallel plate capacitor (µm) Y dimension of parallel plate capacitor (µm) Area of the plate (µm2) Dielectric thickness (nm) Theoretical Capacitance of parallel capacitor (nF) Measured capacitance on capacitor without CNFs (nF)
420 630 264,600 50 0.423 0.398
Length of the longer CNFs (hL) (µm) Number of longer CNFs in SEM picture (nL) Length of the shorter CNFs (hS) (µm) Number of shorter CNFs in SEM picture (nS) Area of the picture (µm2) Surface area of shorter CNFs in SEM image (µm2) Surface area of longer CNFs in SEM image (µm2) Total Surface of CNFs in the SEM image (µm2) Surface of CNFs per µm2 Surface area of CNFs on 420 × 630 µm2 area(µm2) Theoretical Capacitance of CNFs (nF) Measured Capacitance from CNFs at 1 kHz (nF)
4.8 23 2 13 8.446 16.736200 70.053400 86.7896 10.2756357 2718933.207 4.34 3.45
Fig. 5. Cross section diagram of the CNFs chip.
measured capacitance (3.45 nF) to get the capacitance contributed by the CNFs (3.085 nF). The value of measured capacitance contributed by the CNFs is 71% of the calculated capacitance. The lower measured capacitance value is potentially caused by the low level conformal coating of top metal which is further confirmed by the SEM of image of the top metal electrode as shown in Fig. 6. The considerable protrusion of top metal ∼1 µm above the dielectric coated CNFs highlighted with red box confirms the partial covering of the CNFs by the metal. Nevertheless the capacitance can potentially be enhanced by conformal coating of the top CC using ALD technique and also by filling unfilled CC area with CNFs of similar dimension. Finally the capacitor is modelled using an equivalent electrical circuit and verified using keysight ADS, Fig. 7a. The impedance and phase are plotted for frequency up to 10 kHz, Fig. 7b. The model fit well with the experimental data.
Fig. 6. SEM picture of protruded top metal.
4. Conclusion Integrated on-chip solid state capacitors are fabricated based on vertically aligned carbon nanofibers and very thin layer of dielectric using CMOS temperature compatible fabrication processes. The capacitors are ultra-low profile (below 10 µm in height) and have considerable freedom of layout customization making them possible to integrate directly on active CMOS chip, or interposer. The specific capacitance 11–15 nF/mm2 is measured at 1 kHz frequency, and a full 78
Solid State Electronics 139 (2018) 75–79
A.M. Saleem et al.
Fig. 7. (a) Equivalent electrical circuit and (b) impedance and phase vs frequency model.
capacitor of capacitance value 8 nF on 0.5 mm2 is fabricated. A model is also developed to show that only ca 71% surface area of CNFs is contributing for the capacitance and by utilizing the entire surface the capacitance can further be increased.
id=97. [Accessed 21 12 2016]. [9] Pint CL, Nicholas NW, Xu S, Sun Z, Tour JM, Schmidt HK, et al. Three dimensional solid-state supercapacitors from aligned single-walled carbon nanotube array templates. Carbon 2011;49:4890–7. http://dx.doi.org/10.1016/j.carbon.2011.07.011. [10] Fiorentino G, Vollebregt S, Tichelaar F, Ishihara R, Sarro PM. Impact of the atomic layer deposition precursors diffusion on solid-state carbon nanotube based supercapacitors performances. Nanotechnology 2015;26:064002. http://dx.doi.org/10. 1088/0957-4484/26/6/064002. [11] Ghavanini FA, Poche HL, Jonas B, Saleem AM, Kabir MS, Lundgren P, et al. Compatibility assessment of CVD growth of carbon nanofibers on bulk CMOS devices. Nano Lett 2008;8(8):2437–41. http://dx.doi.org/10.1021/nl801397j. [12] Desmaris V, Saleem AM, Shafiee S, Berg J, Kabir MS, Johansson A. Carbon nanofibers (CNF) for enhanced solder-based nano-scale integration and on-chip interconnect solutions. In: 64th electronic components and technology conference (ECTC), IEEE; 2014. p. 1071–6. doi: http://dx.doi.org/10.1109/ECTC.2014. 6897421. [13] Saleem AM, Shafiee S, Krasia-Christoforou T, Savva I, Göransson G, Desmaris V, et al. Low temperature and cost-effective growth of vertically aligned carbon nanofibers using spin-coated polymer-stabilized palladium nanocatalysts. Sci Technol Adv Mater 2015;16:015007. http://dx.doi.org/10.1088/1468-6996/16/1/015007. [14] Malek GA, Brown E, Klankowski SA, Liu J, Elliot AJ, Lu R, et al. Atomic layer deposition of Al-doped ZnO/Al2O3 double layers on vertically aligned carbon nanofiber arrays. ACS Appl Mater Interfaces 2014;6:6865–71. http://dx.doi.org/10. 1021/am5006805.
Acknowledgement The author will like to thank Smoltek AB for the financial support to conduct this research. References [1] Popovich M. Effective radii of on-chip decoupling capacitors. IEEE Trans Very Large Scale Integr (VLSI) Syst 2008;16(7):894–907. http://dx.doi.org/10.1109/TVLSI. 2008.2000454. [2] Saleem MA, Göransson G, Desmaris v, Enoksson P. CMOS compatible on-chip decoupling capacitor based on vertically aligned carbon nanofibers. Solid-State Electron 2015;107:15–9. http://dx.doi.org/10.1016/j.sse.2015.01.022. [3] Saleem AM, Desmaris V, Enoksson P. Performance enhancement of carbon nanomaterials for supercapacitors. J Nanomater 2016;2016. http://dx.doi.org/10.1155/ 2016/1537269. [4] Saleem AM, Andersson R, Song B, Wong CP, Desmaris V. On-chip integrated solidstate micro-supercapacitor. In: 67th electronic components and technology conference (ECTC), IEEE; 2017. p. 173–8. doi: http://dx.doi.org/10.1109/ECTC.2017. 135. [5] Johari H, Ayazi F. High-density embedded deep trench capacitors in silicon with enhanced breakdown voltage. IEEE Trans Compon Packag Technol 2009;32(4):808–14. http://dx.doi.org/10.1109/TCAPT.2009.2024210. [6] Klootwijk JH, Jinesh KB, Dekkers W, Verhoeven JF, van den Heuvel FC, Kim H-D, et al. Ultrahigh capacitance density for multiple ALD-grown MIM capacitor stacks in 3-D silicon. IEEE Electron Device Lett 2008;29(7). http://dx.doi.org/10.1109/LED. 2008.923205. [7] Aminulloh A, Kumar V, Yang SM, Sheu G. Novel structure of deep trench capacitor with higher breakdown and higher capacitance density for low dropout voltage regulator. In: IEEE 10th international conference on power electronics and drive systems (PEDS). Kitakyushu International Conference Center; 2013. doi: http://dx. doi.org/10.1109/PEDS.2013.6527050. [8] Nodet F. http://www.ipdia.com/index.php?page=news&item_id=97, IPDiA, 19 10 2016. [Online]. Available: http://www.ipdia.com/index.php?page=news&item_
Muhammad Amin Saleem is currently working as a research engineer at Smoltek AB. He recently received Ph.D. degree from Chalmers University of Technology, Sweden and his main research interests are the different applications of carbon nanostructures. He received his M.Sc. degree in nanoscale science and technology in 2006 from Chalmers University of Technology, after which he worked as a research assistant with the Atomic Physics Department, Gothenburg University, until 2007. From 2007 to 2012, he worked as a processing engineer at Smoltek AB.
79
Contents lists available at ScienceDirect
Solid State Electronics journal homepage: www.elsevier.com/locate/sse
Integrated on-chip solid state capacitor based on vertically aligned carbon nanofibers, grown using a CMOS temperature compatible process
MARK
⁎
Amin M. Saleema,b, , Rickard Anderssona, Vincent Desmarisa, Peter Enokssona,b a b
Smoltek AB, Regnbågsgatan 3, Gothenburg SE-41755, Sweden Department of Microtechnology and Nanoscience, Chalmers University of Technology, Gothenburg SE-41755, Sweden
A R T I C L E I N F O
A B S T R A C T
The review of this paper was arranged by Prof. A. Zaslavsky
Complete miniaturized on-chip integrated solid-state capacitors have been fabricated based on conformal coating of vertically aligned carbon nanofibers (VACNFs), using a CMOS temperature compatible microfabrication processes. The 5 µm long VACNFs, operating as electrode, are grown on a silicon substrate and conformally coated by aluminum oxide dielectric using atomic layer deposition (ALD) technique. The areal (footprint) capacitance density value of 11–15 nF/mm2 is realized with high reproducibility. The CMOS temperature compatible microfabrication, ultra-low profile (less than 7 µm thickness) and high capacitance density would enables direct integration of micro energy storage devices on the active CMOS chip, multi-chip package and passives on silicon or glass interposer. A model is developed to calculate the surface area of VACNFs and the effective capacitance from the devices. It is thereby shown that 71% of surface area of the VACNFs has contributed to the measured capacitance, and by using the entire area the capacitance can potentially be increased.
Keywords: CNFs CMOS Capacitor On-chip Integrated
1. Introduction The public demand to have even smarter, thin, small and lightweight electronic devices with enhanced performance and data processing speed requires further miniaturization of micro-devices and also more devices on the active CMOS chip. Technologically, it translates to a need for high energy density capacitors integrated directly on CMOS chip to power up on-chip devices, and for decoupling purposes with minimized current path. In fact, the industry is currently deploying 3-D and 2.5-D integration technologies containing devices including energy sources on passive silicon or glass interposer which are required to power up the devices present on the CMOS chip or interposer. In addition, the simultaneous switching of the devices on the chip draws high current, which results in the drop of power supply voltage below the threshold level, creating ripples in the power. Therefore, decoupling capacitors are used which compensate the voltage by releasing energy when the voltage drops below the tolerable level. Moreover these capacitors can also bypass the high frequency noise. The decoupling capacitors should be mounted close to the power terminals of the devices to minimize the current path for better efficiency [1]. In fact, the long current path generates an equivalent series inductance (ESL), which generates impedance variation in power delivery causing the capacitor to be less effective.
⁎
Corresponding author at: Smoltek AB, Regnbågsgatan 3, Gothenburg SE-41755, Sweden. E-mail address: [email protected] (A.M. Saleem).
http://dx.doi.org/10.1016/j.sse.2017.10.037 Received 11 October 2017; Accepted 14 October 2017 Available online 16 October 2017 0038-1101/ © 2017 Elsevier Ltd. All rights reserved.
Electrochemical double layer capacitors (EDLC), also called supercapacitors, are good candidates because of their high areal specific capacitance [2]. High surface area, conductive and chemically inert materials such as carbon nanomaterials [3] are used as electrode materials in the supercapacitor, and liquid or sol-gel electrolytes as source of ions [4]. The energy is stored by physical adsorption of ions at the surface of electrode materials creating a very thin (a few angstrom) layer of dielectric, thus providing high specific capacitance and long cycle-life (approx. 1 million). However, the liquid electrolytes are often toxic and corrosive, and their integration directly on CMOS chips presents a big challenge. Solid polymer-gel electrolytes based supercapacitors have potential for direct integration on the chip in which the electrolyte and electrode materials are embedded inside the gel thus creating a packaging of supercapacitor. The physical separation of the electrodes helps to eliminate the need of separator materials however the electrolytes face low ionic conductivity problem at room temperature [4]. On the other hand, traditional parallel plate capacitor architecture combined with thin (few nm in thickness) solid dielectric layer and high surface area electrode can also give high areal capacitance at particular footprint area. High areal specific capacitance 58 nF/mm2 was achieved by making deep trenches in silicon [5]. Both the insulator to isolate the substrate from the capacitor and the dielectric materials are deposited by LPCVD technique. However, the trenches are fabricated using Bosch
Solid State Electronics 139 (2018) 75–79
A.M. Saleem et al.
rate of 20/500 ms, Fig. 1d. To define the top electrode, a stack of metals Ti/Au (30/1000 nm in thickness) was sputtered followed by photolithography leaving the resist at the top electrode location. Finally the bare Titanium/gold layers are etched away by wet and dry etching technique, Fig. 1e. The intended capacitance to be measured is shown in Fig. 2a, however the thick oxide between the probe pads and the silicon substrate can build capacitors connected in series, which could be the potential source of parasitic capacitance, Fig. 2b. To measure the parasitic capacitance of the formed capacitor, capacitors of different dimensions are fabricated. By extrapolating capacitance vs area plot, the parasitic capacitance can be extracted. The basic reference parallel plate capacitors without carbon nanofibers are also fabricated for comparison. The scanning electron microscopy (SEM) analysis of VACNFs after growth and dielectric coating was performed using JEOL JSM-6301F. The images were taken at 40° tilt angle to see the morphology, and to measure the length of VACNFs. Finally, the capacitance of the capacitor was measured at 1 kHz frequency using a LCR meter coupled to two tungsten probes, one of which punched though the ALD layer to contact the bottom electrode.
process, which is time consuming, expensive and also irreversible if any problem occurs during trenches fabrication. Moreover, deep trenches in the silicon substrate make the chip mechanically weaker and vulnerable to defects due to warpage. The atomic layer deposition (ALD) is another technique to deposit dielectric which deposits materials layer by layer giving better step coverage, morphology and textures of the deposited film. The ALD technique can enhance the capacitance by utilizing the surface area inside the small pores. The specific capacitance of 440 nF/ mm2 is achieved from the deep trenches by depositing aluminum oxide (Al2O3) dielectric and titanium nitride (TiN) top metal using ALD technique in multilayer capacitor [6]. Multilayer capacitors are also made in trenches with an improved LPCVD method, and even higher specific capacitance 527 nF/mm2 is obtained [7]. Recently IPDiA (now Murata) has shown 500 nF/mm2 capacitor integrated in the silicon interposer with minimum die thickness 100 µm [8]. Carbon nanostructures are also investigated to make solid state capacitor, in combination to the deposition of thin dielectric layer using ALD. However the temperature growth of the carbon nanotubes prevents their direct growth on CMOS chip whereas the transfer process adds extra cost to final product. Therefore, until such approach comes at the cost of additional fabrication step, since the growth temperature of the carbon nanostructures is traditionally well above CMOS compatible temperature. For example, the carbon nanotubes (CNTs) were first grown at 700–750 °C on silicon substrate and then transferred on the desired substrate. The dielectric thickness of 15–40 nm gives specific capacitance of ∼120 nF/mm2 at 100–10 kHz frequency [9]. The shorter CNTs (ca. 2 µm in length) grown at lower temperature 500 °C were also used to make capacitor in which both the Al2O3 dielectric and TiN top metal of thickness 15 nm each were deposited by ALD. The specific capacitance value was high ∼42 nF/mm2 however the original device size (0.0025 mm2) was small and corresponding capacitance (106 pF) was not practical [10]. In the present work, solid state capacitors based on vertically aligned carbon nanofibers (VACNFs) that can be grown directly on the active CMOS chip and hence integrated, are demonstrated [11]. The fabrication can be carried out using a proven CMOS compatible process [12]. The specific capacitance 10–15 nF/mm2 is obtained at 1 kHz frequency.
3. Results and discussion The tilted view SEM images show that CNFs are different both in length and shape, Fig. 3a. The thin CNFs are sparse with length 4.6–5 µm, however the lengths of shorter CNFs are 1.9–2.3 µm. The ALD deposition of Al2O3 shows that dielectric is coated homogeneously and uniformly, without damaging both CNFs and dielectric, Fig. 3b, also previously shown using HRTEM [14]. The top view of the CNFs after dielectric coating and top metal coating clearly show the difference in the diameters, Fig. 3c. Fig. 4a shows the SEM image of a complete three dimensional solid state capacitor which is intended to be integrated directly on CMOS chip. Because of the CMOS temperature compatible processing, the layout of the capacitor can easily be tailored without further processing step. Moreover, the profile of the capacitor is less than 7 um making it an ultra-low profile capacitor which can easily be integrated into multi-chip packages and future interposer technology (see Table 1). The capacitances measured at 1 kHz frequency for different footprint areas capacitors are given in Fig. 4b. The equivalent parallel resistances, measured by the LCR were typically 1.9 MΩ, indicating a rather suitable conformal (I.e. void-free) deposition of the Al2O3. We therefore can see that the capacitance with CNFs is 7–9 times higher than the capacitance of a parallel plate capacitance with the same footprint area showing the real 3D capacitive effect of CNFs. A complete integrated solid state capacitor of capacitance up to 8 nF is fabricated and verified. In addition, a parasitic capacitance of very small value (185 pF) is observed by extrapolating capacitance Vs capacitor area plot, which could potentially originate from the parasitic capacitor between contact pads or bottom electrode and silicon substrate through the silicon oxide as discussed earlier. To verify that, the parasitic capacitance is from probe pads and silicon substrate is calculated. The dimensions of the single probe pad are105 µm × 105 µm and there are two dielectric layers of silicon oxide and aluminum oxide with thicknesses around 400 nm and 50 nm respectively and only silicon oxide under second pad, Fig. 2b. All three parasitic capacitors are connected in series resulting in very small capacitance values 121 fF. Furthermore the
2. Experiments A complete fabrication of on-chip integrated dielectric solid state capacitor is shown in Fig. 1. A 4-in. oxidized (500 nm SiO2) p-type silicon wafer was used as a substrate. The bottom current collector (CC) including a probing pad was defined by photolithography, followed by a sputtered metal stack of Ti/Au (20/50 nm in thicknesses) and lift-off. The metal catalyst, required to grow carbon nanofibers, was then deposited using electron beam evaporation. Vertically aligned CNFs are grown on the bottom current collector using a direct current plasma enhanced chemical vapor deposition (DC-PECVD) method at a monitored sample temperature of 390 °C and a plasma current of 300 mA, similar to [13]. A combination of acetylene and ammonia gas was used for growth of the VACNFs where the acetylene is a carbon source and ammonia is a carrier gas which also etches back the amorphous carbon. Thermal ALD technique was used for conformal coating of dielectric Al2O3 on VACNFs. The precursor trimethylealuminium (TMA) and water were used to deposit 50 nm thick layer of Al2O3 at substrate temperature of 300 °C at a pressure of 80 mtorr and a pulsing/purging
Fig. 1. (a) fabrication of bottom current collector, (b) catalyst deposition, (c) VACNFs growth, (d) conformation coating of dielectric, and (e) top current collector deposition.
76
Solid State Electronics 139 (2018) 75–79
A.M. Saleem et al.
Fig. 2. Schematic diagram of (a) measured capacitance and (b) parasitic series capacitance.
and the shorter (hS: 2 μm) CNFs. The numbers of longer (nL) and shorter (nS) CNFs are counted from the SEM picture where the shorter and longer CNFs are marked with circles and squares respectively, Fig. 3c, and total numbers of longer (NL) and shorter (NS) CNFs on area A are counted. The total CNFs surface area and empty metal area are then calculated using Eqs. (1) and (2).
difference between the measured capacitance and parallel plate capacitance for the devices without fibers (Table 2) is smaller than 5%, which is within the measurement accuracy of the data. Therefore the eventual contribution parasitic of a capacitance between the bottom electrodes of the capacitors and the Silica on substrate can be considered negligible, especially for capacitors made out of CNFs. A model is suggested to estimate the surface area of the VACNFs contributing to the capacitance, Table 2. A 420 × 630 µm2 area (A) capacitor is used for this purpose and the CNFs in contact with this area are active for capacitance. For an ordinary parallel plate capacitor without CNFs the calculated capacitance (423 pF) and measured capacitance (398 pF) have almost same values. However the total capacitance in CNFs based capacitor is the sum of capacitance from the CNFs and the empty bottom CC layer between the CNFs. The areas contributing to the total capacitance are shown by dashed lines marked with circle 1, 2 and 3 in the schematic diagram, Fig. 5. To calculate the capacitance due to bottom CC surface, the empty metal area is calculated by subtracting the CNFs area in contact with bottom CC from the capacitor footprint area. To proceed for calculation, all the CNFs are considered as uniform cylinders of same radius (r: 100 nm), and the average lengths are taken for the longer (hL: 4.8 μm)
Total surface area of the CNFs = NL × (2π rhL + π 2r ) + Ns × (2π rhS + πr 2)
(1)
Total CNFs(N) = NL + NS Since the radius of all CNFs is same
Empty metal area = A−CNFs area( N× πr 2)
(2)
The contact area of the CNFs is 35,413 µm2 and unfilled surface area of the bottom metal attained using Eq. (2) is 229,187 µm2 and finally the surface area of CNFs is 2,718,933 µm2, see Table 2. The calculated capacitances contributed by CNFs and unfilled CC area are 4.34 nF and 366 pF respectively. The calculated capacitance from the empty metal area is 12 times lower than the capacitance from the CNFs. The calculated capacitance from the unfilled area is subtracted from the
Fig. 3. SEM images of (a) VACNFs, (b) Al2O3 coated CNFs, and (c) Al2O3 and top metal coated CNFs top view.
77
Solid State Electronics 139 (2018) 75–79
A.M. Saleem et al.
Fig. 4. (a) A complete Solid state capacitor (b) capacitance measurement on CNFs and parallel capacitors.
Table 1 Average capacitance vs footprint area.
VACNFs electrode
Area (mm2)
Footprint area factor
Capacitance from CNFs (nF)
Parallel plate capacitance (nF)
0.088 0.088 0.265 0.265 0.352 0.529 0.706
1 1 3 3 4 6 8
0.990 1.180 3.450 3.160 4.250 6.540 8.0
0.133 0.132 0.398 0.397
Table 2 Values to calculate surface area of CNFs and capacitance from CNFs. X dimension of parallel plate capacitor (µm) Y dimension of parallel plate capacitor (µm) Area of the plate (µm2) Dielectric thickness (nm) Theoretical Capacitance of parallel capacitor (nF) Measured capacitance on capacitor without CNFs (nF)
420 630 264,600 50 0.423 0.398
Length of the longer CNFs (hL) (µm) Number of longer CNFs in SEM picture (nL) Length of the shorter CNFs (hS) (µm) Number of shorter CNFs in SEM picture (nS) Area of the picture (µm2) Surface area of shorter CNFs in SEM image (µm2) Surface area of longer CNFs in SEM image (µm2) Total Surface of CNFs in the SEM image (µm2) Surface of CNFs per µm2 Surface area of CNFs on 420 × 630 µm2 area(µm2) Theoretical Capacitance of CNFs (nF) Measured Capacitance from CNFs at 1 kHz (nF)
4.8 23 2 13 8.446 16.736200 70.053400 86.7896 10.2756357 2718933.207 4.34 3.45
Fig. 5. Cross section diagram of the CNFs chip.
measured capacitance (3.45 nF) to get the capacitance contributed by the CNFs (3.085 nF). The value of measured capacitance contributed by the CNFs is 71% of the calculated capacitance. The lower measured capacitance value is potentially caused by the low level conformal coating of top metal which is further confirmed by the SEM of image of the top metal electrode as shown in Fig. 6. The considerable protrusion of top metal ∼1 µm above the dielectric coated CNFs highlighted with red box confirms the partial covering of the CNFs by the metal. Nevertheless the capacitance can potentially be enhanced by conformal coating of the top CC using ALD technique and also by filling unfilled CC area with CNFs of similar dimension. Finally the capacitor is modelled using an equivalent electrical circuit and verified using keysight ADS, Fig. 7a. The impedance and phase are plotted for frequency up to 10 kHz, Fig. 7b. The model fit well with the experimental data.
Fig. 6. SEM picture of protruded top metal.
4. Conclusion Integrated on-chip solid state capacitors are fabricated based on vertically aligned carbon nanofibers and very thin layer of dielectric using CMOS temperature compatible fabrication processes. The capacitors are ultra-low profile (below 10 µm in height) and have considerable freedom of layout customization making them possible to integrate directly on active CMOS chip, or interposer. The specific capacitance 11–15 nF/mm2 is measured at 1 kHz frequency, and a full 78
Solid State Electronics 139 (2018) 75–79
A.M. Saleem et al.
Fig. 7. (a) Equivalent electrical circuit and (b) impedance and phase vs frequency model.
capacitor of capacitance value 8 nF on 0.5 mm2 is fabricated. A model is also developed to show that only ca 71% surface area of CNFs is contributing for the capacitance and by utilizing the entire surface the capacitance can further be increased.
id=97. [Accessed 21 12 2016]. [9] Pint CL, Nicholas NW, Xu S, Sun Z, Tour JM, Schmidt HK, et al. Three dimensional solid-state supercapacitors from aligned single-walled carbon nanotube array templates. Carbon 2011;49:4890–7. http://dx.doi.org/10.1016/j.carbon.2011.07.011. [10] Fiorentino G, Vollebregt S, Tichelaar F, Ishihara R, Sarro PM. Impact of the atomic layer deposition precursors diffusion on solid-state carbon nanotube based supercapacitors performances. Nanotechnology 2015;26:064002. http://dx.doi.org/10. 1088/0957-4484/26/6/064002. [11] Ghavanini FA, Poche HL, Jonas B, Saleem AM, Kabir MS, Lundgren P, et al. Compatibility assessment of CVD growth of carbon nanofibers on bulk CMOS devices. Nano Lett 2008;8(8):2437–41. http://dx.doi.org/10.1021/nl801397j. [12] Desmaris V, Saleem AM, Shafiee S, Berg J, Kabir MS, Johansson A. Carbon nanofibers (CNF) for enhanced solder-based nano-scale integration and on-chip interconnect solutions. In: 64th electronic components and technology conference (ECTC), IEEE; 2014. p. 1071–6. doi: http://dx.doi.org/10.1109/ECTC.2014. 6897421. [13] Saleem AM, Shafiee S, Krasia-Christoforou T, Savva I, Göransson G, Desmaris V, et al. Low temperature and cost-effective growth of vertically aligned carbon nanofibers using spin-coated polymer-stabilized palladium nanocatalysts. Sci Technol Adv Mater 2015;16:015007. http://dx.doi.org/10.1088/1468-6996/16/1/015007. [14] Malek GA, Brown E, Klankowski SA, Liu J, Elliot AJ, Lu R, et al. Atomic layer deposition of Al-doped ZnO/Al2O3 double layers on vertically aligned carbon nanofiber arrays. ACS Appl Mater Interfaces 2014;6:6865–71. http://dx.doi.org/10. 1021/am5006805.
Acknowledgement The author will like to thank Smoltek AB for the financial support to conduct this research. References [1] Popovich M. Effective radii of on-chip decoupling capacitors. IEEE Trans Very Large Scale Integr (VLSI) Syst 2008;16(7):894–907. http://dx.doi.org/10.1109/TVLSI. 2008.2000454. [2] Saleem MA, Göransson G, Desmaris v, Enoksson P. CMOS compatible on-chip decoupling capacitor based on vertically aligned carbon nanofibers. Solid-State Electron 2015;107:15–9. http://dx.doi.org/10.1016/j.sse.2015.01.022. [3] Saleem AM, Desmaris V, Enoksson P. Performance enhancement of carbon nanomaterials for supercapacitors. J Nanomater 2016;2016. http://dx.doi.org/10.1155/ 2016/1537269. [4] Saleem AM, Andersson R, Song B, Wong CP, Desmaris V. On-chip integrated solidstate micro-supercapacitor. In: 67th electronic components and technology conference (ECTC), IEEE; 2017. p. 173–8. doi: http://dx.doi.org/10.1109/ECTC.2017. 135. [5] Johari H, Ayazi F. High-density embedded deep trench capacitors in silicon with enhanced breakdown voltage. IEEE Trans Compon Packag Technol 2009;32(4):808–14. http://dx.doi.org/10.1109/TCAPT.2009.2024210. [6] Klootwijk JH, Jinesh KB, Dekkers W, Verhoeven JF, van den Heuvel FC, Kim H-D, et al. Ultrahigh capacitance density for multiple ALD-grown MIM capacitor stacks in 3-D silicon. IEEE Electron Device Lett 2008;29(7). http://dx.doi.org/10.1109/LED. 2008.923205. [7] Aminulloh A, Kumar V, Yang SM, Sheu G. Novel structure of deep trench capacitor with higher breakdown and higher capacitance density for low dropout voltage regulator. In: IEEE 10th international conference on power electronics and drive systems (PEDS). Kitakyushu International Conference Center; 2013. doi: http://dx. doi.org/10.1109/PEDS.2013.6527050. [8] Nodet F. http://www.ipdia.com/index.php?page=news&item_id=97, IPDiA, 19 10 2016. [Online]. Available: http://www.ipdia.com/index.php?page=news&item_
Muhammad Amin Saleem is currently working as a research engineer at Smoltek AB. He recently received Ph.D. degree from Chalmers University of Technology, Sweden and his main research interests are the different applications of carbon nanostructures. He received his M.Sc. degree in nanoscale science and technology in 2006 from Chalmers University of Technology, after which he worked as a research assistant with the Atomic Physics Department, Gothenburg University, until 2007. From 2007 to 2012, he worked as a processing engineer at Smoltek AB.
79