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Integration challenges of porous ultra low-k spin-on dielectrics
Microelectronic Engineering 64 (2002) 11–24 www.elsevier.com / locate / mee
Integration challenges of porous ultra low-k spin-on dielectrics K. Mosig a , * ,1 , T. Jacobs b ,1 , K. Brennan c ,1 , M. Rasco d ,1 , J. Wolf e ,1 , R. Augur b ,1 a
¨ , Germany Infineon Technologies, CL CTS RM DIE, D-81730 Munchen b Philips, Eindhoven, Netherlands c Texas Instruments, Dallas, TX, USA d Motorola, Austin, TX, USA e Intel Corp., Hillsboro, OR, USA
Abstract In the latest edition of the International Technology Roadmap for Semiconductors (ITRS), the predicted time for the introduction of porous ultra low-k materials with a dielectric constant of 2.2 has slipped significantly against earlier predictions. This is largely due to greater-than-expected problems with the integration of these fragile materials, which generally exhibit weak mechanical properties and low resistance against chemical attack, requiring great care during the integration process. This paper discusses some of the challenges encountered and improvements made at International Sematech and elsewhere regarding the integration of spin-on porous ultra low-k dielectrics into a copper dual damascene process. 2002 Elsevier Science B.V. All rights reserved. Keywords: Porous dielectrics; Ultra low-k materials; Spin-on dielectrics; Dual damascene
1. Introduction It is consensus in the interconnect community that the requirements for future high-end CMOS logic technologies can only be achieved by using ultra low-k materials (k | 2.3 or lower), although the k-value targets have been somewhat relaxed in the latest edition of the International Technology Roadmap for Semiconductors (ITRS) [1]. This slip in the timeline is largely caused by the problems encountered when trying to replace silicon dioxide with ultra low-k materials. While there are a great number of ultra low-k dielectrics like PE–CVD low-k materials, inorganic and organic spin-on, they all share some common properties. Firstly all are porous; there is currently no dense low-k dielectric material for semiconductor * Corresponding author. E-mail address: [email protected] (K. Mosig). 1 Assignees to International Sematech, 2706 Montopolis Drive, Austin, TX 78741, USA. 0167-9317 / 02 / $ – see front matter PII: S0167-9317( 02 )00767-0
2002 Elsevier Science B.V. All rights reserved.
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K. Mosig et al. / Microelectronic Engineering 64 (2002) 11–24
applications available with a dielectric constant below 2.5. This already brings up challenges on how to form a dense copper barrier e.g. in trenches if a pore is cross-sectioned by the etch process. Also residual gases from etch and ash processes can be trapped in the material, causing interaction with later processing steps, one such case leads to DUV resist poisoning. Secondly they all are mechanically weak compared to silicon dioxide, and generally exhibit poorer adhesion to under layers and cap materials. This means that they are especially prone to damage during processes inducing stress into the dual damascene structure like CMP, assembly, thermal processes and electromigration reliability testing. Thirdly they are rather sensitive to all kinds of wet and dry clean chemicals. This requires great care in designing appropriate integration schemes to avoid all unnecessary exposure of the low-k material to the environment. In particularly, most ultra low-k materials are also attacked by CMP or post-CMP clean chemicals, so that they have to be securely capped with dense dielectric materials, introducing additional layers and interfaces into the integration scheme. Despite all of these challenges, some progress has been reported recently with respect to the integration of these materials into copper dual damascene structures. This paper will concentrate on the integration behaviour of inorganic spin-on porous ultra low-k materials with a dielectric constant of 2.2–2.3.
2. Experimental
2.1. Overview of possible failure modes Fig. 1 shows a schematic of single and dual damascene stacks as used in this investigation indicating the main challenges for the integration. For single damascene structures like that depicted
Fig. 1. (a) Schematic single damascene structure; (b) schematic dual damascene structure. Explanations of letters see text.
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in Fig. 1a, these are etch and ash damage (A), possible undercuts under the cap (B), cap retention during CMP (C), adhesion to etch stop and cap layers (D) and the question of barrier integrity over a porous material (E). For dual damascene shown in Fig. 1b, there is additionally the possibility of delamination below and above the M2 trench etch stop layer (F), damage from pre-barrier deposition sputter etching (G), hardmask rounding during the via bottom open etch (H), and damage from wet and dry cleans post via bottom open etch (J). These challenges can be roughly divided into the mechanical part—like material strength, adhesion of the low-k material to different other layers and CMP compatibility—and chemical issues like compatibilities with etches, dry and wet cleans. In addition, there are further challenges waiting in reliability testing and packaging even if the copper / low-k dual damascene structure shows good electrical parameters in electrical tests at the end of the wafer fabrication process.
2.2. Mechanical strength, adhesion and CMP behaviour The first set of challenges for integration are mechanical in nature. Table 1 shows the comparison of some key parameters for silicon dioxide and JSR LKD 5109, a typical example of a methylsilsesquioxane (MSQ) based porous spin-on ultra low-k material. Porous ultra low-k materials have a much lower modulus and hardness than SiO 2 . Usually the modulus is only | 4 GPa compared to 55 . . . 70 GPa, depending on the deposition conditions, for plasma enhanced CVD (PE–CVD) deposited SiO 2 . Lin [2] showed a relationship between the modulus of a low-k material and its behaviour during blanket wafer and patterned wafer CMP. He described the CMP behaviour of some 20 low-k materials and depending on the modulus, divides them into several classes. Fig. 2 shows this relationship. The CMP behaviour can be improved by the introduction of so-called dummy fill metal patterns. Fig. 3 shows a schematic drawing and a picture of a simple Boolean dummy fill structure used by International Sematech. The use of this dummy fill structure at least enables single damascene CMP of very soft ultra low-k materials using the harder copper as an anchor to eliminate excessive shear stresses in the low-k material itself. On the other hand this dummy fill introduces unconnected metal parts in the stack, which have an undefined electrical potential. This might have detrimental effects on the high-frequency behaviour. For a distance of 6 mm to the nearest signal line, as chosen for the construction of the International Sematech dummy fill, however, no negative effect could be detected at high frequency transmission lines up to 40 GHz. A welcome side effect of the dummy fill is the increased heat conductance, lowering Joule heating in Cu / low-k samples (see below, Reliability). Table 1 Selected properties of JSR LKD 5109 and plasma-enhanced CVD (PE–CVD) deposited silicon dioxide
3
Density (g / cm ) Dielectric constant Modulus (GPa) Hardness (GPa) n (633 nm) CTE (ppm / K) Porosity (from SANS) Avg. pore size (nm) Thermal conductivity (W/ m K)
JSR LKD 5109
PE–CVD SiO 2
1.03 2.3 4 0.5 1.255 14 | 50% , 2.0 0.26
2.2 4.1 55–70 3.5 1.45 0.6 – – 1.4
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Fig. 2. Relationship between modulus of low-k material and CMP performance after [2].
In the case of dual damascene integration, the introduction of via and trench etch stop layers produces new interfaces between PE–CVD materials and low-k, which usually do not have high adhesion. Fig. 4 shows a typical picture of a dual damascene delamination occurring at the via trench
Fig. 3. Boolean dummy fill structure (a) schematic; (b) picture showing wide M1 signal line and dummy fill in field region.
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Fig. 4. Picture of delamination occurring during dual damascene CMP.
etch stop layer during CMP. This behaviour can be improved upon by: (a) careful selection of cap and etch-stop materials and adhesion improvement like plasma-pretreatment or adhesion promoters; or (b) reducing the mechanical stress during CMP. The application of dummy fill structures like shown above for single damascene integration into a dual damascene scheme is very difficult, especially in the via level. In order to avoid unwanted metallic shorts, this would involve a complicated construction rule depending on other layers and not a simple Boolean rule like in the single damascene case. The structures at International Sematech therefore only contain dummy fill patterns in the metal levels, and not in the via level. As shown recently by several groups, including International Sematech, successful integration of porous ultra low-k requires a combination of the above mentioned measures, adhesion improvement, the introduction of dummy fills to improve the overall Cu / low-k system strength, and low down force CMP processes [3–6]. There are new approaches to plating and planarisation like electro-chemical polishing [7,8], that could allow the formation of copper dual damascene structures with virtually no mechanical stress and could therefore be enablers for the manufacturing of dual damascene structures for even weaker low-k materials which were not able to withstand CMP in Fig. 2, but have dielectric constants k , 2.2. A factor that also induces stress into the low-k material and that cannot be easily avoided is any thermal cycling which always occurs in a multilevel build when new layers are deposited. Most PE–CVD films are deposited and low-k films are cured around 400 8C, up to 430 8C. An integration scheme with seven metal layers means at least 40 temperature cycles between room temperature and 400 8C. Early low-k materials could not pass a simple test in which 10 low-k layers with PE–CVD cap layers between were successively deposited to simulate a multi-metal-level build. More recently, as shown in Fig. 5, a successful build of a simulated seven-metal layer stack was accomplished, using 13 layers JSR LKD 5109 of 400 nm thickness with PE–CVD silicon carbide layers in between. The first layer was patterned using an M1 pattern, the top layer was patterned using an M2 pattern, and the whole stack was polished with a low down force CMP process using conventional consumables on a rotary tool. The formation of a dense metal barrier on the porous low-k material can be quite challenging, too.
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Fig. 5. Stack with 13 layers of JSR LKD 5109 and PE–CVD silicon carbide layers in between. The bottom layer is patterned with M1, the top layer is patterned with M2 and polished using a low down force CMP process.
Due to the porosity of the material it is inevitable that some pores are opened when etching a pattern into the low-k material. Wetzel and co-workers [9] have produced samples of single damascene combs using low-k materials with different pore sizes. They show a clear correlation between yield and pore size. For their integration scheme with 25 nm PVD Ta barrier metal they conclude that there is a threshold at approximately 5 nm in pore size, for larger pores the comb yield drops significantly. Also positron annihilation studies showed escaping positronium (indicating pinholes in the PVD metal barrier) for low-k materials with large pores for thin barriers. Mosig et al. [5] showed that at least in the case of JSR LKD 5109 with a very small pore size, CVD TiN(Si) can form a very thin conformal and continuous barrier.
2.3. Etch, ash and clean chemicals compatibility In addition to the mechanical there are chemical effects to be considered. Etching the porous low-k material itself is usually not difficult. MSQ based materials like JSR LKD 5109 can be etched using conventional silicon dioxide etch chemistries. Due to the porosity the etch rate is higher than for the corresponding bulk material, also the etch front is rougher than for dense materials, and micro-trenching can be very pronounced. Therefore, it will be very difficult to use a dual damascene scheme without a trench etch stop layer. The ash process, however, which is used to remove the remaining resist and sidewall polymers generated during the etch, is a very critical process step. Some of the chemistries can modify the chemical matrix of the low-k material leading to hydrophilic behaviour or an increase in dielectric constant. For JSR LKD, reducing ash chemistry was found to give lower capacitance values compared to oxygen based ashes, which sometimes led to k-values close to that of oxide [3]. The sensitivity to
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ash processes means that for example litho rework with open low-k material becomes critical. From this point of view a via first dual damascene integration scheme is undesirable, because it relies on the ability to rework the metal layer over opened vias. A dual top hard mask trench first scheme like the one used at International Sematech alleviates some of these problems, but creates new ones like a very complicated etch process. Wet cleans also tend to influence the porous low-k materials much more than the respective bulk material due to the larger surface area. Wet clean chemicals from different suppliers were benchmarked and tested for their influence on the etched low-k material using SEM inspection and FTIR spectroscopy. Included were both solvent- and water-based, fluorine- and non-fluorine-containing chemistries. Fig. 6 shows the effect of three of the chemicals on 0.25 mm wide trenches in JSR LKD. It was found that most chemicals currently available for the cleaning of Cu and oxide are not suitable for porous low-k materials. Only very few of the tested chemicals were compatible with JSR LKD. Generally diluted aqueous chemicals gave the best results [3]. Porous low-k materials are mostly open pored so that etch gases and cleans chemicals can penetrate into and through the bulk material. This means that N-containing chemistries have to be avoided whenever the low-k material is exposed, especially in a via first integration scheme in order to avoid resist poisoning. An example of resist poisoning is shown in Fig. 7. The amines outgassing from the low-k material are inhibiting the development of the chemically amplified deep-UV resist in the exposed area leading to the mushroom-like shape in Fig. 7a. If etched this undeveloped resist masks the underlying layer during etch, leading to a ‘volcano’ shown in Fig. 7b.
Fig. 6. effect of three different wet clean chemicals on JSR LKD.
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Fig. 7. (a) Resist poisoning caused by outgassing amines; (b) volcano caused by the blocking of the etch by a resist plug like the one in (a).
2.4. Chemical–mechanical effects Most low-k materials are also not compatible with either the CMP process itself, leading to large erosion of the low-k material when polishing through the cap material (Fig. 8), or the chemicals used during the post-CMP clean step in a scrubber. Therefore, polishing through the CMP cap has to be avoided, which implies that the erosion at the CMP process in the worst case structure has to determine the minimum thickness of the low-k cap. A combination of fluorine residues from etch process, sidewall roughness after etch, barrier used, plating chemistry and thermal budget induces another interesting chemical–mechanical phenomenon i.e., porous low-k voiding [9,10], that can lead to large holes being generated in the low-k material after Cu anneal. A typical example is shown in Fig. 9.
2.5. Robust integration vs. low effective k value Fig. 10 shows the capacitance measured at a JSR LKD 5109 single damascene structure with 0.25 mm trenches and 0.30 mm spacing. As a reference the capacitance of one Cu / oxide lot is also shown, which has the same structures as the low-k samples, but uses silane based PE–CVD silicon dioxide as dielectric. The capacitance for JSR LKD is significantly smaller than for the Cu / oxide sample, the
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Fig. 8. Single damascene structure where the CMP process has by mistake removed all cap material showing severe erosion of the low-k material.
capacitance value of 5.5 pF in this specific structure is consistent with a k-value of 2.35 for the JSR LKD assuming dielectric constants of 4 for the oxide and carbide cap and 7 for the nitride. The overall effective k-value is still k 5 2.7. Therefore, one challenge for future work is to minimise the thickness and k-value of all additional layers like CMP cap and etch stop layer in order to take full advantage of the low dielectric constant
Fig. 9. Typical example of low-k voiding (after [10]).
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Fig. 10. Comparison of capacitance measurement of single damascene combs for Cu / JSR LKD 5109 and Cu / oxide samples, the insert shows a 0.18-mm comb with 0.40 mm pitch.
of porous low-k materials. One possibility besides changing to CMP-free approaches as described in Refs. [7,8], is to exchange the capping material for a dense oxide-like PE–CVD low-k material like those available from most CVD tool vendors. But there are limits to the effort of minimising the thickness of all non-low-k layers. Fig. 11 shows the damage to a porous ultra low-k material by the argon sputter etch prior to barrier / seed deposition. It clearly shows that the argon sputter leads to a large roughness of the low-k surface. Therefore, the—in our case silicon carbide—trench etch stop layer not only has to act as an effective etch stop layer for M2, it also has to be thick enough so that it is not consumed during the etch of the via bottom etch stop layer. This increase in the SiC layer thickness is countering the effort to further decrease the overall effective dielectric constant, so in the future new integration schemes have to be explored. One possibility is the elimination of the argon sputter clean by using a plasma clean chamber prior to barrier deposition, etching chemically rather than physically the copper oxide layer at the bottom of the via. This could ultimately enable the use of very thin etch stop layers that take full advantage of the high achievable etch selectivity to low-k materials.
2.6. Reliability Very little is known about the implications of the change from a dense oxide dielectric to a porous material in terms of electromigration and reliability. It is generally believed that this change will deteriorate the reliability significantly, lowering the dielectric breakdown field, BTS lifetime, increasing the Joule heating and leading to decreased EM lifetime as the relatively weak low-k material is not able to constrain the metallisation in the same way the rigid silicon dioxide does. First
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Fig. 11. (a) Etched dual damascene pattern before barrier and seed deposition; (b) damage caused by argon sputter etch prior to barrier / seed deposition; (c) sample with increased etch stop layer thickness showing no damage from argon sputter etch.
Joule heating, BTS and electromigration results for a porous ultra low-k material have been presented by Mosig and Blaschke [11]. As an example, the results of Joule heating are depicted in Fig. 12. As expected, Cu / porous spin-on ultra low-k material samples exhibit lower breakdown strength, higher Joule heating and lower EM lifetimes than usually found for Cu / SiO2 interconnects. For the JSR LKD material used in this investigation, the difference observed is approximately a factor of 2.5 for Joule heating and median EM lifetime, and a factor of four for the dielectric breakdown field.
2.7. Packaging Packaging is the ultimate test for the mechanical strength of Cu / porous low-k interconnects. Even samples with no problems in the semiconductor manufacturing process can fail, especially at Au ball or Al wedge bond, if no appropriate precautions are taken. Fig. 13a shows the results of an early bond attempt, failing at the M2 trench etch stop layer, which is similar to the failure mechanism shown in Fig. 4. With improving low-k materials and integration approaches, however, and using optimised bond parameters, it is possible to get good assembly yield with both wire bond techniques [12]. Fig. 13b shows successful Au wire bonds to a JSR LKD 5109 dual damascene build.
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Fig. 12. Comparison of Joule heating for Cu / SiO2 and Cu / JSR LKD samples with and without dummy fill structures. The arrows indicate typical current densities for electromigration testing and use conditions.
3. Summary and outlook There has been significant progress in the last years regarding the integration of porous ultra low-k materials into a copper dual damascene scheme—the materials have become better, a lot more ultra
Fig. 13. Au wire bonds on JSR LKD, (a) first attempt, fail at the M2 trench etch stop layer; (b) later result with improved stack and optimised bond parameters.
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low-k compatible unit processes have been developed and the integration approaches are better characterised. Nonetheless, the vastly different properties of spin-on porous ultra low-k materials compared to silicon dioxide lead to unique challenges during the semiconductor manufacturing process. Basically, every single unit process has to be optimised to ensure that the low-k material is not damaged. Due to the mechanical weakness of the ultra low-k materials, CMP becomes a very critical process, and alternatives to conventional CMP would be very advantageous for the integration of ultra low-k materials. Due to their open porosity and very large surface area, every production step that exposes the low-k material to e.g. a plasma, or a wet chemical treatment, has to be critically examined. The best integration scheme in this respect is the one avoiding contact of the low-k material to such processes. Our experiments show further that even when the parametric test data is good, there may be problems further down the road. Packaging and assembly techniques have to be adapted to the new materials, or the integration approaches have to be modified until conventional assembly techniques work. But even when wafer fabrication and assembly work without problems, there still is the open question of how good especially the electromigration reliability of Cu / low-k will be. Due to the much lower modulus, the back driving force during electromigration will definitely be smaller than in the case of Cu / oxide, leading to a shorter average lifetime in the same structures. More work is needed to evaluate the potential for improvement by changing e.g. integration approaches. Furthermore, it has to be investigated whether the extrapolations conventionally used to estimate failure rates at real-life use conditions from the accelerated test conditions are a good enough approximation in the case of Cu / low-k materials, and if the observed reliability results would be sufficient for future technology generations.
Acknowledgements The authors wish to thank International Sematech’s Advanced Tool Development Facility (ATDF), the staff of the Interconnect Division, the electrical test and physical analysis labs for their help in processing the samples used in this investigation. We are indebted to a large number of companies than cannot be listed here individually; especially low-k dielectrics vendors and chemical suppliers for supplying pre-production versions of their resins and other chemicals for the characterisation and integration work, and tool manufacturers for supporting the development of new improved unit processes for the new materials.
References [1] The International Technology Roadmap for Semiconductors, Semiconductor Industry Association, San Jose, CA, 2001. [2] S. Lin, C. Jin, L. Lui, M.H. Tsai, M. Daniels, A. Gonzalez, J.T. Wetzel, K.A. Monnig, P.A. Winebarger, S. Jang, D. Yu, M.S. Liang, Low-k dielectrics characterisation for damascene integration, in: Proc. IITC 2001, IEEE, Piscataway, 2001, pp. 146–148.
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[3] K. Mosig, T. Jacobs, P. Kofron, M. Daniels, K. Brennan, A. Gonzales, R. Augur, J. Wetzel, R. Havermann, A. Shiota, Single and dual damascene integration of a spin-on porous ultra low-k material, in: Proc. IITC 2001, IEEE, Piscataway, 2001, pp. 292–294. [4] M. Hiroi, M. Tada, H. Ohtake, S. Saito, T. Onodera, N. Furutake, Y. Harada, Y. Hayashi, Dual hard mask process for low-k porous organosilica dielectric in copper dual damascene interconnect fabrication, in: Proc. IITC 2001, IEEE, Piscataway, 2001, pp. 295–297. [5] K. Mosig, H. Cox, E. Klawuhn, T. Suwwan de Felipe, A. Shiota, Integration of porous ultra low-k dielectric with CVD barriers, in: Proc. IEDM 2001, IEEE, Piscataway, 2001, pp. 88–91. [6] J.C. Lin, H.S. Lee, S. Satyanarayana, H. Martinez, T. Jacobs, K. Brennan, A. Gonzalez, R. Augur, S.L. Shue, C.H. Yu, M.S. Liang, Via first dual damascene integration of nanoporous ultra low-k material, in: Proc. IITC 2002, IEEE, Piscataway, 2002, pp. 48–50. [7] M.H. Tsai, S.W. Chou, C.L. Chang, C.H. Hsieha, M.W. Lin, C.M. Wu, W.S. Shue, D.C. Yu, M.S. Liang, CMP-free and CMP-less approaches for mulitlevel Cu / low-k BEOL integration, in: Proc. IEDM 2001, IEEE, Piscataway, 2001, pp. 80–83. [8] S. Sato, Z. Yasuda, M. Ishihara, N. Komai, H. Ohtorii, A. Yoshio, Y. Segawa, H. Horikoshi, Y. Ohoka, K. Tai, S. Takahashi, T. Nogami, Newly developed electro-chemical polishing process of copper as replacement of cmp suitable for damascene copper inlaid in fragile low-k dielectrics, in: Proc. IEDM 2001, IEEE, Piscataway, 2001, pp. 84–87. [9] J. Wetzel, S.H. Lin, W. Mickler, J. Lee, B. Ahlburn, C. Jin, R.J. Fox III, M.H. Tsai, W. Mlynko, K.A. Monnig, P.M. Winebarger, Evaluation of material property requirements and performance of ultra-low dielectric constant insulators for inlaid copper metallization, in: Proc. IEDM 2001, IEEE, Piscataway, 2001, pp. 73–75. [10] T. Jacobs, K. Brennan, R. Carpio, K. Mosig, J.C. Lin, H. Cox, W. Mlynko, J. Fourcher, J. Bennett, J. Wolf, R. Augur, P. Gillespie, Voiding in ultra porous low-k materials, Proposed mechanism, detection and possible solutions, in: Proc. IITC 2002, IEEE, Piscataway, 2002, pp. 113–115. [11] K. Mosig, V. Blaschke, Electromigration reliability of Cu / spin-on porous ultra low-k interconnects, in: A.J. McKerrow, Y. Sacham-Diamand, S. Zaima, T. Ohba (Eds.), Proc. AMC 2001, MRS conf. proc. series, in press. [12] M. Rasco, K. Mosig, J. Ling, P. Elenius, R. Augur, Packaging assessment of porous ultra low-k materials, International Sematech internal publication, submitted to IITC 2002.
Integration challenges of porous ultra low-k spin-on dielectrics K. Mosig a , * ,1 , T. Jacobs b ,1 , K. Brennan c ,1 , M. Rasco d ,1 , J. Wolf e ,1 , R. Augur b ,1 a
¨ , Germany Infineon Technologies, CL CTS RM DIE, D-81730 Munchen b Philips, Eindhoven, Netherlands c Texas Instruments, Dallas, TX, USA d Motorola, Austin, TX, USA e Intel Corp., Hillsboro, OR, USA
Abstract In the latest edition of the International Technology Roadmap for Semiconductors (ITRS), the predicted time for the introduction of porous ultra low-k materials with a dielectric constant of 2.2 has slipped significantly against earlier predictions. This is largely due to greater-than-expected problems with the integration of these fragile materials, which generally exhibit weak mechanical properties and low resistance against chemical attack, requiring great care during the integration process. This paper discusses some of the challenges encountered and improvements made at International Sematech and elsewhere regarding the integration of spin-on porous ultra low-k dielectrics into a copper dual damascene process. 2002 Elsevier Science B.V. All rights reserved. Keywords: Porous dielectrics; Ultra low-k materials; Spin-on dielectrics; Dual damascene
1. Introduction It is consensus in the interconnect community that the requirements for future high-end CMOS logic technologies can only be achieved by using ultra low-k materials (k | 2.3 or lower), although the k-value targets have been somewhat relaxed in the latest edition of the International Technology Roadmap for Semiconductors (ITRS) [1]. This slip in the timeline is largely caused by the problems encountered when trying to replace silicon dioxide with ultra low-k materials. While there are a great number of ultra low-k dielectrics like PE–CVD low-k materials, inorganic and organic spin-on, they all share some common properties. Firstly all are porous; there is currently no dense low-k dielectric material for semiconductor * Corresponding author. E-mail address: [email protected] (K. Mosig). 1 Assignees to International Sematech, 2706 Montopolis Drive, Austin, TX 78741, USA. 0167-9317 / 02 / $ – see front matter PII: S0167-9317( 02 )00767-0
2002 Elsevier Science B.V. All rights reserved.
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applications available with a dielectric constant below 2.5. This already brings up challenges on how to form a dense copper barrier e.g. in trenches if a pore is cross-sectioned by the etch process. Also residual gases from etch and ash processes can be trapped in the material, causing interaction with later processing steps, one such case leads to DUV resist poisoning. Secondly they all are mechanically weak compared to silicon dioxide, and generally exhibit poorer adhesion to under layers and cap materials. This means that they are especially prone to damage during processes inducing stress into the dual damascene structure like CMP, assembly, thermal processes and electromigration reliability testing. Thirdly they are rather sensitive to all kinds of wet and dry clean chemicals. This requires great care in designing appropriate integration schemes to avoid all unnecessary exposure of the low-k material to the environment. In particularly, most ultra low-k materials are also attacked by CMP or post-CMP clean chemicals, so that they have to be securely capped with dense dielectric materials, introducing additional layers and interfaces into the integration scheme. Despite all of these challenges, some progress has been reported recently with respect to the integration of these materials into copper dual damascene structures. This paper will concentrate on the integration behaviour of inorganic spin-on porous ultra low-k materials with a dielectric constant of 2.2–2.3.
2. Experimental
2.1. Overview of possible failure modes Fig. 1 shows a schematic of single and dual damascene stacks as used in this investigation indicating the main challenges for the integration. For single damascene structures like that depicted
Fig. 1. (a) Schematic single damascene structure; (b) schematic dual damascene structure. Explanations of letters see text.
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in Fig. 1a, these are etch and ash damage (A), possible undercuts under the cap (B), cap retention during CMP (C), adhesion to etch stop and cap layers (D) and the question of barrier integrity over a porous material (E). For dual damascene shown in Fig. 1b, there is additionally the possibility of delamination below and above the M2 trench etch stop layer (F), damage from pre-barrier deposition sputter etching (G), hardmask rounding during the via bottom open etch (H), and damage from wet and dry cleans post via bottom open etch (J). These challenges can be roughly divided into the mechanical part—like material strength, adhesion of the low-k material to different other layers and CMP compatibility—and chemical issues like compatibilities with etches, dry and wet cleans. In addition, there are further challenges waiting in reliability testing and packaging even if the copper / low-k dual damascene structure shows good electrical parameters in electrical tests at the end of the wafer fabrication process.
2.2. Mechanical strength, adhesion and CMP behaviour The first set of challenges for integration are mechanical in nature. Table 1 shows the comparison of some key parameters for silicon dioxide and JSR LKD 5109, a typical example of a methylsilsesquioxane (MSQ) based porous spin-on ultra low-k material. Porous ultra low-k materials have a much lower modulus and hardness than SiO 2 . Usually the modulus is only | 4 GPa compared to 55 . . . 70 GPa, depending on the deposition conditions, for plasma enhanced CVD (PE–CVD) deposited SiO 2 . Lin [2] showed a relationship between the modulus of a low-k material and its behaviour during blanket wafer and patterned wafer CMP. He described the CMP behaviour of some 20 low-k materials and depending on the modulus, divides them into several classes. Fig. 2 shows this relationship. The CMP behaviour can be improved by the introduction of so-called dummy fill metal patterns. Fig. 3 shows a schematic drawing and a picture of a simple Boolean dummy fill structure used by International Sematech. The use of this dummy fill structure at least enables single damascene CMP of very soft ultra low-k materials using the harder copper as an anchor to eliminate excessive shear stresses in the low-k material itself. On the other hand this dummy fill introduces unconnected metal parts in the stack, which have an undefined electrical potential. This might have detrimental effects on the high-frequency behaviour. For a distance of 6 mm to the nearest signal line, as chosen for the construction of the International Sematech dummy fill, however, no negative effect could be detected at high frequency transmission lines up to 40 GHz. A welcome side effect of the dummy fill is the increased heat conductance, lowering Joule heating in Cu / low-k samples (see below, Reliability). Table 1 Selected properties of JSR LKD 5109 and plasma-enhanced CVD (PE–CVD) deposited silicon dioxide
3
Density (g / cm ) Dielectric constant Modulus (GPa) Hardness (GPa) n (633 nm) CTE (ppm / K) Porosity (from SANS) Avg. pore size (nm) Thermal conductivity (W/ m K)
JSR LKD 5109
PE–CVD SiO 2
1.03 2.3 4 0.5 1.255 14 | 50% , 2.0 0.26
2.2 4.1 55–70 3.5 1.45 0.6 – – 1.4
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Fig. 2. Relationship between modulus of low-k material and CMP performance after [2].
In the case of dual damascene integration, the introduction of via and trench etch stop layers produces new interfaces between PE–CVD materials and low-k, which usually do not have high adhesion. Fig. 4 shows a typical picture of a dual damascene delamination occurring at the via trench
Fig. 3. Boolean dummy fill structure (a) schematic; (b) picture showing wide M1 signal line and dummy fill in field region.
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Fig. 4. Picture of delamination occurring during dual damascene CMP.
etch stop layer during CMP. This behaviour can be improved upon by: (a) careful selection of cap and etch-stop materials and adhesion improvement like plasma-pretreatment or adhesion promoters; or (b) reducing the mechanical stress during CMP. The application of dummy fill structures like shown above for single damascene integration into a dual damascene scheme is very difficult, especially in the via level. In order to avoid unwanted metallic shorts, this would involve a complicated construction rule depending on other layers and not a simple Boolean rule like in the single damascene case. The structures at International Sematech therefore only contain dummy fill patterns in the metal levels, and not in the via level. As shown recently by several groups, including International Sematech, successful integration of porous ultra low-k requires a combination of the above mentioned measures, adhesion improvement, the introduction of dummy fills to improve the overall Cu / low-k system strength, and low down force CMP processes [3–6]. There are new approaches to plating and planarisation like electro-chemical polishing [7,8], that could allow the formation of copper dual damascene structures with virtually no mechanical stress and could therefore be enablers for the manufacturing of dual damascene structures for even weaker low-k materials which were not able to withstand CMP in Fig. 2, but have dielectric constants k , 2.2. A factor that also induces stress into the low-k material and that cannot be easily avoided is any thermal cycling which always occurs in a multilevel build when new layers are deposited. Most PE–CVD films are deposited and low-k films are cured around 400 8C, up to 430 8C. An integration scheme with seven metal layers means at least 40 temperature cycles between room temperature and 400 8C. Early low-k materials could not pass a simple test in which 10 low-k layers with PE–CVD cap layers between were successively deposited to simulate a multi-metal-level build. More recently, as shown in Fig. 5, a successful build of a simulated seven-metal layer stack was accomplished, using 13 layers JSR LKD 5109 of 400 nm thickness with PE–CVD silicon carbide layers in between. The first layer was patterned using an M1 pattern, the top layer was patterned using an M2 pattern, and the whole stack was polished with a low down force CMP process using conventional consumables on a rotary tool. The formation of a dense metal barrier on the porous low-k material can be quite challenging, too.
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Fig. 5. Stack with 13 layers of JSR LKD 5109 and PE–CVD silicon carbide layers in between. The bottom layer is patterned with M1, the top layer is patterned with M2 and polished using a low down force CMP process.
Due to the porosity of the material it is inevitable that some pores are opened when etching a pattern into the low-k material. Wetzel and co-workers [9] have produced samples of single damascene combs using low-k materials with different pore sizes. They show a clear correlation between yield and pore size. For their integration scheme with 25 nm PVD Ta barrier metal they conclude that there is a threshold at approximately 5 nm in pore size, for larger pores the comb yield drops significantly. Also positron annihilation studies showed escaping positronium (indicating pinholes in the PVD metal barrier) for low-k materials with large pores for thin barriers. Mosig et al. [5] showed that at least in the case of JSR LKD 5109 with a very small pore size, CVD TiN(Si) can form a very thin conformal and continuous barrier.
2.3. Etch, ash and clean chemicals compatibility In addition to the mechanical there are chemical effects to be considered. Etching the porous low-k material itself is usually not difficult. MSQ based materials like JSR LKD 5109 can be etched using conventional silicon dioxide etch chemistries. Due to the porosity the etch rate is higher than for the corresponding bulk material, also the etch front is rougher than for dense materials, and micro-trenching can be very pronounced. Therefore, it will be very difficult to use a dual damascene scheme without a trench etch stop layer. The ash process, however, which is used to remove the remaining resist and sidewall polymers generated during the etch, is a very critical process step. Some of the chemistries can modify the chemical matrix of the low-k material leading to hydrophilic behaviour or an increase in dielectric constant. For JSR LKD, reducing ash chemistry was found to give lower capacitance values compared to oxygen based ashes, which sometimes led to k-values close to that of oxide [3]. The sensitivity to
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ash processes means that for example litho rework with open low-k material becomes critical. From this point of view a via first dual damascene integration scheme is undesirable, because it relies on the ability to rework the metal layer over opened vias. A dual top hard mask trench first scheme like the one used at International Sematech alleviates some of these problems, but creates new ones like a very complicated etch process. Wet cleans also tend to influence the porous low-k materials much more than the respective bulk material due to the larger surface area. Wet clean chemicals from different suppliers were benchmarked and tested for their influence on the etched low-k material using SEM inspection and FTIR spectroscopy. Included were both solvent- and water-based, fluorine- and non-fluorine-containing chemistries. Fig. 6 shows the effect of three of the chemicals on 0.25 mm wide trenches in JSR LKD. It was found that most chemicals currently available for the cleaning of Cu and oxide are not suitable for porous low-k materials. Only very few of the tested chemicals were compatible with JSR LKD. Generally diluted aqueous chemicals gave the best results [3]. Porous low-k materials are mostly open pored so that etch gases and cleans chemicals can penetrate into and through the bulk material. This means that N-containing chemistries have to be avoided whenever the low-k material is exposed, especially in a via first integration scheme in order to avoid resist poisoning. An example of resist poisoning is shown in Fig. 7. The amines outgassing from the low-k material are inhibiting the development of the chemically amplified deep-UV resist in the exposed area leading to the mushroom-like shape in Fig. 7a. If etched this undeveloped resist masks the underlying layer during etch, leading to a ‘volcano’ shown in Fig. 7b.
Fig. 6. effect of three different wet clean chemicals on JSR LKD.
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Fig. 7. (a) Resist poisoning caused by outgassing amines; (b) volcano caused by the blocking of the etch by a resist plug like the one in (a).
2.4. Chemical–mechanical effects Most low-k materials are also not compatible with either the CMP process itself, leading to large erosion of the low-k material when polishing through the cap material (Fig. 8), or the chemicals used during the post-CMP clean step in a scrubber. Therefore, polishing through the CMP cap has to be avoided, which implies that the erosion at the CMP process in the worst case structure has to determine the minimum thickness of the low-k cap. A combination of fluorine residues from etch process, sidewall roughness after etch, barrier used, plating chemistry and thermal budget induces another interesting chemical–mechanical phenomenon i.e., porous low-k voiding [9,10], that can lead to large holes being generated in the low-k material after Cu anneal. A typical example is shown in Fig. 9.
2.5. Robust integration vs. low effective k value Fig. 10 shows the capacitance measured at a JSR LKD 5109 single damascene structure with 0.25 mm trenches and 0.30 mm spacing. As a reference the capacitance of one Cu / oxide lot is also shown, which has the same structures as the low-k samples, but uses silane based PE–CVD silicon dioxide as dielectric. The capacitance for JSR LKD is significantly smaller than for the Cu / oxide sample, the
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Fig. 8. Single damascene structure where the CMP process has by mistake removed all cap material showing severe erosion of the low-k material.
capacitance value of 5.5 pF in this specific structure is consistent with a k-value of 2.35 for the JSR LKD assuming dielectric constants of 4 for the oxide and carbide cap and 7 for the nitride. The overall effective k-value is still k 5 2.7. Therefore, one challenge for future work is to minimise the thickness and k-value of all additional layers like CMP cap and etch stop layer in order to take full advantage of the low dielectric constant
Fig. 9. Typical example of low-k voiding (after [10]).
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Fig. 10. Comparison of capacitance measurement of single damascene combs for Cu / JSR LKD 5109 and Cu / oxide samples, the insert shows a 0.18-mm comb with 0.40 mm pitch.
of porous low-k materials. One possibility besides changing to CMP-free approaches as described in Refs. [7,8], is to exchange the capping material for a dense oxide-like PE–CVD low-k material like those available from most CVD tool vendors. But there are limits to the effort of minimising the thickness of all non-low-k layers. Fig. 11 shows the damage to a porous ultra low-k material by the argon sputter etch prior to barrier / seed deposition. It clearly shows that the argon sputter leads to a large roughness of the low-k surface. Therefore, the—in our case silicon carbide—trench etch stop layer not only has to act as an effective etch stop layer for M2, it also has to be thick enough so that it is not consumed during the etch of the via bottom etch stop layer. This increase in the SiC layer thickness is countering the effort to further decrease the overall effective dielectric constant, so in the future new integration schemes have to be explored. One possibility is the elimination of the argon sputter clean by using a plasma clean chamber prior to barrier deposition, etching chemically rather than physically the copper oxide layer at the bottom of the via. This could ultimately enable the use of very thin etch stop layers that take full advantage of the high achievable etch selectivity to low-k materials.
2.6. Reliability Very little is known about the implications of the change from a dense oxide dielectric to a porous material in terms of electromigration and reliability. It is generally believed that this change will deteriorate the reliability significantly, lowering the dielectric breakdown field, BTS lifetime, increasing the Joule heating and leading to decreased EM lifetime as the relatively weak low-k material is not able to constrain the metallisation in the same way the rigid silicon dioxide does. First
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Fig. 11. (a) Etched dual damascene pattern before barrier and seed deposition; (b) damage caused by argon sputter etch prior to barrier / seed deposition; (c) sample with increased etch stop layer thickness showing no damage from argon sputter etch.
Joule heating, BTS and electromigration results for a porous ultra low-k material have been presented by Mosig and Blaschke [11]. As an example, the results of Joule heating are depicted in Fig. 12. As expected, Cu / porous spin-on ultra low-k material samples exhibit lower breakdown strength, higher Joule heating and lower EM lifetimes than usually found for Cu / SiO2 interconnects. For the JSR LKD material used in this investigation, the difference observed is approximately a factor of 2.5 for Joule heating and median EM lifetime, and a factor of four for the dielectric breakdown field.
2.7. Packaging Packaging is the ultimate test for the mechanical strength of Cu / porous low-k interconnects. Even samples with no problems in the semiconductor manufacturing process can fail, especially at Au ball or Al wedge bond, if no appropriate precautions are taken. Fig. 13a shows the results of an early bond attempt, failing at the M2 trench etch stop layer, which is similar to the failure mechanism shown in Fig. 4. With improving low-k materials and integration approaches, however, and using optimised bond parameters, it is possible to get good assembly yield with both wire bond techniques [12]. Fig. 13b shows successful Au wire bonds to a JSR LKD 5109 dual damascene build.
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Fig. 12. Comparison of Joule heating for Cu / SiO2 and Cu / JSR LKD samples with and without dummy fill structures. The arrows indicate typical current densities for electromigration testing and use conditions.
3. Summary and outlook There has been significant progress in the last years regarding the integration of porous ultra low-k materials into a copper dual damascene scheme—the materials have become better, a lot more ultra
Fig. 13. Au wire bonds on JSR LKD, (a) first attempt, fail at the M2 trench etch stop layer; (b) later result with improved stack and optimised bond parameters.
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low-k compatible unit processes have been developed and the integration approaches are better characterised. Nonetheless, the vastly different properties of spin-on porous ultra low-k materials compared to silicon dioxide lead to unique challenges during the semiconductor manufacturing process. Basically, every single unit process has to be optimised to ensure that the low-k material is not damaged. Due to the mechanical weakness of the ultra low-k materials, CMP becomes a very critical process, and alternatives to conventional CMP would be very advantageous for the integration of ultra low-k materials. Due to their open porosity and very large surface area, every production step that exposes the low-k material to e.g. a plasma, or a wet chemical treatment, has to be critically examined. The best integration scheme in this respect is the one avoiding contact of the low-k material to such processes. Our experiments show further that even when the parametric test data is good, there may be problems further down the road. Packaging and assembly techniques have to be adapted to the new materials, or the integration approaches have to be modified until conventional assembly techniques work. But even when wafer fabrication and assembly work without problems, there still is the open question of how good especially the electromigration reliability of Cu / low-k will be. Due to the much lower modulus, the back driving force during electromigration will definitely be smaller than in the case of Cu / oxide, leading to a shorter average lifetime in the same structures. More work is needed to evaluate the potential for improvement by changing e.g. integration approaches. Furthermore, it has to be investigated whether the extrapolations conventionally used to estimate failure rates at real-life use conditions from the accelerated test conditions are a good enough approximation in the case of Cu / low-k materials, and if the observed reliability results would be sufficient for future technology generations.
Acknowledgements The authors wish to thank International Sematech’s Advanced Tool Development Facility (ATDF), the staff of the Interconnect Division, the electrical test and physical analysis labs for their help in processing the samples used in this investigation. We are indebted to a large number of companies than cannot be listed here individually; especially low-k dielectrics vendors and chemical suppliers for supplying pre-production versions of their resins and other chemicals for the characterisation and integration work, and tool manufacturers for supporting the development of new improved unit processes for the new materials.
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