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Jet vapor deposition nitride processing and application to advanced CMOS devices for reduction of gate leakage current and boron penetration
Materials Science in Semiconductor Processing 3 (2000) 173–178
Jet vapor deposition nitride processing and application to advanced CMOS devices for reduction of gate leakage current and boron penetration H.-H. Tsenga,*, J. Veterana, P.J. Tobina, J. Mogaba, P.G.Y. Tsuia, V. Wanga, M. Khareb, X.W. Wangb, T.P. Mab, C. Hobbsa, R. Hegdea, M. Hartiga, G. Keniga, R. Blumenthala, R. Cottona, V. Kaushika, T. Tamagawac, B.L. Halpernc, G.J. Cuic, J.J. Schmittc a
APRDL, Motorola, Austin, TX 78721, USA b Yale University, New Haven, CT, USA c Jet Process Corporation, New Haven, CT, USA
Abstract The increase in gate leakage current and boron penetration are major problems for scaled gate dielectrics in advanced device technology. We have demonstrated, for the first time, reduction in gate leakage current and strong resistance to boron penetration when jet vapor deposition (JVD) nitride is used as a gate dielectric in an advanced CMOS process. JVD nitride provides a robust interface in addition to well behaved bulk properties, MOSFET characteristics and ring oscillator performance. Process optimization is discussed. Manufacturing issues remain to be addressed. # 2000 Elsevier Science Ltd. All rights reserved. Keywords: Gate leakage current; Boron penetration; Jet vapor deposition
1. Introduction In order to improve device performance, the gate oxide has been scaled aggressively for advanced technology. There are two major challenges as the gate oxide thickness decreases: (1) gate leakage current through the gate oxide increases significantly, and (2) boron penetration in surface-channel PMOSFETs with P+ gate increases significantly. One efficient way to reduce leakage current is to use a gate dielectric with a high dielectric constant which provides a physically thicker film for the same electrically equivalent SiO2 thickness. Silicon nitride is an attractive candidate for this purpose due to its relatively high dielectric constant. Further, nitride is an efficient diffusion barrier which can minimize the boron penetration problems encountered for P+ gate *Corresponding author. Fax:+1-512-933-6962. E-mail address: [email protected] (H.-H. Tseng).
integration. However, conventional CVD nitride has a poor interface with silicon and is leaky due to a high trap density in the film. Therefore, it is not an attractive candidate for a future gate dielectric for ULSI. Recently, nitride deposited by jet vapor deposition (JVD) has been studied, and has shown encouraging electrical results with an aluminum gate [1,2]. However, it is important to improve the deposition processing of JVD nitride film [3], and study JVD nitride with a polysilicon gate for deep-sub-micron technology. In this work we will discuss both the processing aspects of JVD nitride film and the results of implementing JVD nitride as a gate dielectric for devices using a 0.35 mm CMOS technology.
2. Experiment JVD nitride is deposited in a vacuum chamber, using a supersonic remote plasma jet. A diagram of the jet
1369-8001/00/$ - see front matter # 2000 Elsevier Science Ltd. All rights reserved. PII: S 1 3 6 9 - 8 0 0 1 ( 9 9 ) 0 0 0 2 4 - 4
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Fig. 1. Schematic of the jet vapor deposition system.
nozzle is shown in Fig. 1. It consists of two concentric quartz tubes. For a constant flow velocity, the diameter of the outer nozzle defines the jet velocity. It is the supersonic velocity of the gases that provides the unique characteristics of the JVD process. For the same flow rate, larger diameter tubing reduces the jet velocity. The source gases for the nitride deposition flow separately through these nozzles, with the outer nozzle carrying the nitrogen source in the form of nitrogen gas mixed with a helium carrier gas in a 4.6% mixture, and the inner nozzle carrying silane with a He carrier gas in a 0.0004% mixture. A microwave cavity (operated at a nominal 100 W power) that is mounted around the outer nozzle is used to generate the plasma. Devices were built using a 0.35 mm technology [4] with shallow trench isolation, N+/P+ gates, Ti-salicide, and shallow transistor extensions with 1400 A˚ nitride spacer. Wafers were delivered to Yale University for JVD nitride deposition. After wafer cleaning, JVD nitride was deposited in the single wafer chamber. Upon receiving the wafers from Yale, an 8008C post deposition anneal was performed prior to depositing the polysilicon gate and the completion of wafer processing.
Fig. 2. Scanning speed profile from the center to the edge of the wafer.
Fig. 3. Thickness uniformity across a 200 mm wafer.
3. Results and discussions Fig. 4. Microwave power versus thickness and refractive index.
3.1. JVD nitride deposition processing Studies of various wafer scanning profiles were performed to optimize the thickness uniformity. Fig. 2 depicts the digitized scan profile used for two conditions. Fig. 3 shows the resulting wafer thickness uniformity patterns obtained with the two scan profiles indicated. A wafer uniformity of 3% (3 S.D.) across a 200 mm wafer was obtained in this study. Improvement of across wafer uniformity is possible with improved scanning profiles. The effect of variation to the jet nozzle assembly was studied to determine its effect on thickness, film uniformity and refractive index (RI), as shown in Fig. 4. Increases in the power did not increase the deposition rate of the film, or change the thickness uniformity across the wafer. However, the index of refraction was observed to increase as the plasma power
was increased. This is most likely due to increased nitrogen and reduced hydrogen incorporation, in the film. Some heating of the wafer occurred during the deposition. This heating was related to the microwave power level, but in all cases the wafer temperature (as measured with an infrared pyrometer) remained below 508C. Auger depth profiling of the as-deposited films has shown the JVD nitride films are uniform in composition in depth and across the wafer. The oxygen level measured in several samples was 8–20%, as is shown in Fig. 5. One source of oxygen was determined to be oxidant impurities in the source gases. An upgrade to semiconductor grade gases reduced the oxygen incorporation by 50%. It is believed that the remaining oxygen source is due to the outgassing of the system
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walls. Since the system is not load locked, the adsorption of oxygen occurs each time a wafer is loaded.
3.2. Device results Figure 6 shows the TEM cross-section of the poly/ JVD nitride/Si structure. The physical thickness of the JVD nitride film is 50 A˚ while the equivalent oxide thickness (EOT) is 30 A˚, measured using a transistor in the inversion mode. The increased physical thickness, due to the high dielectric constant of nitride, resulted in 100 times lower leakage current than 30 A˚ SiO2 at 5 MV/ cm electric field as shown in Fig. 7. In order to study the film stability, poly gate capacitors of JVD nitride and thermal oxide fabricated with the full CMOS process were stressed using constant current injection to a 0.5 C/ cm2 fluence. Fig. 8 shows that there is no hysteresis in the C–V measurement and that the flat-band voltage shift for JVD nitride after stressing is comparable to that of thermal oxide. These results demonstrate that the interface stability of JVD nitride compares favorably with thermal oxide.
Fig. 5. Auger depth profile of JVD Nitride.
Fig. 7. J–E comparison for JVD nitride and thermal oxide.
Post nitride deposition annealing plays an important role in achieving a stable JVD nitride film. Fig. 9 shows the results of SIMS analysis for 55 A˚ thick JVD nitride film before and after 8008C post deposition anneal in nitrogen. The anneal process reduces both the surface and bulk hydrogen concentration significantly. To investigate the strong resistance to boron penetration with JVD nitride, we built capacitors with standard boron and BF2 implantation for P+ gate as well as transistors with very high dose P+ gate implantation conditions. N+ and P+ poly gate capacitors were fabricated on N-type substrates. Fig. 10 shows the normalized high frequency C–V results from the capacitors. For the N+ gate case, JVD nitride reveals a negative shift as compared with thermal oxide due to the larger fixed charge contained in JVD nitride. It is well known that boron penetration causes flat-band voltage increase for P+ gate processing. For the B implanted P+ gate case, the flat-band voltage for thermal oxide is about 0.7 V larger than JVD nitride. The flat-band voltage difference is even larger (about 0.9 V) for BF2 implanted P+ gate due to fluorineenhanced boron penetration. After compensating the 0.2 V flat-band voltage shift caused by fixed charge contained in JVD nitride as observed from N+ gate case, the thermal oxide still results in a much larger flatband voltage than JVD nitride for P+ gate case caused by boron penetration. Furthermore, the negligible C–V difference between B and BF2 implanted P+ gate
Fig. 6. TEM cross-section of poly/JVD nitride/Si structure.
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Fig. 8. C–V shift comparison for JVD nitride and thermal oxide after stressing.
Fig. 9. SIMS analysis for post nitride deposition anneal.
capacitors using JVD nitride, suggests that JVD nitride has a strong resistance to fluorine-enhanced boron penetration. To examine the boron penetration resistance with JVD nitride for the transistors, the threshold voltage was compared for thermal oxide and JVD nitride as shown in Fig. 11. For the N-ch MOSFET, JVD nitride shows a slightly lower threshold voltage (Vt,n) than thermal oxide due to the influence of the fixed charge associated with the nitride film. For the P-ch MOSFET, because a very high BF2 dose was implanted into the P+ gate, the thermal oxide shows severe boron penetration effects which cause a shift of the threshold voltage from the expected value (ÿ0.5 V), to a slightly positive value. The P-ch MOSFET threshold voltage (Vt,p) for JVD nitride is strongly negative. The negative Vt,p for JVD nitride is partially due to strong resistance to boron penetration and partially due to the additive effect of fixed charge and increased donor-like interface states originating from the nitride [5]. Fig. 12 shows the N-ch MOSFET I–V characteristics where the normalized Id of
Fig. 10. Boron penetration resistance comparison.
JVD nitride approaches that of thermal oxide. Fig. 13 shows that JVD nitride provides a well-behaved P-ch MOSFET I–V characteristic. The current drive is relatively low which we postulate to be due to the high Vt,p caused by fixed charge and interface state density (Dit). However, this problem can be addressed by in situ N2O plasma pre-treatment before JVD nitride deposition and additional water vapor anneal [2]. In order to demonstrate the stability of the device, transistor I–V characteristics before and after constant E-field (10 MV/cm) stressing were measured for the Nch MOSFET as shown in Figs. 14 and 15. The JVD nitride sample showed comparable I–V shift to thermal oxide indicating excellent transistor stability. Fig. 16 shows the product of power and stage delay for a CMOS ring oscillator with 125 inverter stages using JVD nitride compared to a CMOS ring oscillator using thermal
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Fig. 14. Thermal oxide NMOSFET stability.
Fig. 11. Threshold voltage comparison.
Fig. 15. JVD nitride NMOSFET stability.
Fig. 12. NMOSFET I–V characteristic comparison. Id: drain current, Vd: drain voltage.
Fig. 16. CMOS ring oscillator results for JVD nitride.
Fig. 13. PMOSFET I–V characteristic for JVD nitride. Id: drain current, Vd: drain voltage.
oxide. The fact that a functional ring oscillator is achieved with JVD nitride suggests there is no fundamental obstacle to the use of JVD nitride for advanced technology.
power on film composition are discussed. JVD nitride can address the two major challenges faced by aggressive gate oxide thickness reduction for advanced technology with no fundamental integration obstacle. This technique reduces gate leakage current significantly for the same oxide equivalent thickness. It also demonstrates strong resistance to boron penetration, a robust interface and well behaved bulk properties, and as stable transistor characteristics.
Acknowledgements
4. Conclusions The effects of the scanning profile of the JVD nitride system on thickness uniformity and the microwave
The authors would like to express thanks for the support of the APRDL Pilot Line and Process Engineering Department. The managerial support from Lou Parrillo, Fabio Pintchovski and Bob Yeargain are appreciated.
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H.-H. Tseng et al. / Materials Science in Semiconductor Processing 3 (2000) 173–178
References [1] Wang XW, Ma TP, Cui GJ, Tamagawa T, Golz JW, Karecki S, Halpern BL, Schmitt JJ. In: International Conference on Solid State Devices and Materials, 1994. p. 856. [2] Khare M, Guo Xin, Wang XW, Ma TP, Cui GJ, Tamagawa T, Halpern BL, Schmitt JJ. In: Symposium on VLSI Technology, 1997. p. 51.
[3] Veteran J, Hobbs C, Hegde R, Tobin P, Wang V, Tseng H, Kenig G, Hartig M, Doran T, Makowicz P, Schmitt J, Harpern B, Zhang JZ. Mater Res Soc Symp Proc 1998;495:445. [4] Tsui P, Tseng H-H, Orlowski M, Sun SW, Tobin PJ, Reid K, Taylor WJ. In: IEDM, 1994. p. 501. [5] Hori T. In: IEEE TED, 1990. p. 2058.
Jet vapor deposition nitride processing and application to advanced CMOS devices for reduction of gate leakage current and boron penetration H.-H. Tsenga,*, J. Veterana, P.J. Tobina, J. Mogaba, P.G.Y. Tsuia, V. Wanga, M. Khareb, X.W. Wangb, T.P. Mab, C. Hobbsa, R. Hegdea, M. Hartiga, G. Keniga, R. Blumenthala, R. Cottona, V. Kaushika, T. Tamagawac, B.L. Halpernc, G.J. Cuic, J.J. Schmittc a
APRDL, Motorola, Austin, TX 78721, USA b Yale University, New Haven, CT, USA c Jet Process Corporation, New Haven, CT, USA
Abstract The increase in gate leakage current and boron penetration are major problems for scaled gate dielectrics in advanced device technology. We have demonstrated, for the first time, reduction in gate leakage current and strong resistance to boron penetration when jet vapor deposition (JVD) nitride is used as a gate dielectric in an advanced CMOS process. JVD nitride provides a robust interface in addition to well behaved bulk properties, MOSFET characteristics and ring oscillator performance. Process optimization is discussed. Manufacturing issues remain to be addressed. # 2000 Elsevier Science Ltd. All rights reserved. Keywords: Gate leakage current; Boron penetration; Jet vapor deposition
1. Introduction In order to improve device performance, the gate oxide has been scaled aggressively for advanced technology. There are two major challenges as the gate oxide thickness decreases: (1) gate leakage current through the gate oxide increases significantly, and (2) boron penetration in surface-channel PMOSFETs with P+ gate increases significantly. One efficient way to reduce leakage current is to use a gate dielectric with a high dielectric constant which provides a physically thicker film for the same electrically equivalent SiO2 thickness. Silicon nitride is an attractive candidate for this purpose due to its relatively high dielectric constant. Further, nitride is an efficient diffusion barrier which can minimize the boron penetration problems encountered for P+ gate *Corresponding author. Fax:+1-512-933-6962. E-mail address: [email protected] (H.-H. Tseng).
integration. However, conventional CVD nitride has a poor interface with silicon and is leaky due to a high trap density in the film. Therefore, it is not an attractive candidate for a future gate dielectric for ULSI. Recently, nitride deposited by jet vapor deposition (JVD) has been studied, and has shown encouraging electrical results with an aluminum gate [1,2]. However, it is important to improve the deposition processing of JVD nitride film [3], and study JVD nitride with a polysilicon gate for deep-sub-micron technology. In this work we will discuss both the processing aspects of JVD nitride film and the results of implementing JVD nitride as a gate dielectric for devices using a 0.35 mm CMOS technology.
2. Experiment JVD nitride is deposited in a vacuum chamber, using a supersonic remote plasma jet. A diagram of the jet
1369-8001/00/$ - see front matter # 2000 Elsevier Science Ltd. All rights reserved. PII: S 1 3 6 9 - 8 0 0 1 ( 9 9 ) 0 0 0 2 4 - 4
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H.-H. Tseng et al. / Materials Science in Semiconductor Processing 3 (2000) 173–178
Fig. 1. Schematic of the jet vapor deposition system.
nozzle is shown in Fig. 1. It consists of two concentric quartz tubes. For a constant flow velocity, the diameter of the outer nozzle defines the jet velocity. It is the supersonic velocity of the gases that provides the unique characteristics of the JVD process. For the same flow rate, larger diameter tubing reduces the jet velocity. The source gases for the nitride deposition flow separately through these nozzles, with the outer nozzle carrying the nitrogen source in the form of nitrogen gas mixed with a helium carrier gas in a 4.6% mixture, and the inner nozzle carrying silane with a He carrier gas in a 0.0004% mixture. A microwave cavity (operated at a nominal 100 W power) that is mounted around the outer nozzle is used to generate the plasma. Devices were built using a 0.35 mm technology [4] with shallow trench isolation, N+/P+ gates, Ti-salicide, and shallow transistor extensions with 1400 A˚ nitride spacer. Wafers were delivered to Yale University for JVD nitride deposition. After wafer cleaning, JVD nitride was deposited in the single wafer chamber. Upon receiving the wafers from Yale, an 8008C post deposition anneal was performed prior to depositing the polysilicon gate and the completion of wafer processing.
Fig. 2. Scanning speed profile from the center to the edge of the wafer.
Fig. 3. Thickness uniformity across a 200 mm wafer.
3. Results and discussions Fig. 4. Microwave power versus thickness and refractive index.
3.1. JVD nitride deposition processing Studies of various wafer scanning profiles were performed to optimize the thickness uniformity. Fig. 2 depicts the digitized scan profile used for two conditions. Fig. 3 shows the resulting wafer thickness uniformity patterns obtained with the two scan profiles indicated. A wafer uniformity of 3% (3 S.D.) across a 200 mm wafer was obtained in this study. Improvement of across wafer uniformity is possible with improved scanning profiles. The effect of variation to the jet nozzle assembly was studied to determine its effect on thickness, film uniformity and refractive index (RI), as shown in Fig. 4. Increases in the power did not increase the deposition rate of the film, or change the thickness uniformity across the wafer. However, the index of refraction was observed to increase as the plasma power
was increased. This is most likely due to increased nitrogen and reduced hydrogen incorporation, in the film. Some heating of the wafer occurred during the deposition. This heating was related to the microwave power level, but in all cases the wafer temperature (as measured with an infrared pyrometer) remained below 508C. Auger depth profiling of the as-deposited films has shown the JVD nitride films are uniform in composition in depth and across the wafer. The oxygen level measured in several samples was 8–20%, as is shown in Fig. 5. One source of oxygen was determined to be oxidant impurities in the source gases. An upgrade to semiconductor grade gases reduced the oxygen incorporation by 50%. It is believed that the remaining oxygen source is due to the outgassing of the system
H.-H. Tseng et al. / Materials Science in Semiconductor Processing 3 (2000) 173–178
175
walls. Since the system is not load locked, the adsorption of oxygen occurs each time a wafer is loaded.
3.2. Device results Figure 6 shows the TEM cross-section of the poly/ JVD nitride/Si structure. The physical thickness of the JVD nitride film is 50 A˚ while the equivalent oxide thickness (EOT) is 30 A˚, measured using a transistor in the inversion mode. The increased physical thickness, due to the high dielectric constant of nitride, resulted in 100 times lower leakage current than 30 A˚ SiO2 at 5 MV/ cm electric field as shown in Fig. 7. In order to study the film stability, poly gate capacitors of JVD nitride and thermal oxide fabricated with the full CMOS process were stressed using constant current injection to a 0.5 C/ cm2 fluence. Fig. 8 shows that there is no hysteresis in the C–V measurement and that the flat-band voltage shift for JVD nitride after stressing is comparable to that of thermal oxide. These results demonstrate that the interface stability of JVD nitride compares favorably with thermal oxide.
Fig. 5. Auger depth profile of JVD Nitride.
Fig. 7. J–E comparison for JVD nitride and thermal oxide.
Post nitride deposition annealing plays an important role in achieving a stable JVD nitride film. Fig. 9 shows the results of SIMS analysis for 55 A˚ thick JVD nitride film before and after 8008C post deposition anneal in nitrogen. The anneal process reduces both the surface and bulk hydrogen concentration significantly. To investigate the strong resistance to boron penetration with JVD nitride, we built capacitors with standard boron and BF2 implantation for P+ gate as well as transistors with very high dose P+ gate implantation conditions. N+ and P+ poly gate capacitors were fabricated on N-type substrates. Fig. 10 shows the normalized high frequency C–V results from the capacitors. For the N+ gate case, JVD nitride reveals a negative shift as compared with thermal oxide due to the larger fixed charge contained in JVD nitride. It is well known that boron penetration causes flat-band voltage increase for P+ gate processing. For the B implanted P+ gate case, the flat-band voltage for thermal oxide is about 0.7 V larger than JVD nitride. The flat-band voltage difference is even larger (about 0.9 V) for BF2 implanted P+ gate due to fluorineenhanced boron penetration. After compensating the 0.2 V flat-band voltage shift caused by fixed charge contained in JVD nitride as observed from N+ gate case, the thermal oxide still results in a much larger flatband voltage than JVD nitride for P+ gate case caused by boron penetration. Furthermore, the negligible C–V difference between B and BF2 implanted P+ gate
Fig. 6. TEM cross-section of poly/JVD nitride/Si structure.
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H.-H. Tseng et al. / Materials Science in Semiconductor Processing 3 (2000) 173–178
Fig. 8. C–V shift comparison for JVD nitride and thermal oxide after stressing.
Fig. 9. SIMS analysis for post nitride deposition anneal.
capacitors using JVD nitride, suggests that JVD nitride has a strong resistance to fluorine-enhanced boron penetration. To examine the boron penetration resistance with JVD nitride for the transistors, the threshold voltage was compared for thermal oxide and JVD nitride as shown in Fig. 11. For the N-ch MOSFET, JVD nitride shows a slightly lower threshold voltage (Vt,n) than thermal oxide due to the influence of the fixed charge associated with the nitride film. For the P-ch MOSFET, because a very high BF2 dose was implanted into the P+ gate, the thermal oxide shows severe boron penetration effects which cause a shift of the threshold voltage from the expected value (ÿ0.5 V), to a slightly positive value. The P-ch MOSFET threshold voltage (Vt,p) for JVD nitride is strongly negative. The negative Vt,p for JVD nitride is partially due to strong resistance to boron penetration and partially due to the additive effect of fixed charge and increased donor-like interface states originating from the nitride [5]. Fig. 12 shows the N-ch MOSFET I–V characteristics where the normalized Id of
Fig. 10. Boron penetration resistance comparison.
JVD nitride approaches that of thermal oxide. Fig. 13 shows that JVD nitride provides a well-behaved P-ch MOSFET I–V characteristic. The current drive is relatively low which we postulate to be due to the high Vt,p caused by fixed charge and interface state density (Dit). However, this problem can be addressed by in situ N2O plasma pre-treatment before JVD nitride deposition and additional water vapor anneal [2]. In order to demonstrate the stability of the device, transistor I–V characteristics before and after constant E-field (10 MV/cm) stressing were measured for the Nch MOSFET as shown in Figs. 14 and 15. The JVD nitride sample showed comparable I–V shift to thermal oxide indicating excellent transistor stability. Fig. 16 shows the product of power and stage delay for a CMOS ring oscillator with 125 inverter stages using JVD nitride compared to a CMOS ring oscillator using thermal
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Fig. 14. Thermal oxide NMOSFET stability.
Fig. 11. Threshold voltage comparison.
Fig. 15. JVD nitride NMOSFET stability.
Fig. 12. NMOSFET I–V characteristic comparison. Id: drain current, Vd: drain voltage.
Fig. 16. CMOS ring oscillator results for JVD nitride.
Fig. 13. PMOSFET I–V characteristic for JVD nitride. Id: drain current, Vd: drain voltage.
oxide. The fact that a functional ring oscillator is achieved with JVD nitride suggests there is no fundamental obstacle to the use of JVD nitride for advanced technology.
power on film composition are discussed. JVD nitride can address the two major challenges faced by aggressive gate oxide thickness reduction for advanced technology with no fundamental integration obstacle. This technique reduces gate leakage current significantly for the same oxide equivalent thickness. It also demonstrates strong resistance to boron penetration, a robust interface and well behaved bulk properties, and as stable transistor characteristics.
Acknowledgements
4. Conclusions The effects of the scanning profile of the JVD nitride system on thickness uniformity and the microwave
The authors would like to express thanks for the support of the APRDL Pilot Line and Process Engineering Department. The managerial support from Lou Parrillo, Fabio Pintchovski and Bob Yeargain are appreciated.
178
H.-H. Tseng et al. / Materials Science in Semiconductor Processing 3 (2000) 173–178
References [1] Wang XW, Ma TP, Cui GJ, Tamagawa T, Golz JW, Karecki S, Halpern BL, Schmitt JJ. In: International Conference on Solid State Devices and Materials, 1994. p. 856. [2] Khare M, Guo Xin, Wang XW, Ma TP, Cui GJ, Tamagawa T, Halpern BL, Schmitt JJ. In: Symposium on VLSI Technology, 1997. p. 51.
[3] Veteran J, Hobbs C, Hegde R, Tobin P, Wang V, Tseng H, Kenig G, Hartig M, Doran T, Makowicz P, Schmitt J, Harpern B, Zhang JZ. Mater Res Soc Symp Proc 1998;495:445. [4] Tsui P, Tseng H-H, Orlowski M, Sun SW, Tobin PJ, Reid K, Taylor WJ. In: IEDM, 1994. p. 501. [5] Hori T. In: IEEE TED, 1990. p. 2058.