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Logic gates based on edge states in gyromagnetic photonic crystal
Journal Pre-proofs Research articles Logic gates based on edge states in gyromagnetic photonic crystal Rui Ge, Bei Yan, Jianlan Xie, Exian Liu, Wei Tan, Jianjun Liu PII: DOI: Reference:
S0304-8853(18)34166-0 https://doi.org/10.1016/j.jmmm.2019.166367 MAGMA 166367
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Journal of Magnetism and Magnetic Materials
Received Date: Revised Date: Accepted Date:
24 December 2018 8 December 2019 27 December 2019
Please cite this article as: R. Ge, B. Yan, J. Xie, E. Liu, W. Tan, J. Liu, Logic gates based on edge states in gyromagnetic photonic crystal, Journal of Magnetism and Magnetic Materials (2019), doi: https://doi.org/10.1016/ j.jmmm.2019.166367
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Logic gates based on edge states in gyromagnetic photonic crystal Rui Ge, Bei Yan, Jianlan Xie, Exian Liu, Wei Tan and Jianjun Liu* Key Laboratory for Micro/Nano Optoelectronic Devices of Ministry of Education & Hunan Provincial Key Laboratory of Low-Dimensional Structural Physics and Devices, School of Physics and Electronics, Hunan University, Changsha 410082, China *
Corresponding author.
E-mail Addresses: [email protected] Abstract Three logic gates based on the one-way edge states in gyromagnetic photonic crystal (GPC) are proposed and analyzed theoretically. The frequency range of the one-way transmission of waveguide is obtained with Finite Element Method (FEM). The relationships between the performance parameters and the structure parameters are investigated. To estimate whether the logic gates are robust, the transmission efficiencies of logic gates with an obstacle in different positions are calculated. Simulation results show that a high contrast ratio (CR) and strong robustness can be obtained. This work is expected to provide guidance to the design of logic gate with high performance. Keywords: gyromagnetic photonic crystal, logic gate, contrast ratio 1. Introduction Logic gates based on photonic crystal (PC) have shown many advantages including simple structure, strong confinement of light and easiness of integrating on chip [1-3]. However, traditional PC-based logic gates [4, 5] have shown a lot of weaknesses such as unwanted strong backward light propagation effect and weak robustness [1, 6], which may degrade their performance. Obviously, the strong backward light propagation is reflected in the weak isolating effect of the different input channels of
the logic gate [5]. The weak robustness is reflected in the low tolerance of fabrication errors, such as, the deviations of the structure parameters or the positions of the rods [6] in the PC will affect the performance of the logic gate. According to the previous works, the solutions of these weaknesses include improving the fabrication process of the logic gates [7] or introducing one-way edge state [8]. However, fabrication error is unavoidable whatever fabrication process is improved [9]. Therefore, the key method is to introduce the one-way edge state into the logic gate. Theories and experiments verified that integer quantum Hall effect can be extended to photonic field, which makes the one-way edge state become the research hotspot [10-13]. The principle of creating the one-way edge state is that external magnetic field can break up the time-reversal symmetry and lift the degeneracies and create a gap which makes the chern number of other gaps below this one become non-zero [10-15]. Beam splitter [16], add-drop filter [9, 17-19] and circulator [20] based on the one-way edge state in GPC have been proposed in recent years. Traditional investigations of GPC put emphasis on the transmission properties of only one input signal. However, investigation of GPC with more than one input signal has not been reported yet. Definitely, study of GPC with more than one input signal is of great importance because devices with more than one input signal are vital components in signal processor devices [21]. Moreover, comparing with traditional nonreciprocal transmission phenomenon [22, 23], the one-way transmission based on edge state has shown many advantages including circumventing the obstacle with low loss and have no backscattering which results in that the forward transmission efficiency is 50 dB higher than the backward one [11]. These merits enable the GPC to be the best candidate structure for the high-quality logic gate. In this work, three logic gates based on the edge states in GPC are proposed. Logic operations are achieved by interference effect. The relationships between the structure parameters and the performance parameters are analyzed. The optimum logic gates have a high CR and strong robustness. 2. Modeling and theory
The logic gates are composed of waveguide with the applied external magnetic field which consists of the PC and the GPC in which the magnetic field is in the out-of-plane direction. The structure of waveguide is shown in Fig. 1(a). The frequency ranges of the one-way-transmission of supercells of the waveguide must be calculated before designing the logic gates.
Fig. 1. (a) Structure of waveguide consisting of PC and GPC, the structure in red dash line represents the calculated supercell. (b) The relationship between the frequencies and the CR of waveguide consisting of PC and GPC. (c) Band gap diagram of the supercell. The structures are constructed by rods in air background. The PC is composed of alumina (Al) rods which are arranged in the 45° tilted square lattice with the lattice constant LAl=a/ 2 . The radius and dielectric constant of Al rods are r1=0.106a and ε1=10. The GPC is composed of yttrium-iron-garnet (YIG) rods which are arranged in the square lattice with lattice constant LYIG=a. The radius and dielectric constant of YIG rods are r2=0.11a and ε2=15-0.003j [11, 19]. When the external magnetic field is
applied in ±z direction (out-of-plane direction or in-plane direction), the permeability of YIG rods becomes the tensor [16]
0 ik 0
ik 0 0 0 1
(1)
where =1+m0 / (0 2 2 ) , k =m / (0 2 2 ) , μ0 is the permeability of vacuum, 0 =2 H 0 is the precession frequency, and =2.8 106 rad s -1G -1 is the gyromagnetic ratio,
H0
is the magnetic field,
m =2 (4 ms )
is the
characteristic frequency and 4 ms =1780 G is the saturation magnetization [19, 24]. When external magnetic field intensity equals to 1600 G and the frequency of incident waves is 4.28 GHz, the corresponding parameters are ω=26.89 GHz, μ=14, k=12.4 [11, 16]. The external magnetic field is always applied in +z direction in our research. In general, the YIG rod is commercially available [25], and the detailed fabrication procedure can be referred to Ref. [26]. The one-way properties of the waveguides and performance of the logic gates is analyzed with the FEM-software COMSOL Multiphysics. Perfectly matched layers are set to absorb energies [27-29]. All input signals in the logic gates are TM polarized plane waves. The relationships between the frequency and the CR of the forward and backward transmission efficiencies of the waveguide, and the band gap diagram of supercell of structure consisting of PC and GPC, are shown in Fig. 1(b)-1(c). The frequency, where the CR is larger than 45 dB, is defined as one-way transmission frequency. It can be inferred from Figs. 2 (a) and 2 (b) that one-way transmission frequency of waveguide composed of PC and GPC ranges from 0.5256 (2πc/a) to 0.5768 (2πc/a). If the frequencies of source are in the one-way frequency range, the signal can propagate in only one direction. The schematics of the proposed “OR”, “XOR” and “NOR” gates are illustrated in Fig. 2 and the structure parameters including the radius or the material of rods and the lattice constant are the same with those of structures in Fig. 1(a) except for the
radius of defect rods.
Fig. 2. The schematics of the proposed (a) “OR” gate, (b) “XOR” gate and (c) “NOR” gate, (d) Potential characterization model of “XOR” gate. To create phase difference of the signals in PC, the common methods includes constructing a cavity [30], introducing extra rods with much smaller radius [31] or increasing the number of rods in one input channel to create signal path difference
[32]. Increasing the number of rods has advantages such as simple of operating and easiness of obtaining a large bandwidth. However, the number of rods must be integer, which results in the weak adjustability. Introducing extra rods with small radius brings a large bandwidth and shows strong adjustability but have a low CR [31]. Although constructing a cavity shows shortcoming like having a low bandwidth, it shows strong adjustability and a high CR [30]. In this work, cavity [33, 34] is constructed to design “OR” or “XOR” gate with high performance. The proposed “OR” gate is shown in Fig. 2(a). Five Al rods are introduced into the center area of “OR” gate to form a cavity, where the radius of rods at top and right is set as r1 which is the same with that in Fig. 1(a) and the radius of rods at center and bottom and left is set as r3 (variable). Two sources with the same amplitudes and phases are placed near Ports 1 and 2 separately to launch input signals with the power of PI and the frequency of 0.528 (2πc/a), and Port 3 is set as output port. The monitor is placed near Port3 and the output power detected is defined as PO. To realize the logic operation of “1XOR1=0” by the destructive interference, the phases of two input signals must have a difference of π in the output port. The proposed “XOR” gate is shown in Fig. 2(b). The settings of ports, sources and monitor are the same with those in “OR” gate. The parameters of rods are also the same with those in “OR” gate except the defect rods. Four Al rods are introduced into the center area of “XOR” gate to form a cavity, where the radius of rods at top and right is set as r1 which is the same with that in Fig. 1(a) and the radius of rods at bottom and left is set as r4 (variable). To realize the logical operation of “0NOR0=1”, the reference source must be placed. Meanwhile, more waveguides must be constructed owing to the existence of three sources. Obviously, these waveguide channels must have large bandwidths to ensure the signals can flow to the output port. Consequently, rods with small radius are introduced to GPC to design “NOR” gate with high performance. The proposed “NOR” gate is shown in Fig. 2(c). The settings of ports, input sources and monitor are the same with those in “OR” gate. The parameters of rods are also the same with those in “OR” gate except the defect rods. The reference source whose amplitude,
phase and polarization are the same with other input sources is placed near Port 4. Six Al rods with radius of r5 are introduced into the logic gate. The potential characterization model of “XOR” gate is shown in Fig. 2(d). To check the performance of proposed logic gates, we may need a vector network analysis with two antennas, and the whole structure should be sandwiched by two copper plates. The detailed potential procedures of experiment can be referred to Ref. [12]. In this work, the input logic states are “00” when Port 1 and Port 2 don’t have input signals, and the input logic states are “01” when Port 1 doesn’t have input signal but Port 2 have input signal. The input logic states are “10” when Port 2 doesn’t have input signal but Port 1 has input signal. When Port 1 and Port 2 both have input signals, the input logic states are “11”. When the two input signals exist in the logic gate and reference source is not excited (“OR” gate and “XOR” gate), the transmission efficiency is defined as T
Pα Pβ Pγ
(2)
Where Pα is the power detected by the monitor at the output port, and Pβ and Pγ are the powers of different input sources. When the three input signals exist in the logic gate (“NOR” gate), the transmission efficiency is defined as T
Pα Pβ Pγ+Pδ
(3)
Where Pα is the power detected by the monitor at the output port, and Pβ, Pγ and Pδ are the powers of different sources. In Eqs. (2) and (3), the output logic state “1” is defined when the transmission efficiency is larger than 0.4, and the output logic state “0” is defined when transmission efficiency is lower than 0.3 [32]. CR is another important performance parameter to evaluate the logic gate. Obviously, a logic gate with a high CR will bring convenience to the detection of signals. In “OR” gate, the CR is defined as [5, 35]
CR 10 log
Pa Pb
(4)
Where Pa is the power detected at one input port where no source is placed when another input port placed source, and Pb is the power detected by the monitor in output port when only one input port launches signal. In “XOR” and “NOR” gate, the CR is defined as [32] CR 10 log
P2 P1
(5)
Where P1 or P2 represent the power detected by the monitor at the output port when the output logic state is “0” or “1”. For “XOR” gate, the output logic state is “1” when the input logic states are “01” or “10”, and the output logic state is “0” when the input logic states are “00” or “11”. Obviously, the CR has no sense when the input logic states are “00”. Consequently, CR may have two values: CR1 or CR2. Similarly, for “NOR” gate, the output logic state is “1” when input logic states are “00”, and the output logic state is “0” when the input logic states are “01”, “10” or “11”. Consequently, CR has three values: CR1, CR2 or CR3. 3.Result and discussion 3.1 Performance of “OR” gate When the frequency of input signals is chosen as ω=0.528 (2πc/a) and r3=0.235a, the truth table of “OR” gate is shown in Table 1. Table 1 Truth table of “OR” gate Port 1
Port 2
Port 3
PO
0
0
0
0
0
1
1
0.4086 PI
1
0
1
0.4643 PI
1
1
1
1.0402 PI
It can be inferred from Table 1 that when the input logic states are “00”, “01”, “10” and “11”, the power detected by the monitor at the output port are 0, 0.4086 PI, 0.4643 PI and 1.0402 PI. The Ez field distributions of “OR” gate when input logic states are “01”, “10” and “11” are shown in Fig. 3.
Fig. 3. The Ez field distributions of input logic states of (a) “01”, (b) “10” and (c) “11”. It can be inferred in Figs. 3(a) and 3(b) that the “OR” gate shows excellent isolation effect for the signals from the different input channel. To obtain the CR of “OR” gate, an extra monitor is placed near Port 2 (or Port1) and the input logic states are set as “10” (or “01”), the power detected by the extra monitor is 2.767×10-5 PI (or 3.3437×10-5 PI), resulting in a CR of 42.25 dB (or 40.87 dB). To examine whether the “OR” gate is robust, the transmission efficiency of “OR” gate in different conditions (with obstacle and without obstacle) should be obtained. The obstacle is chosen as the Perfect Electric Conductor (PEC) with the length of a in the simulation. The PEC is placed at the left input channel and the output channel respectively, if input logic states are “10”, then the transmission efficiency of “OR” gate are 0.5838 and 0.4554 respectively with the Poynting vector shown in Figs. 4(a) and 4(b). If input logic states are “11”, then the transmission efficiency of “OR” gate are 0.0973 and 0.5102 respectively with the Poynting vector shown in Figs. 4(c) and 4(d). It can be seen that there is no energy in output channel when PEC is placed at the left channel with input logic “11”.
Fig. 4. Poynting vector diagrams of input logic states “10” when (a) PEC is in the left input channel and (b) PEC is in the output channel. Poynting vector diagrams of input logic states “11” when (c) PEC is in the left input channel and (d) PEC is in the output channel. The above results indicates that, placing a PEC in the input channel, whatever the input logic states are, doesn’t influence the performance of “OR” gate. When the input logic states are “01” or “10”, placing a PEC in the input channel doesn’t influence the performance of “OR” gate. However, when the input logic states are “11”, placing a PEC in the input channel will result in the invalidation of “OR” gate. This phenomenon can be explained as, one-way edge state can circumvent the PEC with no loss, and when the input logic states are “11”, placing a PEC in the input or the output channel in “OR” gate will create more signal path for the transmitted signals and therefore changes their phase at the output port [11]. Eventually, the
interference states of the input signals are changed and the “OR” gate is invalid. When the input logic states are any values, placing a PEC in output channel will change the phases of the transmitted signals at the output port for the same degree and the “OR” gate can normally work. The “OR” gate based on one-way edge state is more robust than those based on the common PC. 3.2 Performance of “XOR” gate To design the “XOR” gate with high performance, the structure parameters of the logic gate must be optimized. The relationships between the performance parameters and the radius of defect rods or the frequency of the input signals are shown in Fig. 5.
Fig. 5. The relationships of “XOR” gate between r4 and (a) transmission efficiency or (b) CR. Relationships of “XOR” gate between ω and (c) transmission efficiency or (d) CR. The frequency of input signals is chosen as ω=0.528 (2πc/a), setting r4 ∈ [0.20a,0.24a] with an increment of Δr4=0.002a. Transmission efficiencies of input logic states of “01”, “10” and “11” are defined as T1, T2 and T3 and the CRs of input logic states of “01” and “10” are defined as CR1 and CR2. Figures 5(a) and 5(b) indicates that, as r4 increases, T1 first decreases and then increases and obtains its minimum value T1min=0.2352 at r4=0.206a. Meanwhile, as r4 increases, T2 first increases and then decreases and obtains its maximum value T2max=0.6506 at r3=0.206a. As r4 increases, T3 first decreases and then increases and obtains its
minimum value T3min=0.00028 at r3=0.214a. Moreover, as r4 increases, CR1 and CR2 both first increases and then decreases and obtain their maximum values CR1max=28.78 dB and CR2max=29.07 dB at r4=0.214a. Consequently, r4=0.214a is chosen as the optimized parameter. In order to calculate the bandwidth of “XOR” gate, we have simulated the dependence of frequency of signals on transmission efficiency and contrast ratio of logic gates. Setting ω ∈ [0.525 (2πc/a), 0.535 (2πc/a)] with an increment of Δω=0.0001 (2πc/a). Transmission efficiencies of input logic states of “01”, “10” and “11” are defined as T4, T5 and T6 and the CRs of input logic states of “01” and “10” are defined as CR3 and CR4. Figures 5(c) and 5(d) indicate that, as ω increases, T4 first decreases and then increases and obtains its minimum value T4min=0.4199 at ω=0.5266 (2πc/a), and T5 first increases and then decreases and obtains its maximum value T5max=0.4613 at ω=0.5286 (2πc/a), and T6 first decreases and then increases and obtains its minimum value T6min=0.00022 at ω=0.5288 (2πc/a). Moreover, as ω increases, CR3 and CR4 both first increase and then decrease and obtain their maximum values CR3max=29.98 dB and CR4max=30.23 dB at ω=0.5288 (2πc/a). The bandwidth of “XOR” gate is defined as frequency range where contrast ratios are larger than 15 dB [36, 37]. It can be noticed that the contrast ratio is larger than 15 dB when ω∈[0.5252 (2πc/a), 0.5327 (2πc/a)]. Consequently, the bandwidth of “XOR” gate is 0.0075 (2πc/a). When r4=0.214a, the truth table of “XOR” gate is shown in Table 2. Table 2 Truth table of “XOR” gate Port 1
Port 2
Port 3
PO
0
0
0
0
0
1
1
0.4283 PI
1
0
1
0.4582 PI
1
1
0
0.00056 PI
It can be inferred from Table 2 that, when the input logic states are “00”, “01”, “10” and “11”, the powers detected by the monitor at the output port are 0, 0.4283 PI, 0.4582 PI and 0.00056 PI respectively. The Ez field distributions of “XOR” gate when
input logic states are “01”, “10” and “11” are shown in Fig. 6.
Fig. 6. The Ez field distributions of input logic states of (a) “01”, (b) “10” and (c) “11”. The maximum CR of “XOR” gate with optimized structure parameters is 29.07 dB. To examine whether the “XOR” gate is robust, a PEC of L=a is firstly placed in the output channel, when input logic states are “01”, “10” and “11”, transmission efficiencies detected by the monitor at the output port are 0.4353, 0.4556 and 0.0003 respectively. Then a PEC of L=a is placed in the left input channel, when input logic states are “01”, “10” and “11”, transmission efficiencies detected by the monitor at the output port are 0.5237, 0.3861 and 0.4079. The results indicate that only when the input logic states are “11” and the PEC is placed in the input channel, the “XOR” gate is invalid. 3.3 Performance of “NOR” gate To design the “NOR” gate with high performance, the structure parameters of the logic gate must be optimized. The relationships between the performance parameters and the radius of defect rods or the frequency of the input signals are shown in Fig. 7.
Fig. 7. The relationships of “NOR” gate between r5 and (a) transmission efficiency or (b) CR. Relationships of “NOR” gate between ω and (c) transmission efficiency or (d) CR. The frequency of input signals is chosen as ω=0.528 (2πc/a), setting r5 ∈ [0.05a,0.09a] with an increment of Δr5=0.002a. Transmission efficiencies of input logic states of “00”, “01”, “10” and “11” are defined as T1, T2, T3 and T4 and the CRs of input logic states of “01”, “10” and “11” are defined as CR1, CR2 and CR3. Figures 7(a) and 7(b) indicate that, as r5 increases, T1 increases monotonously, and T2 first decreases and then increases and obtains its minimum value T2min=0.0124 at r5=0.052a. As r5 increases, T3 increases monotonously, and T4 first decreases and then increases and obtains its minimum value T4min=0.0159 at r5=0.066a. Moreover, as r5 increases, CR1, CR2 decreases monotonously, and CR3 first increase and then decrease and obtain its maximum values CR3max=10.40 dB at r5=0.066a. Owing to that, CR1, CR2 and CR3 obtain their maximum values at different r5, the arithmetic mean value of these CRs, CR4=(CR1+CR2+CR3)/3, can be chosen to evaluate the “NOR” gate. As r5 increases, CR4 first increases and then decreases and obtains its maximum value CR4max=8.25 dB at r5=0.054a. However, from our further calculation, at this time the output power of input logic states “00” is 0.3451 PI, which is too low and not reach the standard of level “1”, and the second highest value r5=0.056a with 0.3873 PI of input logic states “00” also shows this drawback. We find that the third highest value r5=0.058a with 0.4229 PI of input logic states “00” reaches the standard of level “1”. Consequently, r5=0.058a is chosen as the optimized parameter. In order to calculate the bandwidth of “NOR” gate, we have simulated the dependence of frequency of signals on transmission efficiency and contrast ratio of logic gates. Setting ω ∈ [0.525 (2πc/a), 0.530 (2πc/a)] with an increment of Δω=0.0001 (2πc/a). Transmission efficiencies of input logic states of “00”, “01”, “10” and “11” are defined as T5, T6, T7 and T8, and the CRs of input logic states of “01”, “10” and “11” are defined as CR5, CR6 and CR7 respectively. Figures 7(c) and 7(d) indicate that, as ω increases, T5 first decreases and then increases and obtains its
minimum value T5min=0.0123 at ω=0.5267 (2πc/a), and T6, T7 and T8 exhibit an oscillatory trend. Moreover, as ω increases, CR5, CR6 and CR7 exhibit an oscillatory trend and obtain their maximum values at different ω. If we define bandwidth as frequency range where contrast ratios are larger than 5 dB, it can be noticed that the contrast ratio is larger than 5 dB when ω∈[0.5279 (2πc/a), 0.5281 (2πc/a)], then the bandwidth of “NOR” gate will be 0.0002 (2πc/a). When r5=0.058a, the truth table of “NOR” gate is shown in Table 3. Table 3 Truth table of “NOR” gate Port 1
Port 2
Port 3
PO
0
0
1
0.4229PI
0
1
0
0.0757PI
1
0
0
0.0404 PI
1
1
0
0.0872PI
It can be inferred from Table 3 that, when the input logic states are “00”, “01”, “10” and “11”, the power detected by the monitor at the output port are 0.4229 PI, 0.0757 PI, 0.0404 PI and 0.0872 PI respectively. The Ez field distributions of “NOR” gate, when input logic states are “00”, “01”, “10” and “11”, are shown in Fig. 8.
Fig. 8. The Ez field distributions of input logic states of (a) “00”, (b) “01”, (c) “10” and (d) “11”. The maximum CR of “NOR” gate with optimized structure parameters is 10.19 dB. Owing to that “NOR” gate has a lot of channels, examining its robustness may be complex. In this work, only the condition when the PEC is placed in the output
channel is considered. When the input logic states are “00”, “01”, “10” and “11”, transmission efficiencies of “NOR” gate are 0.4379, 0.0352, 0.0224 and 0.0286 respectively. The results indicate that placing a PEC in the output channel of any input logic states has almost no influence on “NOR” gate. From the above discussion, it can be inferred that, the proposed logic gates is robust when only one input signal is applied. When two input signals are applied, the logic gates are robust in output channel. Consequently, the number of reference signal should be as low as possible when design the logic gates based on interference effect of edge states. Comparison of maximum CR between recent published work and the proposed gates is shown in Table 4. Table 4 Comparison of CR between the proposed gates and recent works Structure
Gate
Maximum CR (dB)
Year
[5 ]
OR
7.27
2016
This work
OR
42.25
/
[4 ]
XOR
24.70
2016
[32]
XOR
15.19
2018
This work
XOR
29.07
/
[32]
NOR
9.02
2018
This work
NOR
10.19
/
Table 4 shows that the CR of the “OR” gate of this work is 42.25 dB, which is far higher than that of the “OR” gate based on common PC [5]. The CR of the “XOR” gate of this work is 29.07 dB, which is higher than that of the “XOR” gate based on self-collimation effect [4] or interference effect in PC [32]. The CR of the “NOR” gate of this work is 10.19 dB, which is higher than that of the “NOR” gate based on common PC [32]. It should be noticed that, in this work, the initial phases of different input signals are regarded as the same values for the convenience of calculation and analysis, which is same as that in the previous works [30-32]. However, the phase of one input signal is always different from that of other input signal in actual condition. To solve this
problem, an extra Al rod with the radius of r6 can be introduced if the phase difference of input signals is already known. Taking the “XOR” gate for instance, an extra Al rod can be introduced into the left input channel of “XOR” gate, as shown in Fig. 9(a), which has the ability to modify the phase of signal from left source [31]. The structure and simulation parameters are consistent with those in previously proposed “XOR” gate except for the new added rod. When the input logics are “01” and “10”, it is obvious that the initial phase of input signals have no influence on the transmission owing to the absence of interference. We have simulated the dependence of r6 on transmission efficiency of logic gate. The transmission efficiencies of input logic states of “01” and “10” are defined as T1 and T2. Simulation results indicate that r6 does not have much influence on T1 and T2 owing to the robustness of the one-way waveguide, as shown in Fig. 9(b). When the input logics are “11”, the initial phase of input signals will influence the transmission owing to interference effect. The condition that initial phase of source at left channel is former than that of source at right channel with the value of α is considered. The transmission efficiencies are defined as T3, T4, T5, T6 and T7 when α=5°, 10°, 15°, 20° and 25°. We have simulated the dependence of r6 on T3, T4, T5, T6 and T7. Simulation results indicate that T3, T4, T5, T6 and T7 obtain
their
minimum
values
T3min=0.2514,
T4min=0.0387,
T5min=0.0003,
T6min=0.0019 and T7min=0.0037 at r6=0, r6=0.2a, r6=0.18a, r6=0.05a and r6=0 respectively, and all the transmission efficiencies are lower than 0.3, which means that the “XOR” gate does not lose its function, and this method can be extended to the other two logic gates. However, if the logic gates are cascaded, the phase problem will be complex, and the solution will be our further work.
Fig. 9. (a) “XOR” gate with an extra Al rod introduced as r6, (b) The relationships of modified “XOR” gate between r6 and transmission efficiency at “01” and “10” case. (c) The relationships of modified “XOR” gate between r6 and transmission efficiency with 0°, 5°, 10°, 15°, 20° and 25° phase difference of the two input signals at “11” case. 4. Conclusion In this work three logic gates based on edge states in GPC are proposed, and these gates are robust when only one input signal is applied. When two input signals are applied, the power can circumvent an obstacle in the output channel. This work is expected to provide guidance to the design of logic gates with high performance. Acknowledgements This work was supported by the National Natural Science Foundation of China (Grant No. 61405058), the Natural Science Foundation of Hunan Province (Grant No. 2017JJ2048), and the Fundamental Research Funds for the Central Universities (Grant No. 531118040112). The authors acknowledge Prof. J. Q. Liu for software
sponsorship.
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http://dx.doi.org/10.1016/j.optlastec.2012.12.030 Highlights · Three logic gates based on the one-way edge states in gyromagnetic photonic crystal are proposed. · The relationships of the structure parameters and performance parameters of the logic gates are analyzed. · The proposed logic gates show high contrast ratios of 42.25 dB, 29.07 dB and 10.19 dB for “OR” gate, “XOR” gate and “NOR” gate. · The robustness of the proposed logic gates is better than that of previous works.
[38]
Author Statement J. Liu conceived the idea and revised the manuscript, and R. Ge designed the structure, run the simulation, processed the data, and finished and revised the manuscript. B. Yan, J. Xie, E. Liu and W. Tan reviewed and commented on the paper. [39]
S0304-8853(18)34166-0 https://doi.org/10.1016/j.jmmm.2019.166367 MAGMA 166367
To appear in:
Journal of Magnetism and Magnetic Materials
Received Date: Revised Date: Accepted Date:
24 December 2018 8 December 2019 27 December 2019
Please cite this article as: R. Ge, B. Yan, J. Xie, E. Liu, W. Tan, J. Liu, Logic gates based on edge states in gyromagnetic photonic crystal, Journal of Magnetism and Magnetic Materials (2019), doi: https://doi.org/10.1016/ j.jmmm.2019.166367
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Logic gates based on edge states in gyromagnetic photonic crystal Rui Ge, Bei Yan, Jianlan Xie, Exian Liu, Wei Tan and Jianjun Liu* Key Laboratory for Micro/Nano Optoelectronic Devices of Ministry of Education & Hunan Provincial Key Laboratory of Low-Dimensional Structural Physics and Devices, School of Physics and Electronics, Hunan University, Changsha 410082, China *
Corresponding author.
E-mail Addresses: [email protected] Abstract Three logic gates based on the one-way edge states in gyromagnetic photonic crystal (GPC) are proposed and analyzed theoretically. The frequency range of the one-way transmission of waveguide is obtained with Finite Element Method (FEM). The relationships between the performance parameters and the structure parameters are investigated. To estimate whether the logic gates are robust, the transmission efficiencies of logic gates with an obstacle in different positions are calculated. Simulation results show that a high contrast ratio (CR) and strong robustness can be obtained. This work is expected to provide guidance to the design of logic gate with high performance. Keywords: gyromagnetic photonic crystal, logic gate, contrast ratio 1. Introduction Logic gates based on photonic crystal (PC) have shown many advantages including simple structure, strong confinement of light and easiness of integrating on chip [1-3]. However, traditional PC-based logic gates [4, 5] have shown a lot of weaknesses such as unwanted strong backward light propagation effect and weak robustness [1, 6], which may degrade their performance. Obviously, the strong backward light propagation is reflected in the weak isolating effect of the different input channels of
the logic gate [5]. The weak robustness is reflected in the low tolerance of fabrication errors, such as, the deviations of the structure parameters or the positions of the rods [6] in the PC will affect the performance of the logic gate. According to the previous works, the solutions of these weaknesses include improving the fabrication process of the logic gates [7] or introducing one-way edge state [8]. However, fabrication error is unavoidable whatever fabrication process is improved [9]. Therefore, the key method is to introduce the one-way edge state into the logic gate. Theories and experiments verified that integer quantum Hall effect can be extended to photonic field, which makes the one-way edge state become the research hotspot [10-13]. The principle of creating the one-way edge state is that external magnetic field can break up the time-reversal symmetry and lift the degeneracies and create a gap which makes the chern number of other gaps below this one become non-zero [10-15]. Beam splitter [16], add-drop filter [9, 17-19] and circulator [20] based on the one-way edge state in GPC have been proposed in recent years. Traditional investigations of GPC put emphasis on the transmission properties of only one input signal. However, investigation of GPC with more than one input signal has not been reported yet. Definitely, study of GPC with more than one input signal is of great importance because devices with more than one input signal are vital components in signal processor devices [21]. Moreover, comparing with traditional nonreciprocal transmission phenomenon [22, 23], the one-way transmission based on edge state has shown many advantages including circumventing the obstacle with low loss and have no backscattering which results in that the forward transmission efficiency is 50 dB higher than the backward one [11]. These merits enable the GPC to be the best candidate structure for the high-quality logic gate. In this work, three logic gates based on the edge states in GPC are proposed. Logic operations are achieved by interference effect. The relationships between the structure parameters and the performance parameters are analyzed. The optimum logic gates have a high CR and strong robustness. 2. Modeling and theory
The logic gates are composed of waveguide with the applied external magnetic field which consists of the PC and the GPC in which the magnetic field is in the out-of-plane direction. The structure of waveguide is shown in Fig. 1(a). The frequency ranges of the one-way-transmission of supercells of the waveguide must be calculated before designing the logic gates.
Fig. 1. (a) Structure of waveguide consisting of PC and GPC, the structure in red dash line represents the calculated supercell. (b) The relationship between the frequencies and the CR of waveguide consisting of PC and GPC. (c) Band gap diagram of the supercell. The structures are constructed by rods in air background. The PC is composed of alumina (Al) rods which are arranged in the 45° tilted square lattice with the lattice constant LAl=a/ 2 . The radius and dielectric constant of Al rods are r1=0.106a and ε1=10. The GPC is composed of yttrium-iron-garnet (YIG) rods which are arranged in the square lattice with lattice constant LYIG=a. The radius and dielectric constant of YIG rods are r2=0.11a and ε2=15-0.003j [11, 19]. When the external magnetic field is
applied in ±z direction (out-of-plane direction or in-plane direction), the permeability of YIG rods becomes the tensor [16]
0 ik 0
ik 0 0 0 1
(1)
where =1+m0 / (0 2 2 ) , k =m / (0 2 2 ) , μ0 is the permeability of vacuum, 0 =2 H 0 is the precession frequency, and =2.8 106 rad s -1G -1 is the gyromagnetic ratio,
H0
is the magnetic field,
m =2 (4 ms )
is the
characteristic frequency and 4 ms =1780 G is the saturation magnetization [19, 24]. When external magnetic field intensity equals to 1600 G and the frequency of incident waves is 4.28 GHz, the corresponding parameters are ω=26.89 GHz, μ=14, k=12.4 [11, 16]. The external magnetic field is always applied in +z direction in our research. In general, the YIG rod is commercially available [25], and the detailed fabrication procedure can be referred to Ref. [26]. The one-way properties of the waveguides and performance of the logic gates is analyzed with the FEM-software COMSOL Multiphysics. Perfectly matched layers are set to absorb energies [27-29]. All input signals in the logic gates are TM polarized plane waves. The relationships between the frequency and the CR of the forward and backward transmission efficiencies of the waveguide, and the band gap diagram of supercell of structure consisting of PC and GPC, are shown in Fig. 1(b)-1(c). The frequency, where the CR is larger than 45 dB, is defined as one-way transmission frequency. It can be inferred from Figs. 2 (a) and 2 (b) that one-way transmission frequency of waveguide composed of PC and GPC ranges from 0.5256 (2πc/a) to 0.5768 (2πc/a). If the frequencies of source are in the one-way frequency range, the signal can propagate in only one direction. The schematics of the proposed “OR”, “XOR” and “NOR” gates are illustrated in Fig. 2 and the structure parameters including the radius or the material of rods and the lattice constant are the same with those of structures in Fig. 1(a) except for the
radius of defect rods.
Fig. 2. The schematics of the proposed (a) “OR” gate, (b) “XOR” gate and (c) “NOR” gate, (d) Potential characterization model of “XOR” gate. To create phase difference of the signals in PC, the common methods includes constructing a cavity [30], introducing extra rods with much smaller radius [31] or increasing the number of rods in one input channel to create signal path difference
[32]. Increasing the number of rods has advantages such as simple of operating and easiness of obtaining a large bandwidth. However, the number of rods must be integer, which results in the weak adjustability. Introducing extra rods with small radius brings a large bandwidth and shows strong adjustability but have a low CR [31]. Although constructing a cavity shows shortcoming like having a low bandwidth, it shows strong adjustability and a high CR [30]. In this work, cavity [33, 34] is constructed to design “OR” or “XOR” gate with high performance. The proposed “OR” gate is shown in Fig. 2(a). Five Al rods are introduced into the center area of “OR” gate to form a cavity, where the radius of rods at top and right is set as r1 which is the same with that in Fig. 1(a) and the radius of rods at center and bottom and left is set as r3 (variable). Two sources with the same amplitudes and phases are placed near Ports 1 and 2 separately to launch input signals with the power of PI and the frequency of 0.528 (2πc/a), and Port 3 is set as output port. The monitor is placed near Port3 and the output power detected is defined as PO. To realize the logic operation of “1XOR1=0” by the destructive interference, the phases of two input signals must have a difference of π in the output port. The proposed “XOR” gate is shown in Fig. 2(b). The settings of ports, sources and monitor are the same with those in “OR” gate. The parameters of rods are also the same with those in “OR” gate except the defect rods. Four Al rods are introduced into the center area of “XOR” gate to form a cavity, where the radius of rods at top and right is set as r1 which is the same with that in Fig. 1(a) and the radius of rods at bottom and left is set as r4 (variable). To realize the logical operation of “0NOR0=1”, the reference source must be placed. Meanwhile, more waveguides must be constructed owing to the existence of three sources. Obviously, these waveguide channels must have large bandwidths to ensure the signals can flow to the output port. Consequently, rods with small radius are introduced to GPC to design “NOR” gate with high performance. The proposed “NOR” gate is shown in Fig. 2(c). The settings of ports, input sources and monitor are the same with those in “OR” gate. The parameters of rods are also the same with those in “OR” gate except the defect rods. The reference source whose amplitude,
phase and polarization are the same with other input sources is placed near Port 4. Six Al rods with radius of r5 are introduced into the logic gate. The potential characterization model of “XOR” gate is shown in Fig. 2(d). To check the performance of proposed logic gates, we may need a vector network analysis with two antennas, and the whole structure should be sandwiched by two copper plates. The detailed potential procedures of experiment can be referred to Ref. [12]. In this work, the input logic states are “00” when Port 1 and Port 2 don’t have input signals, and the input logic states are “01” when Port 1 doesn’t have input signal but Port 2 have input signal. The input logic states are “10” when Port 2 doesn’t have input signal but Port 1 has input signal. When Port 1 and Port 2 both have input signals, the input logic states are “11”. When the two input signals exist in the logic gate and reference source is not excited (“OR” gate and “XOR” gate), the transmission efficiency is defined as T
Pα Pβ Pγ
(2)
Where Pα is the power detected by the monitor at the output port, and Pβ and Pγ are the powers of different input sources. When the three input signals exist in the logic gate (“NOR” gate), the transmission efficiency is defined as T
Pα Pβ Pγ+Pδ
(3)
Where Pα is the power detected by the monitor at the output port, and Pβ, Pγ and Pδ are the powers of different sources. In Eqs. (2) and (3), the output logic state “1” is defined when the transmission efficiency is larger than 0.4, and the output logic state “0” is defined when transmission efficiency is lower than 0.3 [32]. CR is another important performance parameter to evaluate the logic gate. Obviously, a logic gate with a high CR will bring convenience to the detection of signals. In “OR” gate, the CR is defined as [5, 35]
CR 10 log
Pa Pb
(4)
Where Pa is the power detected at one input port where no source is placed when another input port placed source, and Pb is the power detected by the monitor in output port when only one input port launches signal. In “XOR” and “NOR” gate, the CR is defined as [32] CR 10 log
P2 P1
(5)
Where P1 or P2 represent the power detected by the monitor at the output port when the output logic state is “0” or “1”. For “XOR” gate, the output logic state is “1” when the input logic states are “01” or “10”, and the output logic state is “0” when the input logic states are “00” or “11”. Obviously, the CR has no sense when the input logic states are “00”. Consequently, CR may have two values: CR1 or CR2. Similarly, for “NOR” gate, the output logic state is “1” when input logic states are “00”, and the output logic state is “0” when the input logic states are “01”, “10” or “11”. Consequently, CR has three values: CR1, CR2 or CR3. 3.Result and discussion 3.1 Performance of “OR” gate When the frequency of input signals is chosen as ω=0.528 (2πc/a) and r3=0.235a, the truth table of “OR” gate is shown in Table 1. Table 1 Truth table of “OR” gate Port 1
Port 2
Port 3
PO
0
0
0
0
0
1
1
0.4086 PI
1
0
1
0.4643 PI
1
1
1
1.0402 PI
It can be inferred from Table 1 that when the input logic states are “00”, “01”, “10” and “11”, the power detected by the monitor at the output port are 0, 0.4086 PI, 0.4643 PI and 1.0402 PI. The Ez field distributions of “OR” gate when input logic states are “01”, “10” and “11” are shown in Fig. 3.
Fig. 3. The Ez field distributions of input logic states of (a) “01”, (b) “10” and (c) “11”. It can be inferred in Figs. 3(a) and 3(b) that the “OR” gate shows excellent isolation effect for the signals from the different input channel. To obtain the CR of “OR” gate, an extra monitor is placed near Port 2 (or Port1) and the input logic states are set as “10” (or “01”), the power detected by the extra monitor is 2.767×10-5 PI (or 3.3437×10-5 PI), resulting in a CR of 42.25 dB (or 40.87 dB). To examine whether the “OR” gate is robust, the transmission efficiency of “OR” gate in different conditions (with obstacle and without obstacle) should be obtained. The obstacle is chosen as the Perfect Electric Conductor (PEC) with the length of a in the simulation. The PEC is placed at the left input channel and the output channel respectively, if input logic states are “10”, then the transmission efficiency of “OR” gate are 0.5838 and 0.4554 respectively with the Poynting vector shown in Figs. 4(a) and 4(b). If input logic states are “11”, then the transmission efficiency of “OR” gate are 0.0973 and 0.5102 respectively with the Poynting vector shown in Figs. 4(c) and 4(d). It can be seen that there is no energy in output channel when PEC is placed at the left channel with input logic “11”.
Fig. 4. Poynting vector diagrams of input logic states “10” when (a) PEC is in the left input channel and (b) PEC is in the output channel. Poynting vector diagrams of input logic states “11” when (c) PEC is in the left input channel and (d) PEC is in the output channel. The above results indicates that, placing a PEC in the input channel, whatever the input logic states are, doesn’t influence the performance of “OR” gate. When the input logic states are “01” or “10”, placing a PEC in the input channel doesn’t influence the performance of “OR” gate. However, when the input logic states are “11”, placing a PEC in the input channel will result in the invalidation of “OR” gate. This phenomenon can be explained as, one-way edge state can circumvent the PEC with no loss, and when the input logic states are “11”, placing a PEC in the input or the output channel in “OR” gate will create more signal path for the transmitted signals and therefore changes their phase at the output port [11]. Eventually, the
interference states of the input signals are changed and the “OR” gate is invalid. When the input logic states are any values, placing a PEC in output channel will change the phases of the transmitted signals at the output port for the same degree and the “OR” gate can normally work. The “OR” gate based on one-way edge state is more robust than those based on the common PC. 3.2 Performance of “XOR” gate To design the “XOR” gate with high performance, the structure parameters of the logic gate must be optimized. The relationships between the performance parameters and the radius of defect rods or the frequency of the input signals are shown in Fig. 5.
Fig. 5. The relationships of “XOR” gate between r4 and (a) transmission efficiency or (b) CR. Relationships of “XOR” gate between ω and (c) transmission efficiency or (d) CR. The frequency of input signals is chosen as ω=0.528 (2πc/a), setting r4 ∈ [0.20a,0.24a] with an increment of Δr4=0.002a. Transmission efficiencies of input logic states of “01”, “10” and “11” are defined as T1, T2 and T3 and the CRs of input logic states of “01” and “10” are defined as CR1 and CR2. Figures 5(a) and 5(b) indicates that, as r4 increases, T1 first decreases and then increases and obtains its minimum value T1min=0.2352 at r4=0.206a. Meanwhile, as r4 increases, T2 first increases and then decreases and obtains its maximum value T2max=0.6506 at r3=0.206a. As r4 increases, T3 first decreases and then increases and obtains its
minimum value T3min=0.00028 at r3=0.214a. Moreover, as r4 increases, CR1 and CR2 both first increases and then decreases and obtain their maximum values CR1max=28.78 dB and CR2max=29.07 dB at r4=0.214a. Consequently, r4=0.214a is chosen as the optimized parameter. In order to calculate the bandwidth of “XOR” gate, we have simulated the dependence of frequency of signals on transmission efficiency and contrast ratio of logic gates. Setting ω ∈ [0.525 (2πc/a), 0.535 (2πc/a)] with an increment of Δω=0.0001 (2πc/a). Transmission efficiencies of input logic states of “01”, “10” and “11” are defined as T4, T5 and T6 and the CRs of input logic states of “01” and “10” are defined as CR3 and CR4. Figures 5(c) and 5(d) indicate that, as ω increases, T4 first decreases and then increases and obtains its minimum value T4min=0.4199 at ω=0.5266 (2πc/a), and T5 first increases and then decreases and obtains its maximum value T5max=0.4613 at ω=0.5286 (2πc/a), and T6 first decreases and then increases and obtains its minimum value T6min=0.00022 at ω=0.5288 (2πc/a). Moreover, as ω increases, CR3 and CR4 both first increase and then decrease and obtain their maximum values CR3max=29.98 dB and CR4max=30.23 dB at ω=0.5288 (2πc/a). The bandwidth of “XOR” gate is defined as frequency range where contrast ratios are larger than 15 dB [36, 37]. It can be noticed that the contrast ratio is larger than 15 dB when ω∈[0.5252 (2πc/a), 0.5327 (2πc/a)]. Consequently, the bandwidth of “XOR” gate is 0.0075 (2πc/a). When r4=0.214a, the truth table of “XOR” gate is shown in Table 2. Table 2 Truth table of “XOR” gate Port 1
Port 2
Port 3
PO
0
0
0
0
0
1
1
0.4283 PI
1
0
1
0.4582 PI
1
1
0
0.00056 PI
It can be inferred from Table 2 that, when the input logic states are “00”, “01”, “10” and “11”, the powers detected by the monitor at the output port are 0, 0.4283 PI, 0.4582 PI and 0.00056 PI respectively. The Ez field distributions of “XOR” gate when
input logic states are “01”, “10” and “11” are shown in Fig. 6.
Fig. 6. The Ez field distributions of input logic states of (a) “01”, (b) “10” and (c) “11”. The maximum CR of “XOR” gate with optimized structure parameters is 29.07 dB. To examine whether the “XOR” gate is robust, a PEC of L=a is firstly placed in the output channel, when input logic states are “01”, “10” and “11”, transmission efficiencies detected by the monitor at the output port are 0.4353, 0.4556 and 0.0003 respectively. Then a PEC of L=a is placed in the left input channel, when input logic states are “01”, “10” and “11”, transmission efficiencies detected by the monitor at the output port are 0.5237, 0.3861 and 0.4079. The results indicate that only when the input logic states are “11” and the PEC is placed in the input channel, the “XOR” gate is invalid. 3.3 Performance of “NOR” gate To design the “NOR” gate with high performance, the structure parameters of the logic gate must be optimized. The relationships between the performance parameters and the radius of defect rods or the frequency of the input signals are shown in Fig. 7.
Fig. 7. The relationships of “NOR” gate between r5 and (a) transmission efficiency or (b) CR. Relationships of “NOR” gate between ω and (c) transmission efficiency or (d) CR. The frequency of input signals is chosen as ω=0.528 (2πc/a), setting r5 ∈ [0.05a,0.09a] with an increment of Δr5=0.002a. Transmission efficiencies of input logic states of “00”, “01”, “10” and “11” are defined as T1, T2, T3 and T4 and the CRs of input logic states of “01”, “10” and “11” are defined as CR1, CR2 and CR3. Figures 7(a) and 7(b) indicate that, as r5 increases, T1 increases monotonously, and T2 first decreases and then increases and obtains its minimum value T2min=0.0124 at r5=0.052a. As r5 increases, T3 increases monotonously, and T4 first decreases and then increases and obtains its minimum value T4min=0.0159 at r5=0.066a. Moreover, as r5 increases, CR1, CR2 decreases monotonously, and CR3 first increase and then decrease and obtain its maximum values CR3max=10.40 dB at r5=0.066a. Owing to that, CR1, CR2 and CR3 obtain their maximum values at different r5, the arithmetic mean value of these CRs, CR4=(CR1+CR2+CR3)/3, can be chosen to evaluate the “NOR” gate. As r5 increases, CR4 first increases and then decreases and obtains its maximum value CR4max=8.25 dB at r5=0.054a. However, from our further calculation, at this time the output power of input logic states “00” is 0.3451 PI, which is too low and not reach the standard of level “1”, and the second highest value r5=0.056a with 0.3873 PI of input logic states “00” also shows this drawback. We find that the third highest value r5=0.058a with 0.4229 PI of input logic states “00” reaches the standard of level “1”. Consequently, r5=0.058a is chosen as the optimized parameter. In order to calculate the bandwidth of “NOR” gate, we have simulated the dependence of frequency of signals on transmission efficiency and contrast ratio of logic gates. Setting ω ∈ [0.525 (2πc/a), 0.530 (2πc/a)] with an increment of Δω=0.0001 (2πc/a). Transmission efficiencies of input logic states of “00”, “01”, “10” and “11” are defined as T5, T6, T7 and T8, and the CRs of input logic states of “01”, “10” and “11” are defined as CR5, CR6 and CR7 respectively. Figures 7(c) and 7(d) indicate that, as ω increases, T5 first decreases and then increases and obtains its
minimum value T5min=0.0123 at ω=0.5267 (2πc/a), and T6, T7 and T8 exhibit an oscillatory trend. Moreover, as ω increases, CR5, CR6 and CR7 exhibit an oscillatory trend and obtain their maximum values at different ω. If we define bandwidth as frequency range where contrast ratios are larger than 5 dB, it can be noticed that the contrast ratio is larger than 5 dB when ω∈[0.5279 (2πc/a), 0.5281 (2πc/a)], then the bandwidth of “NOR” gate will be 0.0002 (2πc/a). When r5=0.058a, the truth table of “NOR” gate is shown in Table 3. Table 3 Truth table of “NOR” gate Port 1
Port 2
Port 3
PO
0
0
1
0.4229PI
0
1
0
0.0757PI
1
0
0
0.0404 PI
1
1
0
0.0872PI
It can be inferred from Table 3 that, when the input logic states are “00”, “01”, “10” and “11”, the power detected by the monitor at the output port are 0.4229 PI, 0.0757 PI, 0.0404 PI and 0.0872 PI respectively. The Ez field distributions of “NOR” gate, when input logic states are “00”, “01”, “10” and “11”, are shown in Fig. 8.
Fig. 8. The Ez field distributions of input logic states of (a) “00”, (b) “01”, (c) “10” and (d) “11”. The maximum CR of “NOR” gate with optimized structure parameters is 10.19 dB. Owing to that “NOR” gate has a lot of channels, examining its robustness may be complex. In this work, only the condition when the PEC is placed in the output
channel is considered. When the input logic states are “00”, “01”, “10” and “11”, transmission efficiencies of “NOR” gate are 0.4379, 0.0352, 0.0224 and 0.0286 respectively. The results indicate that placing a PEC in the output channel of any input logic states has almost no influence on “NOR” gate. From the above discussion, it can be inferred that, the proposed logic gates is robust when only one input signal is applied. When two input signals are applied, the logic gates are robust in output channel. Consequently, the number of reference signal should be as low as possible when design the logic gates based on interference effect of edge states. Comparison of maximum CR between recent published work and the proposed gates is shown in Table 4. Table 4 Comparison of CR between the proposed gates and recent works Structure
Gate
Maximum CR (dB)
Year
[5 ]
OR
7.27
2016
This work
OR
42.25
/
[4 ]
XOR
24.70
2016
[32]
XOR
15.19
2018
This work
XOR
29.07
/
[32]
NOR
9.02
2018
This work
NOR
10.19
/
Table 4 shows that the CR of the “OR” gate of this work is 42.25 dB, which is far higher than that of the “OR” gate based on common PC [5]. The CR of the “XOR” gate of this work is 29.07 dB, which is higher than that of the “XOR” gate based on self-collimation effect [4] or interference effect in PC [32]. The CR of the “NOR” gate of this work is 10.19 dB, which is higher than that of the “NOR” gate based on common PC [32]. It should be noticed that, in this work, the initial phases of different input signals are regarded as the same values for the convenience of calculation and analysis, which is same as that in the previous works [30-32]. However, the phase of one input signal is always different from that of other input signal in actual condition. To solve this
problem, an extra Al rod with the radius of r6 can be introduced if the phase difference of input signals is already known. Taking the “XOR” gate for instance, an extra Al rod can be introduced into the left input channel of “XOR” gate, as shown in Fig. 9(a), which has the ability to modify the phase of signal from left source [31]. The structure and simulation parameters are consistent with those in previously proposed “XOR” gate except for the new added rod. When the input logics are “01” and “10”, it is obvious that the initial phase of input signals have no influence on the transmission owing to the absence of interference. We have simulated the dependence of r6 on transmission efficiency of logic gate. The transmission efficiencies of input logic states of “01” and “10” are defined as T1 and T2. Simulation results indicate that r6 does not have much influence on T1 and T2 owing to the robustness of the one-way waveguide, as shown in Fig. 9(b). When the input logics are “11”, the initial phase of input signals will influence the transmission owing to interference effect. The condition that initial phase of source at left channel is former than that of source at right channel with the value of α is considered. The transmission efficiencies are defined as T3, T4, T5, T6 and T7 when α=5°, 10°, 15°, 20° and 25°. We have simulated the dependence of r6 on T3, T4, T5, T6 and T7. Simulation results indicate that T3, T4, T5, T6 and T7 obtain
their
minimum
values
T3min=0.2514,
T4min=0.0387,
T5min=0.0003,
T6min=0.0019 and T7min=0.0037 at r6=0, r6=0.2a, r6=0.18a, r6=0.05a and r6=0 respectively, and all the transmission efficiencies are lower than 0.3, which means that the “XOR” gate does not lose its function, and this method can be extended to the other two logic gates. However, if the logic gates are cascaded, the phase problem will be complex, and the solution will be our further work.
Fig. 9. (a) “XOR” gate with an extra Al rod introduced as r6, (b) The relationships of modified “XOR” gate between r6 and transmission efficiency at “01” and “10” case. (c) The relationships of modified “XOR” gate between r6 and transmission efficiency with 0°, 5°, 10°, 15°, 20° and 25° phase difference of the two input signals at “11” case. 4. Conclusion In this work three logic gates based on edge states in GPC are proposed, and these gates are robust when only one input signal is applied. When two input signals are applied, the power can circumvent an obstacle in the output channel. This work is expected to provide guidance to the design of logic gates with high performance. Acknowledgements This work was supported by the National Natural Science Foundation of China (Grant No. 61405058), the Natural Science Foundation of Hunan Province (Grant No. 2017JJ2048), and the Fundamental Research Funds for the Central Universities (Grant No. 531118040112). The authors acknowledge Prof. J. Q. Liu for software
sponsorship.
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http://dx.doi.org/10.1016/j.optlastec.2012.12.030 Highlights · Three logic gates based on the one-way edge states in gyromagnetic photonic crystal are proposed. · The relationships of the structure parameters and performance parameters of the logic gates are analyzed. · The proposed logic gates show high contrast ratios of 42.25 dB, 29.07 dB and 10.19 dB for “OR” gate, “XOR” gate and “NOR” gate. · The robustness of the proposed logic gates is better than that of previous works.
[38]
Author Statement J. Liu conceived the idea and revised the manuscript, and R. Ge designed the structure, run the simulation, processed the data, and finished and revised the manuscript. B. Yan, J. Xie, E. Liu and W. Tan reviewed and commented on the paper. [39]