- Email: [email protected]
Low swing differential logic for mixed signal applications
ARTICLE IN PRESS
Nuclear Instruments and Methods in Physics Research A 518 (2004) 511–514
Low swing differential logic for mixed signal applications P. Fischera,*, E. Kraftb a
Institut fur . Technische Informatik, Universitat . Mannheim, Germany b Physikalisches Institut, Universitat . Bonn, Germany
Abstract Low swing differential logic operated at a constant bias current is a promising approach to reduce the switching noise in sensitive mixed mode circuits. Most differential logic families do not allow a significant change in bias current between cells so that it is difficult to optimize the power consumption for a required speed. A nonlinear load circuit for differential current-steering logic consisting of a current source in parallel with a diode connected FET is therefore proposed. The logic levels can be easily adjusted with an external supply voltage so that the circuit design is significantly simplified. As an example application a counter for the use in pixel readout chips is presented. The layout area using radiation hard design rules is not significantly larger than CMOS. The logic can be operated at very low power. r 2003 Elsevier B.V. All rights reserved. PACS: 07.50.Ek; 07.50.Qx; 84.30.Sk Keywords: Differential logic; Sensor readout; Mixed signal electronics; Pixel readout chips
1. Introduction One of the challenges in mixed signal designs is the reduction of crosstalk between digital and sensitive analog sections. The usual precautions (guard structures, separate supplies, shielding, a physical separation of blocks) cannot always be applied or they cause significant complications on the system level. Pixel readout chips for instance have several thousand pixel cells which each contain a low noise charge sensitive amplifier and fast ð> 10 MHzÞ digital data processing electronics on an area of typically 100 mm 100 mm: The cells are arranged in a seamless checkerboard pattern *Corresponding author. Tel.: +49-621-181-2735; fax: +49621-181-2734. E-mail address: peter.fi[email protected] (P. Fischer).
on the chip so that analog and digital parts are densely interwoven. Low swing differential logic operated at constant current can address the crosstalk problem. Fig. 1 shows the general topology of a differential gate. A bias current I0 is steered with a differential switching network into load circuits which transform the currents into voltages. The output voltage levels must be suited to drive other gates of the same type. The benefits of this approach are small crosstalk due to small swings, cancellation of injections due to the differential nature and the absence of voltage spikes on the supply voltage (even during signal transients!). Several drawbacks of constant current, low swing differential logic are often stressed. Some of them are briefly discussed here. The power consumption is constant also during switching and should therefore be compared to the
0168-9002/$ - see front matter r 2003 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2003.11.072
ARTICLE IN PRESS P. Fischer, E. Kraft / Nuclear Instruments and Methods in Physics Research A 518 (2004) 511–514
I0
in -
in +
out +
out load circuits
Fig. 1. Inverter implemented in differential logic. The bias current I0 is steered to one of the load circuits where it is converted to a voltage.
dynamic consumption of CMOS circuits. At high speed, the significantly smaller signal swings require less current per transition. At low speed, the DC consumption of differential logic can be made very small ðo mAÞ so that it may not pose a problem. Furthermore, the input capacitance of differential logic is significantly smaller than in CMOS (in particular in radiation tolerant designs) so that less current is needed. Differential gates require more transistors. A gate with N inputs requires 4 NMOS þ ð1 þ 2NÞ PMOS devices for the proposed logic, as compared to N NMOS þ N PMOS in CMOS. Complex logic functions can, however, often be implemented directly in differential logic due to the availability of the inverse signal. As an example, a static latch with a two input multiplexer requires at least 7 þ 7 devices in CMOS and 4 þ 11 devices in the proposed logic. The layout area of gates is often dominated by one type of devices (enclosed NMOS devices in radiation tolerant design, PMOS in standard CMOS). A constant number of the ‘large’ devices, independent of the complexity of the gate, can be advantageous. A PMOS switch network leads to small layouts for radiation tolerant design with large NMOS devices.
2. Proposed load circuit
transistor sizing [1] or a regulation [2] and make it difficult to operate the gates with individual bias currents in order to save current where possible. An ‘ideal’ load circuit should deliver a constant current of I0 =2 so that the current available for charging up/down a load capacitance is 7I0 =2: This leads to equal slew rates for both edges. The speed of the circuit can be increased by raising I0 as opposed to a purely resistive load where the signal swing increases with the bias current so that the RC time constant remains unchanged. In order to obtain well defined voltage levels, the ‘ideal’ load must sink a very high current as soon as the output reaches the high level. The current must fall to zero below the low voltage level.
I0 a 1/ I 2 0
vss = vlow
vhigh
in b bias vss
gnd
Fig. 2. (a) Characteristic and (b) implementation of the proposed load circuit. 3
2
ILoad [µA]
512
1
0 0.0
0.1
0.2
0.3
0.4
0.5
ULoad [V]
Several load circuits for differential logic have been proposed. They require, however, careful
Fig. 3. Measured characteristic of the proposed load circuit for various bias conditions and for vss ¼ 0 and 0:2 V:
ARTICLE IN PRESS P. Fischer, E. Kraft / Nuclear Instruments and Methods in Physics Research A 518 (2004) 511–514
513
This step-wise characteristic can be approximated by a parallel connection of an NMOS operated in saturation as a current source and an element with a very steep characteristic. A second, diode connected NMOS is used in the proposed load circuit Fig. 2(b). Other implementations using diodes could also be used. The turn-on voltage and the capacitance of the element and the compatibility with the technology used must be considered. The expected characteristic shown in Fig. 2(a) illustrates that the low differential voltage level is well defined by the auxiliary supply voltage vss and the high level is reasonably well fixed by the turning on of the NMOS diode. Some important characteristics of this load are: *
*
*
The voltage levels are relatively insensitive to the bias current. The current can therefore be adapted in every gate to the load capacitance and the speed requirements. The sizing of the two transistors is not critical. In particular, the choice does not depend much on the bias current. The voltage swing can be adjusted very easily by changing vss. It can therefore be set to the minimum value sufficient to switch the differential tree. For devices operated in weak inversion, some 100 mV are sufficient.
3. Prototype results A prototype chip has been designed in a 0:25 mm CMOS technology with threshold voltages of E500 mV for NMOS and PMOS devices. Enclosed NMOS devices and guard rings have been used in the layout for radiation hardness [3,4]. The transistor sizes and bias conditions have been optimized for a moderate speed of several 10 MHz: This allows a supply voltage of only 1:2 V and leads to typical bias currents in the microampere range per gate so that most devices operate in weak inversion. A typical value for vss is 0:2 V at a high level of E400 mV so that the voltage swings are only E200 mV: Fig. 3 shows the measured load characteristic for vss ¼ 0 V and vss ¼ 0:2 V for various bias settings. Several test circuits have been studied. An inverter in an inverter chain has a power-delay
Fig. 4. Layout of a 16-bit static ripple counter with a parallel bus readout. Annular NMOS devices and guard rings have been used in a 0:25 mm technology. The size is E50 mm 50 mm:
product of below 3 mW ns: A shift register with parallel load input runs at E80 MHz if operated at 3 mW per stage. A simple 8-bit synchronous counter consumes 35 mW if operated at 8 MHz: A 16-bit static ripple counter can be operated with less bias current in the higher bits because they are clocked at lower speed. This power-efficient design leads to a consumption of only E6:5 mW for a maximum clocking frequency of 20 MHz: The layout of the full counter including a bus readout is shown in Fig. 4. It occupies an area of E50 mm 50 mm:
4. Summary A simple load circuit for differential currentsteering logic has been proposed. The logic swing is nearly independent of the bias current so that the gates can be operated at different power consumption depending on their capacitive load and the speed required. The layout area when using radiation tolerant design rules is comparable to CMOS.
ARTICLE IN PRESS 514
P. Fischer, E. Kraft / Nuclear Instruments and Methods in Physics Research A 518 (2004) 511–514
References [1] S.R. Maskai, et al., IEEE J. Solid State Circuits 27 (8) (1992) 1157. [2] J.G. Maneatis, et al., IEEE J. Solid State Circuits 28 (12) (1993) 1273.
[3] D.R. Alexander, et al., IEEE NSREC Short Course, Vol. 1, 1996. [4] W. Snoeys, et al., Nucl. Instr. and Meth. A 439 (2000) 349.
Nuclear Instruments and Methods in Physics Research A 518 (2004) 511–514
Low swing differential logic for mixed signal applications P. Fischera,*, E. Kraftb a
Institut fur . Technische Informatik, Universitat . Mannheim, Germany b Physikalisches Institut, Universitat . Bonn, Germany
Abstract Low swing differential logic operated at a constant bias current is a promising approach to reduce the switching noise in sensitive mixed mode circuits. Most differential logic families do not allow a significant change in bias current between cells so that it is difficult to optimize the power consumption for a required speed. A nonlinear load circuit for differential current-steering logic consisting of a current source in parallel with a diode connected FET is therefore proposed. The logic levels can be easily adjusted with an external supply voltage so that the circuit design is significantly simplified. As an example application a counter for the use in pixel readout chips is presented. The layout area using radiation hard design rules is not significantly larger than CMOS. The logic can be operated at very low power. r 2003 Elsevier B.V. All rights reserved. PACS: 07.50.Ek; 07.50.Qx; 84.30.Sk Keywords: Differential logic; Sensor readout; Mixed signal electronics; Pixel readout chips
1. Introduction One of the challenges in mixed signal designs is the reduction of crosstalk between digital and sensitive analog sections. The usual precautions (guard structures, separate supplies, shielding, a physical separation of blocks) cannot always be applied or they cause significant complications on the system level. Pixel readout chips for instance have several thousand pixel cells which each contain a low noise charge sensitive amplifier and fast ð> 10 MHzÞ digital data processing electronics on an area of typically 100 mm 100 mm: The cells are arranged in a seamless checkerboard pattern *Corresponding author. Tel.: +49-621-181-2735; fax: +49621-181-2734. E-mail address: peter.fi[email protected] (P. Fischer).
on the chip so that analog and digital parts are densely interwoven. Low swing differential logic operated at constant current can address the crosstalk problem. Fig. 1 shows the general topology of a differential gate. A bias current I0 is steered with a differential switching network into load circuits which transform the currents into voltages. The output voltage levels must be suited to drive other gates of the same type. The benefits of this approach are small crosstalk due to small swings, cancellation of injections due to the differential nature and the absence of voltage spikes on the supply voltage (even during signal transients!). Several drawbacks of constant current, low swing differential logic are often stressed. Some of them are briefly discussed here. The power consumption is constant also during switching and should therefore be compared to the
0168-9002/$ - see front matter r 2003 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2003.11.072
ARTICLE IN PRESS P. Fischer, E. Kraft / Nuclear Instruments and Methods in Physics Research A 518 (2004) 511–514
I0
in -
in +
out +
out load circuits
Fig. 1. Inverter implemented in differential logic. The bias current I0 is steered to one of the load circuits where it is converted to a voltage.
dynamic consumption of CMOS circuits. At high speed, the significantly smaller signal swings require less current per transition. At low speed, the DC consumption of differential logic can be made very small ðo mAÞ so that it may not pose a problem. Furthermore, the input capacitance of differential logic is significantly smaller than in CMOS (in particular in radiation tolerant designs) so that less current is needed. Differential gates require more transistors. A gate with N inputs requires 4 NMOS þ ð1 þ 2NÞ PMOS devices for the proposed logic, as compared to N NMOS þ N PMOS in CMOS. Complex logic functions can, however, often be implemented directly in differential logic due to the availability of the inverse signal. As an example, a static latch with a two input multiplexer requires at least 7 þ 7 devices in CMOS and 4 þ 11 devices in the proposed logic. The layout area of gates is often dominated by one type of devices (enclosed NMOS devices in radiation tolerant design, PMOS in standard CMOS). A constant number of the ‘large’ devices, independent of the complexity of the gate, can be advantageous. A PMOS switch network leads to small layouts for radiation tolerant design with large NMOS devices.
2. Proposed load circuit
transistor sizing [1] or a regulation [2] and make it difficult to operate the gates with individual bias currents in order to save current where possible. An ‘ideal’ load circuit should deliver a constant current of I0 =2 so that the current available for charging up/down a load capacitance is 7I0 =2: This leads to equal slew rates for both edges. The speed of the circuit can be increased by raising I0 as opposed to a purely resistive load where the signal swing increases with the bias current so that the RC time constant remains unchanged. In order to obtain well defined voltage levels, the ‘ideal’ load must sink a very high current as soon as the output reaches the high level. The current must fall to zero below the low voltage level.
I0 a 1/ I 2 0
vss = vlow
vhigh
in b bias vss
gnd
Fig. 2. (a) Characteristic and (b) implementation of the proposed load circuit. 3
2
ILoad [µA]
512
1
0 0.0
0.1
0.2
0.3
0.4
0.5
ULoad [V]
Several load circuits for differential logic have been proposed. They require, however, careful
Fig. 3. Measured characteristic of the proposed load circuit for various bias conditions and for vss ¼ 0 and 0:2 V:
ARTICLE IN PRESS P. Fischer, E. Kraft / Nuclear Instruments and Methods in Physics Research A 518 (2004) 511–514
513
This step-wise characteristic can be approximated by a parallel connection of an NMOS operated in saturation as a current source and an element with a very steep characteristic. A second, diode connected NMOS is used in the proposed load circuit Fig. 2(b). Other implementations using diodes could also be used. The turn-on voltage and the capacitance of the element and the compatibility with the technology used must be considered. The expected characteristic shown in Fig. 2(a) illustrates that the low differential voltage level is well defined by the auxiliary supply voltage vss and the high level is reasonably well fixed by the turning on of the NMOS diode. Some important characteristics of this load are: *
*
*
The voltage levels are relatively insensitive to the bias current. The current can therefore be adapted in every gate to the load capacitance and the speed requirements. The sizing of the two transistors is not critical. In particular, the choice does not depend much on the bias current. The voltage swing can be adjusted very easily by changing vss. It can therefore be set to the minimum value sufficient to switch the differential tree. For devices operated in weak inversion, some 100 mV are sufficient.
3. Prototype results A prototype chip has been designed in a 0:25 mm CMOS technology with threshold voltages of E500 mV for NMOS and PMOS devices. Enclosed NMOS devices and guard rings have been used in the layout for radiation hardness [3,4]. The transistor sizes and bias conditions have been optimized for a moderate speed of several 10 MHz: This allows a supply voltage of only 1:2 V and leads to typical bias currents in the microampere range per gate so that most devices operate in weak inversion. A typical value for vss is 0:2 V at a high level of E400 mV so that the voltage swings are only E200 mV: Fig. 3 shows the measured load characteristic for vss ¼ 0 V and vss ¼ 0:2 V for various bias settings. Several test circuits have been studied. An inverter in an inverter chain has a power-delay
Fig. 4. Layout of a 16-bit static ripple counter with a parallel bus readout. Annular NMOS devices and guard rings have been used in a 0:25 mm technology. The size is E50 mm 50 mm:
product of below 3 mW ns: A shift register with parallel load input runs at E80 MHz if operated at 3 mW per stage. A simple 8-bit synchronous counter consumes 35 mW if operated at 8 MHz: A 16-bit static ripple counter can be operated with less bias current in the higher bits because they are clocked at lower speed. This power-efficient design leads to a consumption of only E6:5 mW for a maximum clocking frequency of 20 MHz: The layout of the full counter including a bus readout is shown in Fig. 4. It occupies an area of E50 mm 50 mm:
4. Summary A simple load circuit for differential currentsteering logic has been proposed. The logic swing is nearly independent of the bias current so that the gates can be operated at different power consumption depending on their capacitive load and the speed required. The layout area when using radiation tolerant design rules is comparable to CMOS.
ARTICLE IN PRESS 514
P. Fischer, E. Kraft / Nuclear Instruments and Methods in Physics Research A 518 (2004) 511–514
References [1] S.R. Maskai, et al., IEEE J. Solid State Circuits 27 (8) (1992) 1157. [2] J.G. Maneatis, et al., IEEE J. Solid State Circuits 28 (12) (1993) 1273.
[3] D.R. Alexander, et al., IEEE NSREC Short Course, Vol. 1, 1996. [4] W. Snoeys, et al., Nucl. Instr. and Meth. A 439 (2000) 349.