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Low-temperature transport of C60 thin-film FET
Physica B 329–333 (2003) 1538–1539
Low-temperature transport of C60 thin-film FET Kazunaga Horiuchia,b,*, Shin Uchinoa, Kenji Nakadaa, Nobuyuki Aokia, Masaaki Shimizub, Yuichi Ochiaia a
b
Department of Materials Technology, Chiba University, 1-33 Yayoi, Inage, Chiba 263-8522, Japan Corporate Research Center, Fuji-Xerox Co. Ltd., 430 Sakai, Nakai, Ashigarakami-gun, Kanagawa 259-0157, Japan
Abstract Electrical transport properties of C60 thin-film field-effect transistor (FET) grown at room temperature was investigated with various gate voltages. The conduction above 260 K and below 200 K can be well explained by a thermal activation model. Especially, it is noted that a strong dependence on the gate voltage appeared for the conduction above 260 K: r 2002 Elsevier Science B.V. All rights reserved. Keywords: C60 thin-film; Field-effect transistor; Transport; Thermal activation
1. Introduction
2. Sample and experiment
It is well known that C60 thin-film gives a n-type semiconducting behavior and a relatively high mobility in comparison with other organic materials. The conduction characteristics can be modulated in a wide range of 104 orders, by means of controlled gate voltage in field-effect transistor (FET). In recent reports [1–5] for oligothiophenes, pentacene and polythienylene vinylene, those conduction mobilities of those organic FETs show clear dependences on the gate voltage, which indicate that not only charge density but also transport mechanism could be affected by the field-effect in FET. Several models have been proposed to explain the gate dependence; localized polaron-like state [1], variable range hopping for exponentially distributed traps [2], extended state conduction with multiple trapping and release [3–5], energy barriers at grain boundary [4,5] or charge concentration effect at a semiconductor–insulator interface [4,5]. In this research, conduction characteristics of C60 thin-film FET has been studied as a function of temperature with various gate voltages.
C60 thin-film was thermally evaporated in a high vacuum with a C60 source, purified by liquid-chromatography to separate residual constituents. Heavily doped p-type Si wafer was used for a substrate in order to act as a back gate electrode with topping of an insulating layer of thermally grown silicon dioxide about 500 nm: The substrate was kept around room temperature to obtain an amorphous thin-film of C60 for the fabrication of FET. Channel electrodes of Au/Ti were patterned on the substrate in sizes of 85 mm (width) and 40 mm (gap). Before transport measurements, the sample was annealed in a high vacuum chamber at 400 K to exclude adsorbed oxygen for more than 10 h: The chamber was equipped with current-probe manipulators and liquidHe cooling cryostat, which enables successive measurements after the sample annealing. The sample was stabilized for 30 min at each temperature to avoid a current fluctuation by heat flow.
3. Results and discussion *Corresponding author. Corporate Research Center, FujiXerox Co. Ltd., 430 Sakai, Nakai, Ashigarakami-gun, Kanagawa 259-0157, Japan. E-mail address: [email protected] (K. Horiuchi).
Measured current of C60 thin-film FET are shown in the Arrhenius plots of Fig. 1 as a function of 1000=T with various gate voltages (Vg ). It is clearly seen about n-type character of C60 that the conduction increases if
0921-4526/03/$ - see front matter r 2002 Elsevier Science B.V. All rights reserved. doi:10.1016/S0921-4526(02)02282-2
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1539
2.5 Gate Voltages 0V 10 V 20 V 30 V 50 V
2 Eac (eV)
Current (A)
K. Horiuchi et al. / Physica B 329–333 (2003) 1538–1539
T > 260 K
1.5 1 0.5
2
4
6 8 1000/T (1/K)
10
12
Fig. 1. Arrhenius plots of electric conductions of C60 thin-film FET as a function of 1000=T are shown with various gate voltages. Straight lines indicate fitting results by a thermal activation model.
the gate voltage is added toward a plus polarity. As the temperature is lowered, it decreases monotonically for the conduction above 260 K and below 200 K: There exists no saturation in a low-temperature limit, which is different from recent reports in Refs. [3,5]. They observed saturation behaviors caused by a band-like conduction. We note that the conduction in our C60 thin-film FET can be explained by thermal activation processes, even if the highest gate voltage (Vg ¼ 50 V) is applied. Fitting analysis with a thermal activation process has been done to estimate activation energy (Eac ) for each temperature range above 260 K or below 200 K: The results are plotted as a function of gate voltage in Fig. 2. The Eac below 200 K does not change so much and decreases slightly with increasing gate voltage. On the other hand, the Eac above 260 K is strongly dependent on the gate voltage, where the Eac increases drastically with decreasing gate voltage. Since the Eac reflects an energy level of trapped carriers in C60 thin-film FET, the increase of Eac at low gate voltages should indicate that conduction carriers are trapped in a deep energy level at low gate voltages, which may have been introduced during vacuum deposition of C60 : At high gate voltages, the Eac saturates at 0:3 eV above 260 K and 0:2 eV below 200 K: These values indicate that conduction carriers
T < 200 K
0 -40
-20 0 20 Gate Voltage (V)
40
Fig. 2. Activation energies are plotted as a function of gate voltages for the conduction above 260 K and below 200 K:
induced by gate voltage can locate in a relatively shallow level below the conduction band.
4. Summary Electrical transport properties of vacuum deposited C60 thin-film FET has been investigated with various gate voltages. The FET conduction decreases as temperature is lowered, which can be explained by thermal activation processes. A strong dependence on the gate voltage has been observed for the conduction above 260 K; where there might exist a deep carrier trapping level introduced by vacuum deposition.
References [1] A. Brown, C. Jarrett, D. de Leeuw, M. Matters, Synth. Met. 88 (1997) 37. [2] M. Vissenberg, M. Matters, Phys. Rev. B 57 (1998) 12 964. [3] G. Horowitz, R. Hajalaoui, R. Bourguiga, M. Hajalaoui, Synth. Met. 101 (1999) 401. [4] G. Holowitz, R. Hajalaoui, D. Fichou, A. Kassmi, J. Appl. Phys. 85 (1999) 3202. [5] G. Horowitz, M. Hajalaoui, R. Hajalaoui, J. Appl. Phys. 87 (2000) 4456.
Low-temperature transport of C60 thin-film FET Kazunaga Horiuchia,b,*, Shin Uchinoa, Kenji Nakadaa, Nobuyuki Aokia, Masaaki Shimizub, Yuichi Ochiaia a
b
Department of Materials Technology, Chiba University, 1-33 Yayoi, Inage, Chiba 263-8522, Japan Corporate Research Center, Fuji-Xerox Co. Ltd., 430 Sakai, Nakai, Ashigarakami-gun, Kanagawa 259-0157, Japan
Abstract Electrical transport properties of C60 thin-film field-effect transistor (FET) grown at room temperature was investigated with various gate voltages. The conduction above 260 K and below 200 K can be well explained by a thermal activation model. Especially, it is noted that a strong dependence on the gate voltage appeared for the conduction above 260 K: r 2002 Elsevier Science B.V. All rights reserved. Keywords: C60 thin-film; Field-effect transistor; Transport; Thermal activation
1. Introduction
2. Sample and experiment
It is well known that C60 thin-film gives a n-type semiconducting behavior and a relatively high mobility in comparison with other organic materials. The conduction characteristics can be modulated in a wide range of 104 orders, by means of controlled gate voltage in field-effect transistor (FET). In recent reports [1–5] for oligothiophenes, pentacene and polythienylene vinylene, those conduction mobilities of those organic FETs show clear dependences on the gate voltage, which indicate that not only charge density but also transport mechanism could be affected by the field-effect in FET. Several models have been proposed to explain the gate dependence; localized polaron-like state [1], variable range hopping for exponentially distributed traps [2], extended state conduction with multiple trapping and release [3–5], energy barriers at grain boundary [4,5] or charge concentration effect at a semiconductor–insulator interface [4,5]. In this research, conduction characteristics of C60 thin-film FET has been studied as a function of temperature with various gate voltages.
C60 thin-film was thermally evaporated in a high vacuum with a C60 source, purified by liquid-chromatography to separate residual constituents. Heavily doped p-type Si wafer was used for a substrate in order to act as a back gate electrode with topping of an insulating layer of thermally grown silicon dioxide about 500 nm: The substrate was kept around room temperature to obtain an amorphous thin-film of C60 for the fabrication of FET. Channel electrodes of Au/Ti were patterned on the substrate in sizes of 85 mm (width) and 40 mm (gap). Before transport measurements, the sample was annealed in a high vacuum chamber at 400 K to exclude adsorbed oxygen for more than 10 h: The chamber was equipped with current-probe manipulators and liquidHe cooling cryostat, which enables successive measurements after the sample annealing. The sample was stabilized for 30 min at each temperature to avoid a current fluctuation by heat flow.
3. Results and discussion *Corresponding author. Corporate Research Center, FujiXerox Co. Ltd., 430 Sakai, Nakai, Ashigarakami-gun, Kanagawa 259-0157, Japan. E-mail address: [email protected] (K. Horiuchi).
Measured current of C60 thin-film FET are shown in the Arrhenius plots of Fig. 1 as a function of 1000=T with various gate voltages (Vg ). It is clearly seen about n-type character of C60 that the conduction increases if
0921-4526/03/$ - see front matter r 2002 Elsevier Science B.V. All rights reserved. doi:10.1016/S0921-4526(02)02282-2
10
-5
10
-6
10
-7
10
-8
10
-9
10
-10
10
-11
10
-12
1539
2.5 Gate Voltages 0V 10 V 20 V 30 V 50 V
2 Eac (eV)
Current (A)
K. Horiuchi et al. / Physica B 329–333 (2003) 1538–1539
T > 260 K
1.5 1 0.5
2
4
6 8 1000/T (1/K)
10
12
Fig. 1. Arrhenius plots of electric conductions of C60 thin-film FET as a function of 1000=T are shown with various gate voltages. Straight lines indicate fitting results by a thermal activation model.
the gate voltage is added toward a plus polarity. As the temperature is lowered, it decreases monotonically for the conduction above 260 K and below 200 K: There exists no saturation in a low-temperature limit, which is different from recent reports in Refs. [3,5]. They observed saturation behaviors caused by a band-like conduction. We note that the conduction in our C60 thin-film FET can be explained by thermal activation processes, even if the highest gate voltage (Vg ¼ 50 V) is applied. Fitting analysis with a thermal activation process has been done to estimate activation energy (Eac ) for each temperature range above 260 K or below 200 K: The results are plotted as a function of gate voltage in Fig. 2. The Eac below 200 K does not change so much and decreases slightly with increasing gate voltage. On the other hand, the Eac above 260 K is strongly dependent on the gate voltage, where the Eac increases drastically with decreasing gate voltage. Since the Eac reflects an energy level of trapped carriers in C60 thin-film FET, the increase of Eac at low gate voltages should indicate that conduction carriers are trapped in a deep energy level at low gate voltages, which may have been introduced during vacuum deposition of C60 : At high gate voltages, the Eac saturates at 0:3 eV above 260 K and 0:2 eV below 200 K: These values indicate that conduction carriers
T < 200 K
0 -40
-20 0 20 Gate Voltage (V)
40
Fig. 2. Activation energies are plotted as a function of gate voltages for the conduction above 260 K and below 200 K:
induced by gate voltage can locate in a relatively shallow level below the conduction band.
4. Summary Electrical transport properties of vacuum deposited C60 thin-film FET has been investigated with various gate voltages. The FET conduction decreases as temperature is lowered, which can be explained by thermal activation processes. A strong dependence on the gate voltage has been observed for the conduction above 260 K; where there might exist a deep carrier trapping level introduced by vacuum deposition.
References [1] A. Brown, C. Jarrett, D. de Leeuw, M. Matters, Synth. Met. 88 (1997) 37. [2] M. Vissenberg, M. Matters, Phys. Rev. B 57 (1998) 12 964. [3] G. Horowitz, R. Hajalaoui, R. Bourguiga, M. Hajalaoui, Synth. Met. 101 (1999) 401. [4] G. Holowitz, R. Hajalaoui, D. Fichou, A. Kassmi, J. Appl. Phys. 85 (1999) 3202. [5] G. Horowitz, M. Hajalaoui, R. Hajalaoui, J. Appl. Phys. 87 (2000) 4456.