Microcomputer networks

Hardware den Beste, S 'A programmable logic analyser' MiniMicro Systems Vol 14 No I (January 1981) pp 137-144 The traditional approach of hard wiring a logic analyser (the primary debugging tool of digital electronics) into only a few configurations is fast reaching its limits. The author looks at Tektronix's 7D02, the first of the new generation of logic analysers with user-programmable resources. Architecture and operations are described (it is a RAM-based state machine) as well as the use of the counters and the timing option. Clements, A 'An introduction to bit-slice microprocessors' Electronics & Power Vol 27 No 3 (March 1981) pp 230-235 The bit-slice microprocessor is essentially a set of individual functional components which can be precisely arranged by a designer for a specific application. The advantage of this is that, for marginal extra cost, devices are available which are quicker and have longer wordlengths. The bitslice elements themselves have a lower number of gates per chip than LSI NMOS devices because they are fabricated with Schottky TTL, ECL or IlL techniques. This, however, gives clock rates of upto 20 MHz as compared with about 1 MHz for conventional 8-bit microprocessors. The paper also gives arrangements of 8-and 16-bit bit-slice devices. Danhof, K J and Shah, V 'A multimicroprocessor architecture for industrial/process control applications' Microcomputer Applications Vol 4 No 4 pp 2 0 4 - 2 1 8 The main shortcomings of microprocessors when compared with hardwired logic and mainframes is their slow speed and limited word size these limitations can often be overcome using multiprocessor architecture. This paper describes a low cost modular multimicroprocessor configuration. The system was designed specifically for industrial/process control applications and uses direct

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memory access (DMA) to facilitate the efficient transfer of data between processors. The system uses five identical 6800 microprocessors. Ekanadham, K and Mahjoub, A 'Microcomputer networks' The Computer/ournal Vol 24 No 1 (February 1981) pp 1 7 - 2 4 This paper presents an implementation of Hoare's I/O commands on a twodimensional network of microcomputers. The implementation is defined so that message transfer delays are bounded by a constant. The communication kernal is small and is embedded in each process. Dedicated processors are used for message handling. Areas looked at are communication, hardware and implementation (particularly a derivation of a constant upper bound on message transfer time). Example programs are also provided. Grappel, R and Hemenway, J 'Evaluating the 16-bit chips' MiniMicro Systems Vol 13 No ] 2 (December 1980) pp 152-162 This paper looks at three leading 16bit microprocessors- the I ntel 8086, the Motorola 68000 and the Zilog Z7000 - and evaluates their strengths and shortcomings in relation to five criteria, namely system calls, byte manipulations, number crunching, architectural features and extended memory addressing. The conclusion is that the 68000 is ahead of the others in its ability to provide uniform addressing of its entire 16 Mbyte space and to allow use of any of its address registers as a stack pointer. It, however, lacks the byte addressability of the 8086 and Z8000 p rocesso rs.

Healey, M 'The possible impact of minicomputers and microprocessors on mainframe computer manufacturers' The Computer Journal Vol 24 No 1 (February 1981) pp 3 - 8 The computer industry has evolved along many different paths, largely because of the different applications areas. The paper focuses on the dominant area of data processing. The widespread availability of the cheap LSl component and cheap high memory

hard disc peripherals means that the market traditionally dominated by mainframe manufacturers will be increasingly wide open. This paper attempts to present a broad view of the current situation and project this into the future. The conclusion is that the mainframe computer manufacturers are not in as safe a position as many market results might forecast.

Huffman, G D 'Programmable memories make product redesign easy' EDN Vol 26 No 2 (21 January 1981) pp 106-117 The latest programmable memory introductions reflect advances to higher speed devices. Speed, however, is not the only improvement - new device types and options can also aid design. Huffman looks at PROMs, EPROMs and EEPROMs and compares, in tabular form, the main types available (PROMs are much faster than masked ROMs or EPROMs, but being fuselinkprogrammable, they must be written correctly first time). A list of names and addresses of PROM manufacturers is included.

Moralee, D 'Microprocessor architectures; ten years of development' Electronics & Power Vol 27 No 3 (March 1981) pp 214-221 This overview of the development of microprocessor architecture begins with the Intel MCS-4, the first 'microprogrammable microcomputer', based on the 4004 single chip CPU. This PMOS device, with only 2250 transistors, was the very first microprocessor. The paper looks at the 4-bit microcontroller, LSI bit-slice devices (8-bit microprocessors) and the third-generation CPUs (16-bit microprocessors). Computer architecture, concepts, features and limitations are examined. The evolutionary pressures, from PMOS through NMOS to HMOS technology, are considered, culminating in the 'supermicro', the 32-bit machine.

Robinson, G P S 'Case history: an input/output expansion unit for the PASCAL Microengine' Microcomputer Applications Vol 4 No 4 pp 248-255 In implementing a microprocessor workstation based on the PASCAL Micro-

microprocessors and microsystems