Mixed level test generation for high fault coverage

Microprocessing and Micro~':agramming32 (1991) 791-796 North-Holland

791

Mixed Level Test Generation for High Fault Coverage U. H ~ b n e r , H. H i n s e n , M. H o f e b a n e r a n d H. T . V i e r h a u s G M D / E . L S . W - 5 2 0 5 St. A u g u s t i n 1, G e r m a n y

Methods for test generation providing high fault coverage for non-trivial faults in CMOS circuits have been a subject of intense research for several years. By test generation from switch level netlists, a good fault coverage is possible also for circuits including structur~ ]~ke complex gates and transmission gates. However, a prohibitive amount of computer time is necessary for large designs. This paper describes an efficientcombination of switch level and gate level test generation providing r~bust 2-pattern pairs via dynandc coupling of test generators.

1

Introduction

In recent years test generation for IC faults beyond the static stuck at model has been worked on by a large number of authors. Results published by Ferguson and Shen [1] have pointed out a demand for improvements particularly concerning stuck-on faults,delay faults and bridging faults. The importance of bridging faults may have been underestimated for a long time [2]. Stuck-open faults seem to have a relatively low statistical importance, but are a reality [14,15]. The additional effort necessary to generate robust twopattern pairs instead of single patterns is relatively high and may be unacceptable under economic aspects if required for stuck-open faults only. Two-pattern pairs will, however, serve to test for transition faults in general, which may well be caused by other effects than stuck-open faults. Faults of this type will mostly if not always be covered by test generation for path- and gate delay faults [8,9], if the circuit is based on simple gate level primitives. Deficiencies in test generation due to inadequate circuit description at gate level have found attention only in a few papers [4,13]. This may be attributed to the fact that most logic designs use only relatively simple gate level structures. It is, however, understood that, with a maximum of freedom in transistor level circuit design, considerable savings in transistor numbers are possible if complex gates and pass transistor structures are implemented [12]. Such design styles, however~ will be relatively risky to use without adapted methods for test generation. Fc,r this reason, a ndxed-level test generation comparable to the approach reported by Glover [13] was developed

which, however, provides robust 2-pattern sequences. Fig. 1 shows a simple n~xed-level drcuit including a common EXOR-implement at;.on.

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2

Concepts of the C T E S T /

LTEST ATPG System Work in this area started with the CTEST switch level ATPG program [3,16] pmddin K tests for stuck open faults. As found by other authors too [13],the effort at this level increases almost exponentiLlly with circuit s~e. Thus a practical Umlt for test generation at switch level is seen at complexities between 200 and 500 transistors. For CMOS primitive gates, who~ iutarnal structure is essentially lr~own, gate level ATPG taking care of internal nodes provides a reasonable fault coverage [4],if switching v~iaall inputs by robust pattern

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Fig. 2: Stuck-open fault in a CMOS complex gate and locally generated test patterns pairs is provided. Hence switch level ATPG should be ]hn]ted to structures, which are detected as nonprimitive by automatic extraction from switch level or pre-defmed by the user. In the CTEST/LTEST ATPG system, a circuit to logic extractor is provided to perform such a prese|ection process on switch level netlists. L o ~ switch level ATPG will generate test patterns, which may be c|ase to an optimum under local aspects within an embedded complex gate or macro. Even longer test sequences to save tke e~orts for initlalization are pos~ble. Under global conditions, however, sequences of more than two patterns including robust tran~it~on~ w ~ mostly be d~fl~cult to apply. A global constraint analy~s reducing the degree of freedom in ]oce~ ATPG was therefore developed, which provides a more deta~ed information on g~obal]y unacceptable patterns than the approach reported by Glover [13]. Figs. 2 and 3 show an example of locally generated ~est p a t t e r ~ which w ~ not be applicable due to gate |evel path reconvergences.

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Fig. 4: Switch level test invalidation due to external gate level hazard condition For global test generation, LTEST was developed as a adapted gate-level generator creating 2-pattern tests with, if possible, globally robust transitions. In earlier approaches for hierarchical test generation [18,19], fixed precomputed sets of test patterns for modules were used. Such an approach leads to an underuti]ization of available degrees of freedom in local test generation and may unnecessarily cause global conflict situations resulting in unnecessary backtracks during the gate level ATPG process and possibly reduced fault coverage. The CTEST/LTEST system therefore includes an efficient gate level to switch level backtracking facility, if global conflicts arise.

Mixed level test generation for h~gh fault coverage

3

Switch Level Test G e n e r a t i o n

by CTEST As the first part of the new ATPG system, a switch level test generator was developed providing 2-pattern tests to cover fau|ts like stuck-off transistors, delay effects, and interrupted lines by optimized path switching procedures. CTE.ST works on SPICE [20] and BONSAI [21] format netlists. In the first step of the program flow, such netlists are stripped from capacitors and resistors except for bias resistors providing VDD/GND potentials. Nodes are merged where appropriate. Then transistor circuits are modeled as graphs according to Chiang et aL [5]. A local analysis first performs a classification of nodes to distinguish VDD, GND, external I / O nodes, output nodes of substructure, and internal connection nodes.

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level networks was not implemented, hut is p~ovided via the switch level to gate level coupling. CTEST performs an evaluation of tests for the coverage of faults on NTC interconnects between t r ~ s t ~ ¢ s . If necessary, additional patterns are generated to coves inten-upts on all non-redundant lines. The final output of CTEST is a pattern list completed by information on untenable transistors. Addltlanally functional descriptions are generated for switch level macros to provide the u a c ~ r y in.rotation ~he gate level ATPG for propagation of p a t t e n s through the respective macros.

4

A d a p t e d G a t e Level Test Generation

sequences with optimum choice for overall pattern length

LTEST was developed as an extended imp]ementao tion of the FAN [6] algorithm h ~ on the transition fault model. Pattern pah~ instead of ~ugle tmtter~ are generated to provide stuck-open tests. A high fault coverage for basic gates is reached by switching the output state via each of the inputs rather t]mn just monitoring stuck-at conditions at input nodes. LTEST generates an initiaUsation at the device test followed by the test pattern. It seems h~gh]y desirable to generate a path f~om the output of the gate under test to a primary drcuit output, which aUows to observe the transition directly, particularly if gate delay tests are required. In netlists with reconversent fanout paths, however, this condition wi]] po~ibly reduce the number of allowed alternatives for initiaIL~* tion and test con~derably. In a mixed-level ~ e r a r c ~ ca[ test environment such as the CTEST/LTEST system, a maximum of allowed alternatives at gate level is crucial to the performance of the overall system. In particular the total number of inter ]eve] backtmchs has to be m;n~rn;~l for ovexa~ pedormance. For this reason, LTEST provides the ohservability at a primary output only for the test pattern. Faults are observable if the wanted transition fails or happens ~ t h a delay much beyond normal gate delays.

Under mixed level ATPG conditions, only the generation of 2-pattern pair~ is possible. Generally CTEST provides robust patterns under local conditions by e. g. prohibiting conducting parallel paths in a complex gate except for initialization. In order to avoid switching hazards, there is only a one-input transition between initialization and test at the input of each complex gate or macro where possible. Under restrictive side conditions, also multiple-state- transitions are allowed (e. g. because of gate-level constraints). A global hazard analysis in large switch

With ~spect to the ohsesvabUlty of gate delay fanlts, this method is, however, inferior to optimized gate delay test generators ns~g 10-valued logic [11]. The validity of the 2-pattern test is ev~uated by a static hase~d analy~s. Recouverseut paths possibly causing hazards eke detected and pattern p e ~ for robust tests are generated whexe poe~ble. If a robust test is found impos~ble to apply, a simple nonrobust pair is generated in order to provide at least a stuck-at test. The previously developed EXTEST program [17] is used as a p r e p r o c ~ o r to LTEST in a

Substructurs such as elementary gates, complex gates, internal pass transistors, and nMOS / CMOS transmission gates are recognized. Elementary gates are identified and stored as part of a gate-level netlist. With CTEST operating on a switch-level input netlist only, identification and preparation of a logic netllst for treatment by gate-level ATPG is done autonmticaily. In order to provide tests not only for transistors hut also for non- redundant interconnecting lines within complex gates, special attention is given to nodes rinking four or more internal transistors (NTC-nodes). A detailed description of CTEST operation is given elsewhere [3,16]. CTEST can be used for local switch level test generation in one of three operation modes. The the user can choose between 3 alternatives: -

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generation of independent pairs of patterns, generation of maximum length pattern sequences,

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Parts of the circuitlevelnetwork containingonly basic gates are transferredto the logicnetlistfor treatment by LTEST. In case a circuit level network contains only such basic gates, the local switch-leveltest generation by C T E S T is not invoked, test generation is then performed only at gate level. If, however, complex gates or genera[ transistornetworks axe detected by C T E S T , a local switch-leveltest generation is performed for such structures.The coupling is organized to reject, based on a gate levelanalysis, pattern pairs from local generation,which are eithernot applicable or cannot be psopagated to a pfimaxy output. On top of this LTEST also provides a check for robustness of pattern pairs. ~ a non-robust pair is detected,the inifiv~zafion pattern is kept, and CTEST is trlggered to generate a n alternative test. If a robust test cannot be found tlds way, the initialization is also changed. This re-calculation uses the existing D-cubes in CTEST

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Fig. 6: Simplified version of the LTEST / CTEST flow graph

Mixed level test generation for high fault covet~e

making this operation rather efficient. The additional computing time is about proportional to the ratio of patterns to be recomputed over the total number of patterns in the local test set. Fig. 6 shows a simplified LTEST/CTEST flow graph, which refers to a mixed level netlist containing one switch-level macro. An extended version handling larger multi-level netlists is under development.

6

Tab. 2: LTEST Performance on Example Circuits a) CPU-min. on Sun 4/65 without / with check for robustness

Results

At present CTEST was tried out on a number of switch level netlists with reasonable results. Run times are generally in the order of 0.5 s on a VAX 8810 for circuits up to 50 trnasistors. In a exceptional case t~f a 54 transistor circuit containing excessive use of hi-directional structures, 16 s were used (see Tab.l). Fault coverages of 100% for transistor stuck-off faults and interrupted lines are obtained except for circuits containing active redundancy due to CMOS transmission gates. Times required for re-calculation of pattern pairs for complex gates are in the order of 0.01 to 0.05 s per backtracking procedure. Basically efforts in local test generation could be traded against efforts in inter-level coupling by setting minimum / maximum sizes of switch level macros. Here first experience showed that, due to the relatively efficient coupling procedure, minimum size switch level circuits will be close to the optimum. Tab. I : CTEST Performance on Example Circuits (on VAX 8810) circuit 2-AND

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cost about 50% of the whole run time, robu~ te~s can be generated in meet cases. As random test generation, which is commonly employed in combinatlon with fault ~imulation in conventional ATPG as a preprocess, is hardly applicable to r o b o t pattern pairs, CTEST/LTEST has to provide the fun test length. Compres~on and ver;~cation of test sets is ~ b ] e by a proprietary switch-levd fault s;mulator FEHSD~ [7]. FEHSIM covers stuck-open-, stuck-on- and local bridging faults, but is not yet integrated in the ATPG procedure. For this reason, test sets tend to be ~latlvely long.

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LTEST was also tried out on a number of benchmexk circuits (see Tab. 2). At present run times are a about 5 to 30 minutes for networks of several hundred gates on a San 4/65 including test generation of pattern pcirs for ~ internal nodes. Although the hazard analysis is relatively restrictive and tends to

Compared with existing tools, the CTEST / LTEST TPG system holds the potential of improved fault coverage for non-trivial networks with respect to transistor faults and interrupted lines. The tran~tion fault model also improves the detectability of bridging faults causing delay effects.

7

Forthcoming Work

At present the CTEST/LTEST system is extan&d towards handling large gate level netlists with switch level macros and subcircuits (see Fig. 1). The problems to be solved n ~ n l y concern the consistent hendiing of gate level netllsts in combination with switchlevel logic extraction. It has still to be investigated, if the additional effort for a global constraint analysis procedure reduces the number of b~.ktracks betwecn LTEST and CTEST sufficiently to justify the additional initial effort. Further improvements will concern the inch!~on of explicit t©s~ generation for bridging faults and an improved hazard analy'~is.

796

U. Huebner et aL

CTEST and LTEST are currently running under VMS and under Sun OS on San 4 machines.

8

Acknowledgements

This work was ~ponsor~dby the German Federal Ministry for Research and Technology (BMFT) under grant NT 2858. The authors are ~so thankful to Prof. W. Evex]ing (Univ. of Bonn) for lds support.

References [1] F. Ferguson and J. Shen, "Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis", IEEE Int. Test Conf. 1988, pp. 475-484 [2] S. D. Millman and E. J. McCluskey, "Detecting BHd~ng Faults with Stuck-at Test", IEEE Int. Test Conf. 1988, pp. 773-783 [3] C. Matthv~us, H. T. Vierhans et al, "CMOS Fault Modeling, Test Generation and Dedgn for Testability", Proc. EUROI~CRO'88, Microprocess]ng and I~croprogrammlng Vol. 24, pp.233238

[10] V. S. Iyengar, B. K. Rosen, and L Spencer, "Delay Test Generation I - Concepts and Coverage Metrics", Proc. IEEE Int. Test Conf., 1988 [11] K. Fuchs, "Testen yon PfadverzSgerungsfehlem in digitalen Schaltungen", Proceedings 1. ARIADNE-Workshop, GMD, 1990 [12] G. Thuau and G. Saucier, "Complex MOS Gates Compiler", Proc. IEEE 1987 Custom Integrated Circuits Conference [13] C. Glover, "Mixed Mode ATPG Under Input Constraints", Proc. IEEE Int. Test Conf. 1990 [14] M. Jacomet, "FANTESTIC: Towards a Powerful Fault Analysis and Test Pattern Generator for Integrated Circuits", Proc. IEEE Int. Test Conf. 1990 [15] J. M. Soden, R. K. Treese, M. R. Taylor, and C. F. Hawkins, "CMOS IC Stuck Open Fault Electrical Effects and Design Considerations", Proc. IEEE Int. Test Conf. 1989 [16] U. Hilbner, "CMOS Testgenerierung fi~r hohe Fehler~berdeckung", GMD-Studie Nr. 174, GMD, St. Augustin, 1989

[4] H. T. Vierhaus, "Testabi~ty of CMOS Faults Under Realistic Conditions", Proc, EUROMICRO'89, Microprocessing and Microprogramruing Vol. 27

[17] C. Matth~us, B. Kr~ger-Sprengel, and H. T. Vierhaus, "EXTEST, a Knowledge Based System for the Design of Testable Logic Circuits", Proc. CompEuro '89, Hamburg

[5] K.W. Chiang and Z. G. Vraneslc, "On Fault Detection in CMOS Logic Networks", 20th Design Automation Conference, 1983

[18] B. T. Murray and J. P. Hayes, "Hierarchical Test Generation Using Precomputed Tests for Modules" Proc. IEE]~ Int. Test Conf. 1988

[7] W. Meyer and H. T. Vierhaus, "Switch-Level Fault Simul.atlon for Non-Trivia] Faults Based on Abstract Data Types", IEEE CompEuro ' 91, Bologna

[19] G. Alfs, R. W. Hartenstein, and A. Wodtko, "Explicit Fault Modeling and Hierarchical Test Pattern Generation in the KARATE System", Proc. EUROMICRO '89, Microprocessing and Microcomputing Vol. 27, 1989 [20] L. W. Nagel, "SPICE2: a Computer Program to Simulate Semiconductor Circuits", Memo ERL M520, University of California-Berkeley, 1975

[8] A. K. Pramanick and S. M. Reddy, "On the Detection of Delay Faults", Proc. IEEE Int. Test Conf. 1988

[21] P. Richert and H. Sibbert, "BONSAI User Manual", Fraunhofer-Institut IMS, Duisburg, and Robert Bosch GmbH, Rentliagen, 1986

[6] H. Fujiwera ~ d T. Slfimono, "On the Acceleration of Test Generation Algorithms", IEEE Trans. on Computers C-32, pp. 1137-1144

[9] E. S. Park, M. R. Mercer, and T. W. Williams, "Statistical Delay Fault Coverage and Defect Level for Delay Faults", Proc. IEEE Int. Test Conf. 1988