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New applications open up for silicon sensors: a special report
280
World Abstracts on Microelectronics and Reliability
reviewed. Existing literature has been classified with respect to above listed features of standby systems. An up-to-date bibliography is presented systematically. Procedure for weighting failure rates in Markov reliability models for automation systems. P. FRIES. Siemens Res. Devel. Rep. 9 (5), 305 (1980). On account of their complexity, reliability forecasts for electronic process-automation systems can usually only be made by means of analytical probability models. The Markov model illustrates the logical failure relationships, including maintenance and repair, in a particularly clear manner. It will be shown how this characteristic can be extended by incorporating a "weighting procedure" for failure rates. This allows the differentiated representation and evaluation of different effects of individual component failures with "dummy" states. Terms such as Markov chains and Semi-Markov processes will be explained. Economical failure analysis for microprocessors. RONALD T. TAYLOR, IEEE Trans. Reliab. R-29 (3), 203 (August 1980). A technique is presented for isolating the failing node within a microprocessor type chip. The computer-driven productiontester is used to identify the failing instructions prior to failure analysis. In the laboratory, simple two or three instruction test-patterns are programmed into a n x 16 (1 ~< n ~< 255) memory buffer and then clocked into the device under test in an endless repetitive loop. Internal microprobing is then used to check the internal control lines and registers to localize the failure. The technique has been used to isolate failure mechanisms on wafers and in packaged devices from a variety of sources, including environmental stress failures and field returns. The article demonstrates the feasibility of performing efficient, accurate, and low cost failure analysis on microprocessors. The essential features are an efficient laboratory administrative system, concise and accurate input documentation, knowledge of the internal workings of each chip, the memory buffer-testing technique, and an accurate microprobing capability. Results at Mostek indicate that a single, well trained technician with occasional engineering supervision can successfully analyze an average of two moderately difficult failing devices per day. Since a usual sample of devices will contain some simple failures, an average daily throughput of about four to five devices has been realized. The capital outlay (less than $1000) for the equipment (exclusive of pre-existing lab equipment such as an oscilloscope) has been confined to the construction and components cost of the memory buffer and its associated interconnect wiring.
Microprocessor and LSI microcircuit reliability-prediction model. HENRY C. RICKERS and PETER F. MANNO. IEEE Trans. Reliab. R-29 (3), 196 (August 1980). This paper discusses the development of an improved failure-rate prediction method which can be used to assess the reliability of complex and new-technology microcircuits, especially memories, microprocessors, and their support devices. The prediction models are similar to those presented in MILHDBK-217C with several modifications to reflect the variation of reliability sensitive parameters and to discriminate against the device design and usage attributes which contribute to known failure mechanisms. A comparison of the failure rate predictions calculated using MIL-HDBK-217C and the actual failure rates for LS1 random logic and memory devices did not indicate a reasonable correlation. An analysis of the 217C models revealed that the lack of correlation was attributable to the generic consolidation of model parameters, which ultimately reduced model sensitivity to several critical reliability factors. The model accuracy was greatly improved, without substantially increasing model complexity, by separating some generic parameters into sets of more detailed parameters. The major model revisions included: Complexity factors oriented toward major device function and technology categories Development of temperature factors for each device technology, in both hermetic and nonhermetic packages Introduction of an additive package failure-rate factor based upon package type and number of functional pins Introduction of a voltage derating stress factor for CMOS devices with maximum recommended operating supply voltage greater than 12 volts Introduction of a ROM and PROM programming technique factor to reflect the influence of the programming mechanism used in these devices. The improved models possess all those qualities common to practical reliability assessment techniques. The expressions are relatively simple to use and allow for evolving fabrication techniques and emerging technologies. An alternative fault-tree algebra. JAMES M. CARGAL. IEEE Trans. Reliab. R-29 (3), 269 (August 1980). This paper describes an algebra that complements Boolean algebra and which can be useful for non-coherent systems. This algebra involves substantially less manipulation than Boolean algebras do, and is convenient for describing the exclusive-or operation.
4. M I C R O E L E C T R O N I C S - - G E N E R A L ISSCC opens era of ultra LSI. JOHN G. POSA. Electronics p. 71 (18 December 1980). HP's six-chip set goes beyond LSI as meeting also establishes that C-MOS is the leading technology for memories and processors.
Limits to the size of semiconductor devices. B. L. H. WILSON. Electron. Power p. 704 (September 1980). Component density on integrated circuits continues to increase at a high rate. What are the limitations to miniaturisation of components, and by what means are these limits pushed back?
Microelectronics takes to the road in a big way: a special report. GIL BASSAK.Electronics p. 113 (20 November 1980). With electronic engine controls set for 1981, auto makers are turning their attention to electronic options.
New applications open up for silicon sensors: a special report. ROGER ALLAN. Electronics p. 113 (6 November 1980). The push to interface microprocessors with the real world will create a huge demand for monolithic sensing devices.
5. M I C R O E L E C T R O N I C S - - D E S I G N Application of conductive adhesives in microcircuits for "longlife" equipment. C. W. L. KOORING and D. RIPHAGEN. Electrocomp. Sci. Technol. 7, 69 (1980). The results of a study of the application of conductive adhesives for attaching semiconductor chips to thin film Au conductors is presented.
AND
CONSTRUCTION
The study concentrates on measuring the stability of the electrical conductivity of adhesive bonds for semiconductor chips. Four types of conductive bonding agents and two types of semiconductor back metallization were tested at raised temperatures for up to 10,000 hours.
World Abstracts on Microelectronics and Reliability
reviewed. Existing literature has been classified with respect to above listed features of standby systems. An up-to-date bibliography is presented systematically. Procedure for weighting failure rates in Markov reliability models for automation systems. P. FRIES. Siemens Res. Devel. Rep. 9 (5), 305 (1980). On account of their complexity, reliability forecasts for electronic process-automation systems can usually only be made by means of analytical probability models. The Markov model illustrates the logical failure relationships, including maintenance and repair, in a particularly clear manner. It will be shown how this characteristic can be extended by incorporating a "weighting procedure" for failure rates. This allows the differentiated representation and evaluation of different effects of individual component failures with "dummy" states. Terms such as Markov chains and Semi-Markov processes will be explained. Economical failure analysis for microprocessors. RONALD T. TAYLOR, IEEE Trans. Reliab. R-29 (3), 203 (August 1980). A technique is presented for isolating the failing node within a microprocessor type chip. The computer-driven productiontester is used to identify the failing instructions prior to failure analysis. In the laboratory, simple two or three instruction test-patterns are programmed into a n x 16 (1 ~< n ~< 255) memory buffer and then clocked into the device under test in an endless repetitive loop. Internal microprobing is then used to check the internal control lines and registers to localize the failure. The technique has been used to isolate failure mechanisms on wafers and in packaged devices from a variety of sources, including environmental stress failures and field returns. The article demonstrates the feasibility of performing efficient, accurate, and low cost failure analysis on microprocessors. The essential features are an efficient laboratory administrative system, concise and accurate input documentation, knowledge of the internal workings of each chip, the memory buffer-testing technique, and an accurate microprobing capability. Results at Mostek indicate that a single, well trained technician with occasional engineering supervision can successfully analyze an average of two moderately difficult failing devices per day. Since a usual sample of devices will contain some simple failures, an average daily throughput of about four to five devices has been realized. The capital outlay (less than $1000) for the equipment (exclusive of pre-existing lab equipment such as an oscilloscope) has been confined to the construction and components cost of the memory buffer and its associated interconnect wiring.
Microprocessor and LSI microcircuit reliability-prediction model. HENRY C. RICKERS and PETER F. MANNO. IEEE Trans. Reliab. R-29 (3), 196 (August 1980). This paper discusses the development of an improved failure-rate prediction method which can be used to assess the reliability of complex and new-technology microcircuits, especially memories, microprocessors, and their support devices. The prediction models are similar to those presented in MILHDBK-217C with several modifications to reflect the variation of reliability sensitive parameters and to discriminate against the device design and usage attributes which contribute to known failure mechanisms. A comparison of the failure rate predictions calculated using MIL-HDBK-217C and the actual failure rates for LS1 random logic and memory devices did not indicate a reasonable correlation. An analysis of the 217C models revealed that the lack of correlation was attributable to the generic consolidation of model parameters, which ultimately reduced model sensitivity to several critical reliability factors. The model accuracy was greatly improved, without substantially increasing model complexity, by separating some generic parameters into sets of more detailed parameters. The major model revisions included: Complexity factors oriented toward major device function and technology categories Development of temperature factors for each device technology, in both hermetic and nonhermetic packages Introduction of an additive package failure-rate factor based upon package type and number of functional pins Introduction of a voltage derating stress factor for CMOS devices with maximum recommended operating supply voltage greater than 12 volts Introduction of a ROM and PROM programming technique factor to reflect the influence of the programming mechanism used in these devices. The improved models possess all those qualities common to practical reliability assessment techniques. The expressions are relatively simple to use and allow for evolving fabrication techniques and emerging technologies. An alternative fault-tree algebra. JAMES M. CARGAL. IEEE Trans. Reliab. R-29 (3), 269 (August 1980). This paper describes an algebra that complements Boolean algebra and which can be useful for non-coherent systems. This algebra involves substantially less manipulation than Boolean algebras do, and is convenient for describing the exclusive-or operation.
4. M I C R O E L E C T R O N I C S - - G E N E R A L ISSCC opens era of ultra LSI. JOHN G. POSA. Electronics p. 71 (18 December 1980). HP's six-chip set goes beyond LSI as meeting also establishes that C-MOS is the leading technology for memories and processors.
Limits to the size of semiconductor devices. B. L. H. WILSON. Electron. Power p. 704 (September 1980). Component density on integrated circuits continues to increase at a high rate. What are the limitations to miniaturisation of components, and by what means are these limits pushed back?
Microelectronics takes to the road in a big way: a special report. GIL BASSAK.Electronics p. 113 (20 November 1980). With electronic engine controls set for 1981, auto makers are turning their attention to electronic options.
New applications open up for silicon sensors: a special report. ROGER ALLAN. Electronics p. 113 (6 November 1980). The push to interface microprocessors with the real world will create a huge demand for monolithic sensing devices.
5. M I C R O E L E C T R O N I C S - - D E S I G N Application of conductive adhesives in microcircuits for "longlife" equipment. C. W. L. KOORING and D. RIPHAGEN. Electrocomp. Sci. Technol. 7, 69 (1980). The results of a study of the application of conductive adhesives for attaching semiconductor chips to thin film Au conductors is presented.
AND
CONSTRUCTION
The study concentrates on measuring the stability of the electrical conductivity of adhesive bonds for semiconductor chips. Four types of conductive bonding agents and two types of semiconductor back metallization were tested at raised temperatures for up to 10,000 hours.