Novel CMOS fully integrable interface for wide-range resistive sensor arrays with parasitic capacitance estimation

Available online at www.sciencedirect.com

Sensors and Actuators B 130 (2008) 207–215

Novel CMOS fully integrable interface for wide-range resistive sensor arrays with parasitic capacitance estimation Giuseppe Ferri a,∗ , Vincenzo Stornelli a , Andrea De Marcellis a , Alessandra Flammini b , Alessandro Depari b a b

Department of Electrical Engineering, University of L’Aquila, L’Aquila, Italy Department of Electronics for Automation, University of Brescia, Brescia, Italy Available online 6 August 2007

Abstract In this work we present a novel CMOS fully integrable interface for wide-range resistive gas sensors. The proposed circuit is able to reveal more than six decades of resistance variation and at the same time to estimate the sensor parasitic capacitance, showing high linearity and reduced percentage error between measured and theoretical results. The implementation as integrated circuit in a standard CMOS technology allows the whole interface to be considered a simple and low-cost solution for wide-range resistive sensor arrays. © 2007 Elsevier B.V. All rights reserved. Keywords: Gas sensors; CMOS sensor interfaces; Wide-range sensor variation

1. Introduction Resistive gas sensors show base-line values varying in a very high range and the sensitive elements heavily change their resistance according to their preparation or structure. Moreover, the resistance value of the sensitive element could change substantially also for small reagent concentrations. This wide range includes very high values, in the order of tens of G, for several reasons. First, new materials, together with new fabrication processes, show often very high resistance values (in the order of the G) [1–4]. In addition, in order to reduce the power consumption, the measurement of high resistive values is necessary: in fact many sensors are able to operate also for low temperature values, but in this way they show very high resistive values and different selectivity and sensitivity [5]. Microsensor applications and, especially, electronic noses, use several different gas sensors, and an electronic circuit operating on a very wide range is suitable to avoid setting of scaling factors [6–8]. An electronic device, which can contain different kind of gas sensors together with the relative interface circuits and, if necessary, the heating circuits for temperature control

∗

Corresponding author. Tel.: +39 0862 434446; fax: +39 0862 434403. E-mail address: [email protected] (G. Ferri).

0925-4005/$ – see front matter © 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.snb.2007.08.001

of the whole system, is one of the recent targets in this field [9–14]. Oscillating circuits, whose output is very simple to manage, seem the best solution [15–17]. In this case, a R–T conversion is necessary because other kind of interfaces cannot give a wide output range without the use of either scaling factors or high-resolution pico-ammeters [18]. Moreover, sensor signal conditioners with frequency output offer a number of benefits compared to voltage output circuits, such as improved noise immunity and easiness in multiplexing and isolation. Unfortunately sensor behavior is not exactly equal to a pure resistance; for instance, miniaturization processes employed in realization of sensor and of its heating element create parasitic capacitances. The equivalent circuit of the gas resistive sensor appears therefore as the parallel between a resistance and a capacitance, whose value is quite low (few pF) [19,20]. In this model, the equivalent sensor resistance presents values ranging from tens of k up to many G, and the parasitic capacitances, due to the connections and to the sensor itself, must be estimated not to affect the measurement accuracy. Oscillating electronic circuits where sensor is DC-powered have been recently proposed [20]. Its main limit concerns difficulty in designing a compact and full-integrable version of the circuit using standard CMOS technologies [21–23].

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For all of these reasons, we have developed a new oscillating circuit performing the R–T conversion. It is a low-voltage, low-cost and very simple novel interface, completely integrable on silicon with a standard CMOS technology together with the sensors. The proposed solution presents low power consumption and very small dimensions, so making it suitable to be replied on silicon substrate and having the possibility to acquire sensor arrays information. The proposed circuit is able to reveal over six order of magnitude of sensor resistance variation and, moreover, can estimate, with high accuracy, sensor parasitic capacitances up to 50 pF. Experimental measurements, performed with a discrete element board and fabricated with commercial components, have demonstrated the validity of the proposed interface and a good agreement between experimental results and theoretical expectations. Furthermore, the integrated solution has been designed in order to be both independent from temperature drift and powered with low supply voltage, making the circuit suitable for portable applications.

2. The proposed interface for wide-range resistive gas sensors In Fig. 1 the block scheme of the proposed interface is shown. The designed circuit implements a resistance-to-period (R–T) conversion and it is able to estimate, with high precision and excellent linearity, both the sensor resistance, which can vary over a range of a six decades, and the parasitic capacitance of the same sensitive elements, which normally is only few pF. The interface is composed by five main blocks: two comparators, an inverting integrator, an inverting amplifier and an exclusive OR (EX-OR) logic block. The first comparator (Comp1) generates a square-wave voltage signal (VC1 ), whose amplitude is equal to the total supply voltage 2Vcc and whose period is proportional to the sensor resistance RSENS , according to the following expression, under the hypothesis of RSENS and CSENS being constant during the measuring time:

Fig. 2. Voltage levels generated by active blocks.

   CSENS TC = 4GC1 RSENS 1 − GC1

(1)

where G is the ratio between R2 and R1 , typically lower than 1. In Eq. (1), if GC1 is designed to be much higher than parasitic sensor capacitance CSENS , the output period TC can be considered as independent from CSENS being: TC = 4GC1 RSENS

(2)

From Eq. (2), it comes that the propose interface shows two degrees of freedom, in particular, C1 and G, to select interface sensitivity. The second comparator (Comp2) and the EX-OR block have been added with the aim to estimate the value of the sensor parasitic capacitance CSENS . The EX-OR gate generates also a square-wave signal, whose duty-cycle depends from CSENS . The whole interface works as follows (Fig. 2 shows the voltage signals at each node of the interface under the hypothesis of RSENS and CSENS being constant during the shown time): the output voltage of the first comparator (VC1 = ±Vcc ) represents both the periodic signal, from which it is possible measure the

Fig. 1. Block scheme of the proposed interface.

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period, and the input signal for three other blocks (inverting integrator, inverting amplifier and EX-OR). Then, this voltage signal is attenuated by G factor (G < 1) and successively applied to the inverting node of the same Comp1, so, the voltage reference VT can assume only two values: ±GVcc . The voltages ± Vcc are integrated by inverting integrator, which generates a rising ramp, when VC1 = −Vcc and a falling ramp, if VC1 = +Vcc . This signal VR is compared with the voltage reference VT , by Comp1, so generating, at Comp1 output, the square-wave voltage VC1 whose period TC is proportional to RSENS and depends also from CSENS value, according to Eq. (1). The presence of the sensor parasitic capacitance, CSENS , involves a charge transfer, which affects instantaneously the ramp signal when there is the voltage commutation, through a vertical edge on VR , as shown in Fig. 2. The second comparator (Comp2) allows separating the ramp signals in two different parts: the first, immediately after the commutation, presents the charge transfer effect due to the presence of the CSENS , while the second part depends only from RSENS . More in detail, the EX-OR logic block generates a square-wave signal which allows estimating both CSENS and RSENS values, according to the following expressions: RSENS

TC2 + TC4 = 2GC1

CSENS = GC1

TC2 + TC4 − TC1 − TC3 2TC2 + 2TC4

(3) (4)

The sensor components estimation can be affected by Op-amp non-idealities, in particular a finite slew-rate (SR), a non-zero input voltage offset, a finite open loop voltage gain, etc. (see Sections 3 and 5). For these reasons, a suitable choice of active components or, in the case of integrated circuits, an opportune internal design has been done. 3. Error analysis on the circuit In this paragraph we present a detailed analysis of the possible errors which affect the measurements, due to non-idealities

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of real components. As will be clarified in the following, the circuit in Fig. 1 has been slightly modified by inserting a diodes voltage limiter at the comparator Comp1 output and a voltage follower just before the sensor, as shown in Fig. 3. In fact, in order to achieve a good symmetry between the two values of the comparator Comp1 output, a voltage limiting circuit, simply based on two diodes has been introduced. This is an important issue, because this signal becomes the sensor excitation voltage and generally sensors could show different resistance values if they are supplied with different voltages. With this solution, the sensor supply voltage switches between a positive and a negative voltage whose value is the diode forward voltage (about 0.65 V). Another practical problem comes from sensor location during experimental tests. The sensor is usually positioned in a measuring chamber and it is connected to the circuit by shielded cables; the cables could have capacitive effects which may slow the commutation of the comparator Comp1. In order to limit this effect, the voltage follower, Buffer, has been inserted. In conclusion, the following uncertainty sources are taken into account: - the sensor excitation voltage, VC1b ; it does not switch between +Vcc and −Vcc , but varies between +Va e −Vb , where Vb = Va (1 + δ) and δ = (Vb /Va − 1); - the input bias current, Ibias , of the inverting integrator; its effect can be very important, especially for high RSENS values; - the input offset voltage, Vos , of the inverting integrator; it could be significant with respect to Va ; - the input offset voltage, n, of second comparator (Comp2); this effect, if considered as the only uncertainty source, is automatically compensated through the use of Eqs. (3) and (4); - the time delay of Comp1, Tcp , when its output switches from negative to positive values; - the time delay of Comp1, Tcn , when its output switches from positive to negative values; - the time delay of Comp2, T0p , when its output switches from negative to positive values;

Fig. 3. Scheme of the analyzed and experimentally tested circuit.

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- the time delay of Comp2, T0n , when its output switches from positive to negative values. - the time delay of the diode/voltage follower stage, Tep , during the commutation from the negative value to the positive one; - the time delay of the diode/voltage follower stage, Ten , during the commutation from the positive value to the negative one. If, according to Fig. 2, we call TC1 the time of the falling ramp signal from Va to “zero” (“zero” = n), TC2 the time of the falling ramp signal from “zero” to −Vb , TC3 the time of the rising ramp signal from −Vb to “zero” and TC4 the time of the rising ramp signal from “zero” to Va , it is possible to obtain the detailed expression of TC1 , TC2 , TC3 and TC4 , as follows: TC1 = C1 GRSENS

1 + δ − n/GVa − (2 + δ)CSENS /C1 G + (1 + δ)Tcp + Tep /C1 GRSENS + (Tcp + Tep )(Ibias RSENS + Vos )/Va C1 GRSENS + T0n 1 − Ibias RSENS + Vos /Va

TC2 = C1 GRSENS TC3 = C1 GRSENS

1 + n/GVa + Tcn − T0n 1 − Ibias RSENS + Vos /Va

(5)

(6)

1 + n/GVa − (2 + δ)CSENS /C1 G + Tcn + Ten /C1 GRSENS − (Tcn + Ten )(Ibias RSENS + Vos )/Va C1 GRSENS + T0p 1 + δ + Ibias RSENS + Vos /Va

TC4 = C1 GRSENS

1 + δ − n/GVa + Tcp − T0p 1 + δ + Ibias RSENS + Vos /Va (8)

We can easily measure only TC1 , TC2 , TC3 and TC4 , so these four equations show fifteen unknown parameters (C1 , G, RSENS , CSENS , Va , δ, Ibias , Vos , n, Tcp , Tcn , T0p , T0n , Tep , Ten ). Some considerations must be done. As first, the integrator input offset voltage Vos is always divided by Va and added to term RSENS Ibias /Va ; Va ∼ 0.7 V so its effect can be easily set to CSENS =

Fig. 4. Picture of the realized prototype.

Obviously RSENS and CSENS expressions are independent from n and Ibias value. It is important to underline that Eqs. (9) and (10) allow computing RSENS and CSENS values by the knowledge of measured times and device delay times, together with C1 and G values. If we suppose Tcp ≈ T0p ≈ Tp and Tcn ≈ T0n ≈ Tn then Eqs. (9) and (10) can be simplified as follows: RSENS =

TC1 TC4 + TC2 TC3 + 2TC2 TC4 + Tep TC2 + Ten TC4 C1 G(TC1 + TC2 + TC3 + TC4 + Tep + Ten ) (11)

C1 G(Tp (TC1 + TC2 + Ten ) + Tn (TC3 + TC4 + Tep ) + TC2 TC4 − TC1 TC3 + Tep TC2 + Ten TC4 + Tep Ten ) TC1 TC4 + TC2 TC3 + 2TC2 TC4 + Tep TC2 + Ten TC4

a small fixed value. On the contrary, as RSENS could be in the order of tens of G and Ibias could strongly increase according to temperature, term RSENS Ibias /Va could be more significant. Term δ depends on differences between positive and negative voltage swing from rail; in fact different currents in diodes produce small differences in forward voltage values. If operational amplifier characteristics are known, term δ can be considered small, fixed and known. If term δ = 0 then comparator input offset n can hardly affect CSENS estimation. Device delays also affect CSENS estimation, but, for instance, comparators can be supposed to be similar, so Tcp ≈ T0p and Tcn ≈ T0n . For these reasons we choose to solve the mathematical system and to extract RSENS , CSENS , n and Ibias from Eqs. (5)–(8). In the following, the expression of RSENS , CSENS are shown:

(7)

(12)

If we consider only light asymmetries, that is TC1 + TC2 + Ten ≈ ␣ − ␧ and TC3 + TC4 + Tep ≈ ␣ + ␧, Eq. (11) can be modified according to Eq. (13) which demonstrates that Eq. (3) is a good approximation. RSENS =

TC2 + TC4 ␧ TC2 − TC4 + 2C1 G ␣ 2C1 G

(13)

On the contrary, simplified Eq. (4) to compute CSENS cannot be considered as a good approximation of Eq. (12), especially if measured times TC1 , TC2 , TC3 , TC4 and their differences are in the same order of magnitude of device delay times Tp , Tn , Tep , Ten . Only if RSENS value is rather high to neglect device delay times and we consider only light asymmetries, then Eq. (4) can be used instead of Eq. (12).

RSENS =

(T0p − Tcp )(TC1 + TC2 + Ten ) + (T0n − Tcn )(TC3 + TC4 + Tep ) + TC1 TC4 + TC2 TC3 + 2TC2 TC4 + Tep TC2 + Ten TC4 C1 G(TC1 + TC2 + TC3 + TC4 + Tep + Ten )

(9)

CSENS =

C1 G(T0p (TC1 + TC2 + Ten ) + T0n (TC3 + TC4 + Tep ) + TC2 TC4 − TC1 TC3 + Tep TC2 + Ten TC4 + Tep Ten ) (T0p − Tcp )(TC1 + TC2 + Ten ) + (T0n − Tcn )(TC3 + TC4 + Tep ) + TC1 TC4 + TC2 TC3 + 2TC2 TC4 + Tep TC2 + Ten TC4

(10)

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Table 1 Mean value (MEAN) and standard deviation (STD) computed over 100 readout RSENS (M)

MEAN (M)

STD (M)

0.1 0.47 1 4.7 10 20 100 300 500 1000 2000

0.103 0.475 1.015 4.744 10.098 20.266 101.345 304.978 506.230 1007.713 2029.098

0.002 0.001 0.005 <1 k 0.003 <1 k 0.001 0.002 0.004 0.690 0.469

4. Prototype experimental results The realized prototype picture, according to the scheme in Fig. 3, is shown in Fig. 4. For the operational amplifiers, three low power devices (TLC251 from Texas Instruments) have been used, while two general purpose devices (␮A741 from Texas Instruments) have been employed as the comparators. 1N4148 diodes and HCF4070BE EX-OR gate from ST have been also used. The circuit is supplied with a ±4 V voltage, while the R1 –R2 ratio has been chosen in order to obtain a gain factor G of about 2. The integrator capacitance C1 is 100 pF. Times have been measured by a 8-bit microcontroller PIC18F452 with a time resolution of 200 ns. The following experimental results have been obtained using commercial 1% high-value resistors (from 100 k to 2 G) and 5% capacitors (from 1 to 47 pF) to simulate the sensor behavior. First, a set of measures using only resistors has been obtained, while, subsequently, different capacitors have been used in parallel to the 1 G resistors to evaluate the capacitance estimation feature. The measure time is about 1 s and a series of 100 measures has been taken for each resistor–capacitor combination. Table 1 reports the mean value and the standard deviation related to the resistance estimation. For the linearity evaluation, the Least Mean Square line is not the best linear approximation of the input–output characteristic because of the wide input range (more than four orders of magnitude) and the logarithmic distribution of samples. In fact, low resistances always present a small absolute error if compared with high ones, therefore they

Fig. 5. CSENS estimation and Least Mean Square line.

do not contribute to LMS minimization process. To better fit experimental results over a wide range, the so called Weighted Least Mean Square line, which minimizes the relative error, is considered as the linear approximation of the input–output characteristic. The maximum error related to such a line is less than 0.4% over the whole considered resistance range. Fig. 5 shows the Least Mean Square line related to the capacitance estimation. The linearity has been evaluated in about 0.6 pF that is about 1.3% of full scale, whereas the standard deviation is less than 0.03 pF over the whole considered capacitance range (0–47 pF). The circuit behavior has been furthermore evaluated using a real sensor taken as an example (a Metal-Oxide Sensor based on MoW). This kind of sensor needs to be heated to a suitable temperature in order to properly work, therefore an external power supply has been used to drive the sensor heater. Sensor resistance strongly depends on the sensor temperature and, as a consequence, on the power furnished to the heater. In this experiment, the sensor heater has been driven with different voltages in order to achieve a set of working temperatures; the sensor resistance RSENS and the sensor capacitance CSENS has been monitored with the proposed circuit. Fig. 6 shows how RSENS and CSENS vary when heater voltage, and therefore heather power, is suddenly varied. CSENS variation, depicted in Fig. 6b, is very noisy in correspondence of sudden heater power variation, yielding to negative values. Fig. 7 shows a zoom of RSENS and CSENS behavior when heater power is varied from 170 to 206 mW. CSENS noise, that causes CSENS standard deviation to increase from 0.01 up to 0.15 pF, occurs during a sudden RSENS variation; in fact CSENS estimation works properly only if resistance is stable during the whole ramp, that is the ramp is perfectly linear.

Fig. 6. RSENS (6a) and CSENS (6b) behavior when heater power is varied.

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Fig. 7. RSENS and CSENS behavior when heater power is varied from 170 to 206 mW.

In conclusion, CSENS estimation is very accurate when sensor is in a steady state; otherwise, if sudden variations occur, CSENS estimation must be heavily filtered. 5. Integrated solution in a standard CMOS technology The interface presented in this paper has been also designed, at transistor level, in a standard CMOS technology (AMS 0.35 ␮m) in order to implement a completely on siliconintegrated solution. It should be underlined that no external components (resistors, capacitors, . . .) are required in the proposed integrated solution, being suitable for very compact applications. In this case, the main non-idealities of the implemented active components have been taken into account, in particular the finite slew-rate value and the non-zero input voltage offset of the amplifiers. Internal circuit topologies have been developed in order to obtain better performances and to operate at reduced supply voltage (±1 V) with low power consumption (few mW). The active blocks used as amplifiers have been implemented by operational transconductance amplifiers (OTA). Through simple calculations, it is possible to evaluate both the relative error, due to input voltage offset of the inverting integrator, and the absolute error, owed by finite OTA SR value of the amplifiers used as comparators. Both these errors affect the output voltage signal measurement on the first comparator, according to the following expressions: eOFF = eSR =

VOFF V0 + VOFF

4V0 SR

Fig. 8. OTA schematic at transistor level.

mented: the generated current is independent both from supply voltage variation (e.g. battery discharge) also for relatively high variation respect to the nominal value (also higher than 20%), and from temperature drifts of the whole circuit. This current reference needs of a “start-up” circuit, which allows to operate in the correct non-zero operating point [24]. In order to optimize the interface performances, in particular errors and power consumption, each of the four OTA has been separately designed, choosing different transistors sizes, even if the same internal topology, depicted in Fig. 8, has been utilized. Fig. 9 shows the transistor level implementation of the EX-OR logic function. It shows a very low power dissipation (<50 ␮W).

(14) (15)

the last error being expressed in seconds. As it shown in Eq. (15), the absolute error due to the finite SR introduces an error very high in the case of low values of RSENS . In Fig. 8, the internal topology of each employed OTA is shown. This circuit is formed by a double stage: the first stage (input stage) is a symmetrical OTA, while the second stage (output stage) is an AB-class inverter amplifier, in a cascoded push–pull configuration, allowing to obtain full dynamic output range. For what concerns the biasing of the circuit, a current reference generator, based on VTH (threshold voltage of the MOS transistor) has been imple-

Fig. 9. EX-OR schematic at transistor level.

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Fig. 10. Output voltage levels of each active block (RSENS = 100 G, CSENS = 0 pF).

Post-layout simulations have been conducted on the designed CMOS integrated interface, confirming the very high dynamic range and an excellent agreement with the theoretical expectations. In particular, from time domain simulations, it has been possible to calculate RSENS and CSENS values and to compare the simulated results on the values of periods, as shown in Table 2, with the theoretical ones, neglecting the sensor parasitic

capacitance CSENS . Simulation results have confirmed both the theoretical expectations and the experimental results on discrete elements board, showing a good linearity and a correct functionality of the proposed interface, for more than seven decades of sensor resistance variation. Post-layout simulation results do not show limits for very high sensor resistance values, except for the fact that a long measure time occurs.

Fig. 11. Output voltage levels of each active block (RSENS = 100 G, CSENS = 10 pF).

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Table 2 Post-layout simulation results, period estimation Operating temperature = 27 ◦ C

RSENS () [CSENS = 0 F]

Theoretical period (s) 1.8 ␮ 3.6 ␮ 18 ␮ 36 ␮ 180 ␮ 360 ␮ 1.8 m 3.6 m 18 m 36 m 180 m 360 m 1.8 3.6 18 36 180

5k 10 k 50 k 100 k 500 k 1M 5M 10 M 50 M 100 M 500 M 1G 5G 10 G 50 G 100 G 500 G

Simulated period (s)

Relative error (%)

2.15 ␮ 4.04 ␮ 18.73 ␮ 36.84 ␮ 180.87 ␮ 360.42 ␮ 1.7945 m 3.5860 m 17.913 m 35.819 m 179.06 m 358.10 m 1.7904 3.5808 17.904 35.808 179.04

+19.44 +12.22 +4.06 +2.33 +0.48 +0.12 −0.31 −0.39 −0.48 −0.50 −0.52 −0.53 −0.53 −0.53 −0.53 −0.53 −0.53

Table 3 Simulation results at different operating temperatures Operating temperature (◦ C)

−50 −20 0 27 50 70 90 100 105 110

RSENS = 500 M theoretical period = 180 ms

RSENS = 50 G theoretical period = 18 s

Simulated period (s)

Relative error (%)

Simulated period (s)

Relative error (%)

179.3044 m 179.2315 m 179.1845 m 179.1205 m 179.0702 m 179.0242 m 178.9840 m 178.9663 m 178.9579 m 178.9522 m

−0.386 −0.427 −0.453 −0.489 −0.517 −0.542 −0.564 −0.574 −0.579 −0.582

17.9917 17.9846 17.9800 17.9740 17.9698 17.9753 18.0932 18.5108 19.2006 21.0181

−0.046 −0.086 −0.111 −0.144 −0.168 −0.137 +0.518 +2.84 +6.67 +16.77

In Table 3, simulation results concerning the circuit behavior at different operating temperature, ranging from −50 ◦ C up to +110 ◦ C, are reported. Table 4 shows the sensor resistance and parasitic capacitance estimation from integrated circuit simulations, determined from ideal Eqs. (3) and (4). Moreover, Figs. 10 and 11 show the output voltage signals, generated by each active block which implements the interface, considering only RSENS and RSENS in parallel to CSENS , respectively. Table 4 Sensor resistance and parasitic capacitance estimation from integrated circuit simulations RSENS () value [CSENS = 10 pF] 100 k 1M 10 M 100 M 1G 10 G 100 G

RSENS () calculated from simulations and Eq. (3)

CSENS (pF) calculated from simulations and Eq. (4)

96.14 k 0.957 M 9.61 M 96.36 M 0.965 G 9.66 G 96.66 G

8.08 8.58 9.03 9.61 9.74 9.83 10.08

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Biographies Giuseppe Ferri received the “laurea” degree in Electronic Engineering in 1988. Since 1991 he has been a researcher and since 2001 he has been an associate professor in Electronics at the Department of Electrical Engineering of L’Aquila University, Italy. His research activity is actually centred on the analog design of integrated circuits for portable applications (e.g., sensors and biomedicals) and circuit theory. He is co-author of a book entitled “Low Voltage, Low Power CMOS Current Conveyors”, Kluwer ed. (2003) and four text-books in Italian on Analogue Microelectronics (2005, 2006). Moreover, he is author and co-author of more than 220 scientific papers on International Journals and about 150 talks at national and international conferences. He is an IEEE senior member. Vincenzo Stornelli was born in Avezzano (AQ), Italy. He received the Electronic Engineering degree (cum laude) in July 2004. In October 2004 he joined the Department of Electronic Engineering, University of L’Aquila, where he is actually involved with problems concerning project and design of integrated circuits for RF, biomedical and sensor applications, physics-based simulation, CAD modeling characterization and design analysis of active microwave components, circuits, and subsystems. His research interests also include several topics in computational electromagnetic, including microwave antennas analysis for outdoor UWB applications. He regularly teaches courses of the European Computer patent and is a consultant for the R&D laboratory of Thales Italia. Andrea De Marcellis was born in Giulianova (TE), Italy, in 1980. In 2005 he graduated in Electronic Engineering at the University of L’Aquila, Italy. Since November 2005 he was a PhD student in Microelectronics at the Department of Electronic Engineering of the University of L’Aquila. His main research activity concerns the signal conditioning for portable integrated applications and the design of analog electronic integrated circuits, in particular for sensor signal processing, CAD modelling of active devices. Alessandra Flammini was born in Brescia, Italy, in 1960. She graduated with honors in Physics at the University of Rome, Italy, in 1985. From 1985 to 1995 she worked on industrial research and development on digital drive control. From 1995 to 2003 she was a researcher at the Department of Electronics for Automation of the University of Brescia, and since 2002 she has been an associate professor. She teaches several courses about measurements in industrial environments, digital electronics and microprocessor-based systems. Her main research activity is the design of methods and digital electronic circuits for numeric measurement instrumentation, sensor signal processing, smart sensor networking and fieldbus applications, with particular attention to Real-time Ethernet protocols. Alessandro Depari was born in Breno (BS), Italy, in 1976. In 2002 he graduated in Electronic Engineering at the University of Brescia, Italy. He obtained his PhD degree in Electronic Instrumentation in 2006 at the University of Brescia. His main activity is the signal conditioning and processing for sensor arrays and the development of sensor networks for distributed measurement.