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Novel IC metallization test structures for drop-in process monitors
back surface inversion play important roles in controlling leakage in SOS devices. A strategy for rule verification shrinks LSI layouts CLARK BECK and STEVE HARDY Electronics 141 (15 December 1983) Product-specific design rules cut die size; automated approach assigns optimal alignment aids
Parametric test system update PETER H. SINGER Semiconductor Int. 84 (September 1983) Programmable parametric test systems are used for the evaluation of test patterns for process control and device characterization in integrated circuit manufacturing operations. Structural characterization of processed silicon wafers PETER L. FEJES, H. MING LIAW and F. SECCO D'ARAGONA I E E E Trans. Components H)'brids Mfg Tcchnol. Chmt6 (3), 314 (September 1983) Two techniques, chemical etching and X-ray diffraction, for the characterization of process-induced defects in silicon wafers are illustrated. The types of etchants used to reveal various defects are reviewed. The use ofa Lang camera for the measurements of bulk defects and mechanical stress in silicon wafers is presented. Examples are given demonstrating the use of these two techniques to monitor the type and density of defects as well as wafer stress in several key steps during wafer processing. Process-induced defects which limit the device yield are also presented. Novel IC metallization test structures for drop-in process monitors RICHARD SPENCER SolidSt. Tcchnol. 201 (September 1983) Two unique test structures are described which allow the acceptability of metal layers on an integrated circuit to be monitored. These structures provide a statistically significant amount of information while consuming a minimum area, and require only a de measurement capability to be effective. The modular design used is consistent with a probe-pad array approach. The test patterns are most useful for drop-in type process monitors, although the concept could be applied to larger structures as well. The structures have been layed out for both an NMOS and an ECL bipolar process, and initial testing indicates that they perform as intended.
Failure physics of integrated circuits - a review N. D. STOJADINOVIC Microelectron. Reliab. 23 (4), 609 (1983) This paper is a review of the most important results on failure physics of integrated circuits, as a synthesis of what has been recently encountered in the literature concerned with these problems.
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In the first part of the paper systematization of failure modes in integrated circuits is accomplished so that all failure modes are divided into four gropups according to their origin. Also, some typical failure mode distributions of different types of integrated circuits are given and the effects of the changeover from LSI to VLSI on fai!ure mode distributions are discussed. In the second part of the paper the most important tests for enhancing of the failure modes are enumerated and relationship between the failure modes and the tests for their detection is given. In the third part of the paper a survey of test structures for failure analysis of integrated circuits is made. Test structures are divided into three groups according to the kind of the failure mode tested by them. First the test structures for the analysis of the failures due to the process induced defects are described. Then, the test structures for the analysis of the failures due to traps at the interface silicon-oxide and mobile alcali ions in oxide are discussed. Finally, the test structures for the analysis of the metallization failures are considered.
An anal)ileal method for determining intrinsic drain/ source resistance of lightly doped drain (LDD) devices C H A R V A K A DUVVURY, DAVE BAGLEE, MICHAEL DLIANE, ADIN tIYSLOP, MICHAEL SMAYLING and MIKE M A E K A W A Solid St. Electron. 27 (1), 89 (1984) MOS devices with double diffusion junctions containing Lightly Doped Drain/Source (LDD) regions have been built and analyzed. Comparison of current characteristics of the 2 ttm LDD devices with conventional devices of same channel length indicates that the LDD devices, while displaying relatively good drain current gain, deviate from the MOS transistors in the linear region due to the intrinsic n drain/source resistance and thus have lower substrate current due to the reduced hot electron effects. An analytical method is developed where this intrinsic resistance can be extracted from curve fitting of/Vdata. Through curve fitting analysis the intrinsic resistance parameter is found to be an inverse function of transistor width as well as being dependent on temperature in the usual T ~ manner.
Parametric test system update PETER H. SINGER Semiconductor Int. 84 (September 1983) Programmable parametric test systems are used for the evaluation of test patterns for process control and device characterization in integrated circuit manufacturing operations. Structural characterization of processed silicon wafers PETER L. FEJES, H. MING LIAW and F. SECCO D'ARAGONA I E E E Trans. Components H)'brids Mfg Tcchnol. Chmt6 (3), 314 (September 1983) Two techniques, chemical etching and X-ray diffraction, for the characterization of process-induced defects in silicon wafers are illustrated. The types of etchants used to reveal various defects are reviewed. The use ofa Lang camera for the measurements of bulk defects and mechanical stress in silicon wafers is presented. Examples are given demonstrating the use of these two techniques to monitor the type and density of defects as well as wafer stress in several key steps during wafer processing. Process-induced defects which limit the device yield are also presented. Novel IC metallization test structures for drop-in process monitors RICHARD SPENCER SolidSt. Tcchnol. 201 (September 1983) Two unique test structures are described which allow the acceptability of metal layers on an integrated circuit to be monitored. These structures provide a statistically significant amount of information while consuming a minimum area, and require only a de measurement capability to be effective. The modular design used is consistent with a probe-pad array approach. The test patterns are most useful for drop-in type process monitors, although the concept could be applied to larger structures as well. The structures have been layed out for both an NMOS and an ECL bipolar process, and initial testing indicates that they perform as intended.
Failure physics of integrated circuits - a review N. D. STOJADINOVIC Microelectron. Reliab. 23 (4), 609 (1983) This paper is a review of the most important results on failure physics of integrated circuits, as a synthesis of what has been recently encountered in the literature concerned with these problems.
50
In the first part of the paper systematization of failure modes in integrated circuits is accomplished so that all failure modes are divided into four gropups according to their origin. Also, some typical failure mode distributions of different types of integrated circuits are given and the effects of the changeover from LSI to VLSI on fai!ure mode distributions are discussed. In the second part of the paper the most important tests for enhancing of the failure modes are enumerated and relationship between the failure modes and the tests for their detection is given. In the third part of the paper a survey of test structures for failure analysis of integrated circuits is made. Test structures are divided into three groups according to the kind of the failure mode tested by them. First the test structures for the analysis of the failures due to the process induced defects are described. Then, the test structures for the analysis of the failures due to traps at the interface silicon-oxide and mobile alcali ions in oxide are discussed. Finally, the test structures for the analysis of the metallization failures are considered.
An anal)ileal method for determining intrinsic drain/ source resistance of lightly doped drain (LDD) devices C H A R V A K A DUVVURY, DAVE BAGLEE, MICHAEL DLIANE, ADIN tIYSLOP, MICHAEL SMAYLING and MIKE M A E K A W A Solid St. Electron. 27 (1), 89 (1984) MOS devices with double diffusion junctions containing Lightly Doped Drain/Source (LDD) regions have been built and analyzed. Comparison of current characteristics of the 2 ttm LDD devices with conventional devices of same channel length indicates that the LDD devices, while displaying relatively good drain current gain, deviate from the MOS transistors in the linear region due to the intrinsic n drain/source resistance and thus have lower substrate current due to the reduced hot electron effects. An analytical method is developed where this intrinsic resistance can be extracted from curve fitting of/Vdata. Through curve fitting analysis the intrinsic resistance parameter is found to be an inverse function of transistor width as well as being dependent on temperature in the usual T ~ manner.