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Novel IC metallization test structures for drop-in process monitors
814
World Abstracts on Microelectronics and Reliability
has the capability of handling high power integrated circuits (IC's).
configuration with 4-~m design rules yields the same density as 2.5-1~m rules do.
A data-base for IC mask making. N. N. KUNDU, S. N. GUPTA, A. K. BAGCHI, D. R. NAGPAL, A. V. RAMANI and W. S. KHOKLE.Microelectron. J. 14 (5), 43 (1983). Photomasks are very important in the manufacturing of integrated circuits and should be of very high quality with low defect density and very good edge definition. A photomask fabrication process involves various photo-imaging, processing, measurement and quality control steps. The complexity and sophistication of the process requires that either the operator be extremely skilled and conversant with all the process steps involved as per requirements of a given set of masks or that the entire process be computerized. CEERI has developed a data-base for the complete processing of emulsion and hard surface masks. This has been generated using the IMAGE 1000 software of a H P 1000 computer system and describes each process step such as, exposing with pattern generator, image repeater and contact printer. Several mask processing procedures, critical dimension measurements and quality control steps have also been included. In fact, depending on the job requirements, the operator can simply enter all parameters through the query system of the data-base, which can be conveniently listed either on hard copy or on a terminal for setting up various work stations and process steps of mask making. In this paper, this data-base has been described with its advantages and practical usage.
Rapid wafer heating: status 1983. PlETER S. BURGGRAAF. Semiconductor Int. 70 (December 1983). To date, rapid wafer heating appears to be emerging as a viable technique for several production wafer-fabrication processes. Initially used for evaluating ion-implantation processes, this fast developing technique may also prove useful for silicide formation, glass reflow and other wafer-heating process steps.
Electrical design of a high speed computer packaging system. EVAN E. DAVIDSON. IEEE Trans. Components Hybrids Mfq Technol. Chmt-6 (3), 272 (September 1983). A methodology for optimizing the design of an electrical packaging system for a high speed computer is described. The pertinent parameters are first defined and their sensitivities are derived so that the proper design trade-offs can ultimately be made. From this procedure, a set of rules is generated for driving a computer-aided design (CAD) system. Finally there is a discussion of design optimization and circuit and package effects on machine performance. Novel IC metallization test structures for drop-in process monitors. RICHARD SPENCER. Solid St. Technol. 201 (September 1983). Two unique test structures are described which allow the acceptability of metal layers on an integrated circuit to be monitored. These structures provide a statistically significant amount of information while consuming a minimum of area, and require only a d c measurement capability to be effective. The modular design used is consistent with a probe-pad array approach. The test patterns are most useful for drop-in type process monitors, although the concept could be applied to larger structures as well. The structures have been layed out for both an NMOS and an ECL bipolar process, and initial testing indicates that they perform as intended. A re-examination of practical performance limits of scaled n-channel and p-channel MOS devices for VLSI. H1SASH1 SHICHDO. Solid-St. Electron. 26 (10), 969 (1983). The device performance of scaled n-channel and p-channel MOS devices is theoretically examined in detail down to 0.2gm gate length including all of the major effects such as source/drain series resistance, mobility degradation due to both parallel and perpendicular fields, and inversion layer capacitance under three different power supply scenarios. From the degradation factor of triode gain and drain saturation current, the relative contribution of each parasitic effect on device performance degradation has been examined. Based on these calculations, some modifications to straightforward scaling are considered. C-MOS process reduces chip size as much as a third. JOHN GOSCH. Electronics 87 (12 January 1984). Zero-clearance
IC wafer fab economics and lithography equipment selection: the inextricable link. PETER DISESSA. Solid St. Technol. 155 (December 1983). IC wafer fab economic and performance gains during the remainder of this decade will continue to be principally derived from the premiere IC production equipment decision; that is, the selection of the optimal lithography tool, or tool mix. The major treatment herein addresses the economic relationships when evaluating such a decision. The discussion illustrates the lithography functional and operational factors as they impact wafer manufacturing costs and what logically must be viewed as the ultimate IC wafer fab productivity criterion : fab cost/good die out. To accomplish this, a step-by-step overview is introduced that can serve as a guideline and aid in providing a clearer approach to a complex and confusing decision-making process. Analysis of leakage currents in CMOS/SOS devices. K. VASUDEV. Microelectron. J. 14 (6), 45 (1983). Understanding the origin and mechanism of leakage currents in CMOS/SOS transistors constitutes an important step towards the advancement of SOS technology for VLSI applications. In this letter, the bias and geometrical dependence of both n- and p-channel transistors has been analysed in detail. These variations have been correlated with independent lifetime measurements, which indicate that both bulk generation and back surface inversion play important roles in controlling leakage in SOS devices. Technique for measuring the moisture content of sealed IC packages. CHARLES H. WINDISCH, JR. and ROBERT P. MERRETT. Semiconductor Int. 80 (December 1983). This method uses the integrated circuit die as a sensor to measure the water content of a ceramic dual inline package. Real time sputter deposition monitoring using glow discharge mass spectroscopy. B. F. T. BOLKER. Solid St. Technol. 115 (December 1983). Because all vacuum systems contain some impurity gases, all sputtering can be viewed as reactive due to these virtual leaks. When a precise amount of a reactive gas like N 2 or Og is required to achieve critical film properties, some method is needed to reproducibly control these sputtering gases. Glow discharge mass spectroscopy is a closedloop, real-time control method that provides such control. The glow discharge mass spectroscopy (GDMS) apparatus consists of a mass spectrometer and an ion lens which is coupled with a microprocessor and provides feedback control for a servo leak valve. G D M S system design and hardware are presented, and comparisons are given between GDMS spectra and resultant film properties. Considerations for achieving optimum real time control of reactive gas leaks are discussed. C H M O S improves system efficiency. JOSEPH ALTNETHER. Electron. Power, 57 (January 1984). Although accepted as the semiconductor technology best suited to low-powerconsumption applications, the efficiency of the CMOS process may be questioned on the grounds of its fabrication complexity, low speed and low function density. The cross breeding of CMOS with HMOS promises to overcome these problems.
Die bonding and package sealing materials. PETER H. SINGER. Semiconductor Int. 62 (December 1983). Conductive epoxies,
World Abstracts on Microelectronics and Reliability
has the capability of handling high power integrated circuits (IC's).
configuration with 4-~m design rules yields the same density as 2.5-1~m rules do.
A data-base for IC mask making. N. N. KUNDU, S. N. GUPTA, A. K. BAGCHI, D. R. NAGPAL, A. V. RAMANI and W. S. KHOKLE.Microelectron. J. 14 (5), 43 (1983). Photomasks are very important in the manufacturing of integrated circuits and should be of very high quality with low defect density and very good edge definition. A photomask fabrication process involves various photo-imaging, processing, measurement and quality control steps. The complexity and sophistication of the process requires that either the operator be extremely skilled and conversant with all the process steps involved as per requirements of a given set of masks or that the entire process be computerized. CEERI has developed a data-base for the complete processing of emulsion and hard surface masks. This has been generated using the IMAGE 1000 software of a H P 1000 computer system and describes each process step such as, exposing with pattern generator, image repeater and contact printer. Several mask processing procedures, critical dimension measurements and quality control steps have also been included. In fact, depending on the job requirements, the operator can simply enter all parameters through the query system of the data-base, which can be conveniently listed either on hard copy or on a terminal for setting up various work stations and process steps of mask making. In this paper, this data-base has been described with its advantages and practical usage.
Rapid wafer heating: status 1983. PlETER S. BURGGRAAF. Semiconductor Int. 70 (December 1983). To date, rapid wafer heating appears to be emerging as a viable technique for several production wafer-fabrication processes. Initially used for evaluating ion-implantation processes, this fast developing technique may also prove useful for silicide formation, glass reflow and other wafer-heating process steps.
Electrical design of a high speed computer packaging system. EVAN E. DAVIDSON. IEEE Trans. Components Hybrids Mfq Technol. Chmt-6 (3), 272 (September 1983). A methodology for optimizing the design of an electrical packaging system for a high speed computer is described. The pertinent parameters are first defined and their sensitivities are derived so that the proper design trade-offs can ultimately be made. From this procedure, a set of rules is generated for driving a computer-aided design (CAD) system. Finally there is a discussion of design optimization and circuit and package effects on machine performance. Novel IC metallization test structures for drop-in process monitors. RICHARD SPENCER. Solid St. Technol. 201 (September 1983). Two unique test structures are described which allow the acceptability of metal layers on an integrated circuit to be monitored. These structures provide a statistically significant amount of information while consuming a minimum of area, and require only a d c measurement capability to be effective. The modular design used is consistent with a probe-pad array approach. The test patterns are most useful for drop-in type process monitors, although the concept could be applied to larger structures as well. The structures have been layed out for both an NMOS and an ECL bipolar process, and initial testing indicates that they perform as intended. A re-examination of practical performance limits of scaled n-channel and p-channel MOS devices for VLSI. H1SASH1 SHICHDO. Solid-St. Electron. 26 (10), 969 (1983). The device performance of scaled n-channel and p-channel MOS devices is theoretically examined in detail down to 0.2gm gate length including all of the major effects such as source/drain series resistance, mobility degradation due to both parallel and perpendicular fields, and inversion layer capacitance under three different power supply scenarios. From the degradation factor of triode gain and drain saturation current, the relative contribution of each parasitic effect on device performance degradation has been examined. Based on these calculations, some modifications to straightforward scaling are considered. C-MOS process reduces chip size as much as a third. JOHN GOSCH. Electronics 87 (12 January 1984). Zero-clearance
IC wafer fab economics and lithography equipment selection: the inextricable link. PETER DISESSA. Solid St. Technol. 155 (December 1983). IC wafer fab economic and performance gains during the remainder of this decade will continue to be principally derived from the premiere IC production equipment decision; that is, the selection of the optimal lithography tool, or tool mix. The major treatment herein addresses the economic relationships when evaluating such a decision. The discussion illustrates the lithography functional and operational factors as they impact wafer manufacturing costs and what logically must be viewed as the ultimate IC wafer fab productivity criterion : fab cost/good die out. To accomplish this, a step-by-step overview is introduced that can serve as a guideline and aid in providing a clearer approach to a complex and confusing decision-making process. Analysis of leakage currents in CMOS/SOS devices. K. VASUDEV. Microelectron. J. 14 (6), 45 (1983). Understanding the origin and mechanism of leakage currents in CMOS/SOS transistors constitutes an important step towards the advancement of SOS technology for VLSI applications. In this letter, the bias and geometrical dependence of both n- and p-channel transistors has been analysed in detail. These variations have been correlated with independent lifetime measurements, which indicate that both bulk generation and back surface inversion play important roles in controlling leakage in SOS devices. Technique for measuring the moisture content of sealed IC packages. CHARLES H. WINDISCH, JR. and ROBERT P. MERRETT. Semiconductor Int. 80 (December 1983). This method uses the integrated circuit die as a sensor to measure the water content of a ceramic dual inline package. Real time sputter deposition monitoring using glow discharge mass spectroscopy. B. F. T. BOLKER. Solid St. Technol. 115 (December 1983). Because all vacuum systems contain some impurity gases, all sputtering can be viewed as reactive due to these virtual leaks. When a precise amount of a reactive gas like N 2 or Og is required to achieve critical film properties, some method is needed to reproducibly control these sputtering gases. Glow discharge mass spectroscopy is a closedloop, real-time control method that provides such control. The glow discharge mass spectroscopy (GDMS) apparatus consists of a mass spectrometer and an ion lens which is coupled with a microprocessor and provides feedback control for a servo leak valve. G D M S system design and hardware are presented, and comparisons are given between GDMS spectra and resultant film properties. Considerations for achieving optimum real time control of reactive gas leaks are discussed. C H M O S improves system efficiency. JOSEPH ALTNETHER. Electron. Power, 57 (January 1984). Although accepted as the semiconductor technology best suited to low-powerconsumption applications, the efficiency of the CMOS process may be questioned on the grounds of its fabrication complexity, low speed and low function density. The cross breeding of CMOS with HMOS promises to overcome these problems.
Die bonding and package sealing materials. PETER H. SINGER. Semiconductor Int. 62 (December 1983). Conductive epoxies,