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Numerical modeling of Subthreshold region of junctionless double surrounding gate MOSFET (JLDSG)
Superlattices and Microstructures 90 (2016) 8e19
Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Numerical modeling of Subthreshold region of junctionless double surrounding gate MOSFET (JLDSG) Sonam Rewari a, Subhasis Haldar b, Vandana Nath c, S.S. Deswal d, R.S. Gupta a, * a
Department Of Electronics and Communication Engineering, Maharaja Agrasen Institute Of Technology, 110086, New Delhi, India Department Of Physics, Motilal Nehru College, University Of Delhi, 110021, New Delhi, India c University School Of Information and Communication Technology, Guru Gobind Singh Indraprastha University Sector - 16C, Dwarka 110078, New Delhi, India d Department Of Electrical and Electronics Engineering, Maharaja Agrasen Institute Of Technology, 110086, New Delhi, India b
a r t i c l e i n f o
a b s t r a c t
Article history: Received 18 September 2015 Received in revised form 20 November 2015 Accepted 22 November 2015 Available online 30 November 2015
In this paper, Numerical Model for Electric Potential, Subthreshold Current and Subthreshold Swing for Junctionless Double Surrounding Gate(JLDSG) MOSFEThas been developed using superposition method. The results have also been evaluated for different silicon film thickness, oxide film thickness and channel length. The numerical results so obtained are in good agreement with the simulated data. Also, the results of JLDSG MOSFET have been compared with the conventional Junctionless Surrounding Gate (JLSG) MOSFET and it is observed that JLDSG MOSFET has improved drain currents, transconductance, outputconductance, Transconductance Generation Factor (TGF) and Subthreshold Slope. © 2015 Elsevier Ltd. All rights reserved.
Keywords: Junctionless Modeling Double surrounding gate(DSG) MOSFET SCE’s Surrounding gate(SG)
1. Introduction MOSFET size is approaching nanoscale regime. The reduction in device size has led to several problems such as Short Channel Effects (SCE's) and Hot Carrier Effects (HCE's) [1e4]. Multigate transistor such as Double Gate (DG) MOSFET, Triple Gate (TG) MOSFET and cylindrical Surrounding Gate (SG) MOSFET [1e4] are feasible solutions to aforesaid problems. SG MOSFET is one of the best architectures to reduce SCE's as this gate completely surrounds the silicon pillar, thus enhancing gate controllability to a much larger extent. SCE's can further be mitigated by employing cylindrical Double Surrounding Gate (DSG) MOSFET. DSG MOSFET is a double gate architecture employed over a surrounding gate structure. It has two cylindrical gates, one above and one below the silicon film. The higher current drive and lower leakage is also obtained by employing DSG MOSFET apart from improved intrinsic characteristics [5e8]. The improved performance is attributed to the additional inner gate which provides an enhanced control over the channel. Another issue associated with SG MOSFET is the abrupt Source Drain junction formation [9]. This problem can be liquidated by using Junctionless (JLT) MOSFET. In JLT MOSFET source-channel-drain are heavily doped with same type of doping i.e. they are uniformly doped. For n type MOSFET doping is Nþ- Nþ- Nþ and for p type MOSFET it is Pþ- Pþ- Pþ. Thus, there is no abrupt source drain junction formation because of homogeneous doping in source-channel-drain. Also, the thermal budget for manufacturing is significantly reduced as JLT has
* Corresponding author. E-mail addresses: [email protected] (S. Haldar), [email protected] (V. Nath), [email protected] (S.S. Deswal), rsgupta1943@ gmail.com (R.S. Gupta). http://dx.doi.org/10.1016/j.spmi.2015.11.026 0749-6036/© 2015 Elsevier Ltd. All rights reserved.
S. Rewari et al. / Superlattices and Microstructures 90 (2016) 8e19
9
no doping concentration gradients [10]. Junctionless Surrounding Gate (JLSG) MOSFET has reduced short channel effects along with homogeneous doping in source-channel-drain [9].In this article, we propose a Numerical Model for Junctionless Double Surrounding Gate (JLDSG) MOSFET as it helps us to understand device physics. JLDSG MOSFET inculcates advantages of JLSG MOSFET and DSG MOSFET both. By employing JLDSG MOSFET we can reduce SCE's and also eliminate the issue of abrupt Source Drain junction formation. 2. Devicestructure and fabrication issues A 3-D structure of cylindrical JLDSG MOSFET is shown in Fig. 1 a and Fig. 1 b shows the Cutplane view of JDSG MOSFET with two gates, an inner gate GATE1 (below the silicon film) and an outer gate GATE2 (above the silicon film) having same metal gate workfunction using silicon dioxide as dielectric.Both the gates, GATE1 and GATE2 are made up of platinum having the same metal workfunction of 5.56 eV with uniformly doped silicon across source-channel-drain with ND ¼ 1019 cm3 for n type MOSFET, thickness of silicon film tsi ¼ 20 nm, oxide thickness tox ¼ 2 nm, oxide permittivity εox ¼ 3.9 (Fig. 2). ATLAS 3D device simulator has been used for simulations with Shockley-Read-Hall (SRH) recombination model with concentration dependent lifetimes is used to account for minority recombination. The Boltzmann transport model is used as a drift diffusion model. To incorporate the effect of high doping in the channel especially for junctionless transistor, the Band Gap Narrowing (BGN) model has been used in simulation. Concentration dependent mobility model (CONMOB) along with Lombardi CVT model is used because it considers large temperature range with parallel and perpendicular field dependent mobility. Fig. 3(a). shows JLDSG MOSFET with two gates, an inner gate(G1) and outer gate (G2) and Fig. 3(b) shows a single gateJLSG MOSFET on silicon film (tsi ¼ 20 nm). In JLDSG MOSFET the gate action is from two sides, one because of the inner gate (G1) and the other because of the outer gate (G2). Thus, the control of gate over the silicon film is increased in JLDSG MOSFET and the effective gate voltage increases. Fabrication feasibility of CSDG MOSFET has been recently addressed by Hanna et al. [12] and Tekleab et al. [13]. They have successfully fabricated a cylindrical surrounding gate with an inner charge control gate. Their design process flow starts from the oxide mandrel patterning followed by sacrificial and structural spacer formation and then etching and cleaning process are performed. To pattern a shell body a sacrificial pillar structure is patterned followed by dielectric/gate deposition with other processing steps. 3. Numerical model 2-D Poisson's equation in cylindrical coordinates is solved under the appropriate boundary conditions using the superposition method [14] to obtain expressions for Electric potential and Subthreshold Current. 2-D Poisson's equation in cylindrical coordinates is expressed as:
1 v v2 v2 qN ðфðr; zÞÞ þ 2 фðr; zÞ þ 2 фðr; zÞ ¼ D r vr 3 si vr vz
(1)
where ND is the uniform doping concentration, ф(r,z) is the potential distribution in the silicon film. In superposition technique the resultant solution of potential can be decomposed into one dimensional long channel solution (V(r)) which satisfies one dimensional Poisson's equation and two dimensional short channel solution (U(r,z)) which satisfies two dimensional Laplace's equation i.e.
фðr; zÞ ¼ VðrÞ þ Uðr; zÞ
Fig. 1. a. 3-D View of cylindrical JLDSG MOSFET. b. Cut plane View of cylindrical JLDSG MOSFET.
(2)
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Fig. 2. Cross-sectional View of cylindrical JLDSG MOSFET.
Then the Eq. (1) becomes
1 v v2 q ND ðVðrÞÞ þ 2 VðrÞ ¼ r vr 3 si vr
(3)
and
1 v v2 v2 ðUðr; zÞÞ þ 2 Uðr; zÞ þ 2 Uðr; zÞ ¼ 0 r vr vr vz
(4)
The boundary conditions employed for the solution of 2D potential ф(r,z) are:
ðiÞ ф teff ; z ¼ фos ðzÞ
(5)
ðiiÞ ф teff tsi ; z ¼ фis ðzÞ
(6)
vфðr; zÞ ðiiiÞ vr
r¼teff
¼ J Vgs фos ðzÞ
(7)
vфðr; zÞ ðivÞ ¼ J Vgs фis ðzÞ vr r¼teff tsi
(8)
ðvÞ фðr; 0Þ ¼ Vbi
(9)
ðviÞ фðr; LÞ ¼ Vbi þ Vds
(10)
teff¼tm þ tox þ tsi,J ¼ Cεoxsi , Vbi ¼ 0 for JLDSG MOSFET,Cox is obtained by series combination of outer oxide capacitance Coxo and the inner oxide capacitance Coxi. Coxo is represented
Coxo ¼
εox
ðtm þ tox þ tsi Þðtm þ tox þ tsi Þln 1 þ ðtm þttoxox þtsi Þ
(11)
asCoxi is represented as:
Coxi ¼
εox ðtm þ tox Þln 1 þ ttoxm
(11a)
εox is the dielectric permittivity of oxide,фos(z) is the constant potential present at the outer surface, фis(z) is the constant potential present at the inner surface.
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Fig. 3. Effect of gates on silicon film for JLDSG MOSFET and JLSG MOSFET.
The resultant solution of Eq. (3) can be considered as parabolic approximation:
VðrÞ ¼ P0 þ P1 r þ P2 r2
(12)
where qNd tsi d P0 ¼ Vgseff P1 t þ J1 P2 t 2 þ 2t ¼ d t ,P 1 eff J 2 ,P2 ¼ 2, d ¼ εsi ,Vgseff ¼ Vgs Vfb, Vfb is the flat band voltage. The solution of Eq. (4) can be obtained as
Uðr; zÞ ¼
∞ X
J0 ðhn rÞðMn expðhn zÞ þ Nn expðhn zÞÞ
(13)
n¼1
where J0 and J1 are the bessel functions of order 0 and 1 respectively, Mn and Nn are the constants evaluated using boundary conditions (9) and (10) and are given in Appendix, an are the Eigen values of
J1
teff teff Cox ¼ J0 an an εsi an
(14)
The resultant solution can be expressed as:
фðr; zÞ ¼ VðrÞ þ
∞ X
J0 ðhn rÞðMn expðhn zÞ þ Nn expðhn zÞÞ
(15)
n¼1
Where hn ¼ a1n . The Subthreshold current, Isub [14] is given as:-
Isub ¼ 2:R:p:m:k:T:hi :Z 0
1e L
0 B @
q:Vds k:T
1 Z
teff
e 0
фðr;zÞ k:T
(16) 1 dz
C dr A
wherek ¼ 1.38 1023 J/K is the Boltzmann's constant, T ¼ 300 K, hi¼1.45 1010 cm3 is the intrinsic carrier density, m¼1300 cm2/Vs is the electron mobility. The Subthreshold Slope, SS is written as:-
SS ¼
1 d dVgs
logðIsub Þ
(17)
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4. Results and discussion Fig. 4 shows the potential distribution at the center of JLDSG MOSFET for different channel length. It can be clearly observed that as the channel length decreases, minimum central potential rises upwards becauseof the reduction in the charge control linear region which causes the potential to shift towards the source region and so this source potential affects the minimum potential at the center of the channel [15]. The Numerical results so obtained are in good agreement with the simulated results. Fig. 5 shows thepotential distribution at the center of JLDSG MOSFET for different silicon film thickness. It can be clearly observed that as the silicon film thickness increases, minimum surface potential decreases. This is because as silicon film thickness increases, the gate control over the channel gets weakened [16], leading to lowering of surface potential and thus, minimum surface potential. The Numerical results obtained are in good agreement with the simulated results. Fig. 6 shows thepotential distribution at the center of JLDSG MOSFET for various oxide thicknesses. The Numerical results so obtained are in good agreement with the simulated results. Vertical electric field is created due to the presence of oxide layer between the metal and the semiconductor. As oxide thickness increases this vertical electric field is reduced because the gate control over the channel weakens. So, as the oxide thickness increases, minimum surface potential is pulled upwards [16]. Fig. 7.Shows the variation of Subthreshold current with the gate to source voltage for different channel length. It can be noted that as the channel length reduces Ioff current increases. this increase in Ioff current is due to short channel effects (SCE's) which creep in when channel length reduces [15]. The Numerical results so obtained are in good agreement with the simulated results. Fig. 8.Shows the variation of Subthreshold current with the gate to source voltage for different silicon film thickness. It can be noted that as the film thickness increases off current decreases because the gate controllability over the channel decreases [16]. The Numerical results so obtained are in good agreement with the simulated results. Fig. 9. Shows the variation of Subthreshold current with the gate to source voltage for different oxide thickness. It can be noted that as the oxide thickness increases, Subthreshold drain current increases. This is so because in JLSG MOSFET, when thickness of oxide layer increases depletion of electrons becomes difficult because of reduced vertical electric field [16]. The Numerical results so obtained are in good agreement with the simulated results. Fig. 10. Shows the variation of Subthreshold slope with channel length for different silicon film thickness. As the silicon film thickness increases the Subthreshold slope of JLDSG MOSFET degrade and drifts away from the ideal value because the silicon area has increased for larger silicon film thickness and so the gate control over the channel has decreased [15]. The Numerical results so obtained are in good agreement with the simulated results. Fig. 11 shows the variation of Subthreshold slope with channel length for different oxide thickness. It can be noted that as the oxide thickness increases, Subthreshold slope (SS) degrades, this is because of limited impact of gate due to increased oxide thickness [16]. The Numerical results so obtained are in good agreement with the simulated results. 5. JLDSGMOSFET a potential device The simulation of the device has been carried out using the ATLAS 3-D device simulator [11].For a fair comparison between JLSG MOSFET and JLDSG MOSFET the threshold voltage is kept same as 0.25 V by changing the workfunction at L ¼ 18 nm.The
Fig. 4. Potential Distribution along the channel at the center for different Channel Length.
S. Rewari et al. / Superlattices and Microstructures 90 (2016) 8e19
Fig. 5. Potential Distribution along the channel at the center for different silicon film thickness.
Fig. 6. Potential Distribution along the channel at the center for different oxide thickness.
Fig. 7. Subthreshold Current as a function of Gate to Source Voltage in JLDSGMOSFET for different Channel Length.
13
Fig. 8. Subthreshold Current as a function of Gate to Source Voltage in JLDSG MOSFET for different silicon film thickness.
Fig. 9. Subthreshold Current as a function of Gate to Source Voltage in JLDSG MOSFET for different oxide thickness.
Fig. 10. Subthreshold Slope as a function of Channel Length in JLDSG MOSFET for different silicon film thickness.
S. Rewari et al. / Superlattices and Microstructures 90 (2016) 8e19
15
Fig. 11. Subthreshold Slope as a function of Channel Length in JLDSG MOSFET for different oxide thickness.
Table 1 Summarizes the various device structure parameters for JLDSG MOSFET. Parameters
JLDSG MOSFET
JLSG MOSFET
Channel length (nm) Channel doping (/cm3) Silicon oxide thickness (nm) Silicon thickness (nm) Gate work function (eV) Length of S/D (nm)
30,40,50 1 1019 2 10 5.56 15
30,40,50 1 1019 2 10 5.7 15
threshold voltage has been calculated using the linear extrapolation method [18]. In this method, threshold voltage is defined as that gate voltage which is obtained by extrapolating the linear portion of the Ids, versus Vgs, characteristics, from the point of maximum slope, to zero drain current Ids. Note that the point of maximum slope is that point where the transconductance gm ¼ vIds/vVgs is maximum. This threshold voltage is often called the extrapolated Vth. This is the most common method of determining Vth and is the defacto industry standard. The various device parameters have been tabulated in Table 1 for both the devices. Fig. 12. Shows the variation of drain current, Ids with the gate voltage, Vgs Improved drain current has been observed in JLDSG MOSFET over JLSG MOSFET.An improvement of 41.98 times in Ion/Ioff ratio of JLDSG MOSFET has been
Fig. 12. Variation of Drain current with Gate to Source Voltage.
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S. Rewari et al. / Superlattices and Microstructures 90 (2016) 8e19
Fig. 13. Variation of Drain current with Drain to Source Voltage.
observed over JLSG MOSFET.In JLSGMOSFET depletion layer is formed in the channel region because of the vertical electric field created due to the applied gate voltage.Lateral conduction begins through the center of the silicon film as the gate voltage is further increased beyond the flat band voltage (VFB). In JLDSG MOSFET there are two gates, consequently there is an enhanced gate control over the channel leading to larger effective gate voltage.So, two inversion layers are formed in the channel region of JLDSG MOSFET leading to improved drain current, transconductance, output conductance and Subthreshold slope. Thus, higher Ion and lower Ioff have been noted in JLDSG MOSFET over JLSG MOSFET. Fig. 13 shows the variation of drain current with drain to source voltage for different channel lengths (L ¼ 18 nm, 24 nm, 30 nm) for JLSG MOSFET and JLDSG MOSFET. It is seen that as the channel length decreases drain current increases. Due to larger gate control over the channel higher drain currents have been observed in JLDSG MOSFET for all the channel lengths. Fig. 14 illustrates the variation of transconductance, gm with the gate voltage. Transconductance (gm) governs the gain of a device and peak value directs higher cut off frequency [17]. So, a higher value of transconductance is always desirable. As the drain current is improving for different gate voltages in JLDSG MOSFET over JLSG MOSFET, gm is also improving. An improvement in gm of JLDSG MOSFET by 1.82 times for channel length L ¼ 18 nm, 2.098 times for L ¼ 24 nm and 2.23 times for L ¼ 30 nm over gm of JLSG MOSFET has been observed. Transconductance Generation Factor(TGF) of any device at a fixed drain voltage depicts the ability to convert the dc power into ac gain and is defined as TGF can be defined as:
Fig. 14. Variation of Transconductance with gate to source voltage.
S. Rewari et al. / Superlattices and Microstructures 90 (2016) 8e19
Fig. 15. Variation of Transconductance Generation Factor(TGF) with gate to source voltage.
Fig. 16. Variation of Output Conductance with drain to source voltage.
Fig. 17. Variation of Subthreshold Slope with gate to source voltage.
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S. Rewari et al. / Superlattices and Microstructures 90 (2016) 8e19
TGF ¼
gm Ids
Fig. 15.Shows the variation of Transconductance Generation Factor(TGF) with gate to source voltage at Vds ¼ 1.0 V. Thus, JLDSG MOSFET has larger capability to convert larger dc power into ac gain in comparison to JLSG MOSFET. Fig. 16 shows the variation of the output conductance with the drain voltage for JLDSG MOSFET and JLSG MOSFET at various channel length. It can be clearly seen that JLDSG MOSFET has higher output conductance than JLSG MOSFET. The enhanced output conductance can be attributed to the higher drain current which is obtained in the double gate architecture. Fig. 17 shows the variation of Subthreshold Slope with the gate to source voltage for JLSG MOSFET and JLDSG MOSFET. Subthreshold Slope for a MOSFET in Subthreshold region can be defined as the slope of the drain current-gate voltage curve. Off to On switching capability of the device is determined by the Subthreshold Slope (SS). Ideally at room temperature its value is 60 mv/decade. SS for JLDSG MOSFET is less and closer to 60 mV/decade than the JLSG MOSFET. This improvement is due to improved Subthreshold characteristics owing to enhanced control over the channel. 6. Conclusion A Numerical model has been developed for JLDSG MOSFET for Potential, Subthreshold Current and Subthreshold Slope. Using the analytic model the Subthreshold performance has been verified for various channel length (L ¼ 30 nm, 40 nm, 50 nm), different silicon film thickness (tsi ¼ 8 nm, 9 nm, 10 nm) and different oxide thickness (tox ¼ 2 nm, 3 nm). The Numerical results so obtained are in good agreement with the simulated results. Also, JLDSG MOSFET has been found a potential device over JLSG MOSFET. Acknowledgment Authors are grateful to the Director, Maharaja Agrasen Institute of Technology, Delhi and All India Council for Technical Education, Government of India for financial assistance to carry out this research work. Appendix
Mn ¼
L2n L1n expðhn LÞ 2 sinhðhn LÞ
(A1)
Nn ¼
L1n expðhn LÞ L2n 2 sinhðhn LÞ
(A2)
2 L1n ¼
2
4 Vbi Vgseff t 2 J12 hn teff
8 193 0 J h t = 1 n eff §teff < teff tsi teff J1 hn teff @ J0 hn teff A 5 þ þ 2 t J2 hn teff teff ; hn hn teff 1 2 2 hn : eff (A3)
2
L2n ¼
2 4 Vbi þ Vds Vgseff t 2 J12 hn teff 193 = J0 hn teff A 5 ;
8 0 t J h t J h t < 1 1 n n eff eff eff §t t t eff eff @ þ si þ 2 t J2 hn teff teff hn hn teff 1 2 2 hn : eff (A4)
References [1] B. Yu, H. Lu, M. Liu, Y. Taur, Explicit Continuous Model for Double Gate and Surrounding Gate MOSFET, Electronic Device, IEEE Tran. on 54 (10) (Oct., 2007) 2715e2722. [2] P. Kumar, D. Joy, B.K. Jeblin, Nanoscale tri-gate MOSFET for Ultra low power applications using high-k dielectrics, Nanoelectronics, 2013, INEC 2013, 5th IEEE International Conference on 2e4 (Jan., 2013) 12e19. [3] D. Jimenez, J.J. Saenz, B. Iniguez, J. Sune, L.F. Marsal, J. Pallares, Modeling of Nanoscale Gate-All- Around MOSFETs, IEEE, Electron device Lett. 25 (5) (May., 2004) 314e316. [4] K.H. Yeo, S.D. Suk, M. Li, Y. Yeoh, K.H. Cho, K.-H. Hong, S. Yun, M.S. Lee, N. Cho, K. Lee, D. Hwang, B. Park, D.-W. Kim, D. Park, B.-I. Ryu, Gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 15 nm length gate and 4 nm radius nanowires, in: IEDM Technical Digest, 2006, pp. 1e4. [5] V.M. Srivastava, K.S. Yadav, G. Singh, Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch, Microelectron. Eng. 42 (2011) 1124e1135.
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[6] V.M. Srivastava, G. Singh, MOSFET Technologies for Double-pole Four-throw Radio-frequency Switch, Springer, Switzerland, 2014. [7] V.M. Srivastava, K.S. Yadav, G. Singh, Drain Current and Noise Model of Cylindrical Surrounding Double Gate MOSFET for RF Switch, in: International Conference on Modeling, Optimization and Computing (ICMOC 2012), Procedia Engineering, 2012, pp. 517e521. [8] Y. Chen, W. Kang, Experimental study and modeling of doublee surrounding-gate and cylindrical siliconeon-nothing MOSFETs, Microelectron. Eng. 97 (2012) 138e143. [9] J. Colinge, C. Lee, A. Afzalian, N. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A.M. Kelleher, B. McCarthy, R. Murphy, Nanowire transistor without junctions, Nat. Nanotechnol. 5 (3) (March 2010) 225e229. [10] D.-Y. Jeon, S.J. Park, M. Mouis, S. Barraud, G.-T. Kim, G. Ghibaudo, Low-temperature electrical characterization of junctionless transistors, Solid State Electron. 80 (Feb. 2013) 135e141. [11] ATLAS: 3D Device Simulator, SILVACO International, 2015. [12] Amir N. Hanna, Hossain M. Fahad & Muhammad M. Hussain “ InAs/Si Hetero-Junction Nanotube Tunnel Transistors” Nature Scientific Reports, 5:9843, DOI: 10.1038, srep09843, pp. 1e7. [13] Silicon Nanotube MOSFET, Daniel Tekleab, Wappingers Falls, Hung H. Tran, Hopewell Junction, NY (US), Jeffery W. Sleight, Ridgefield, CT (US), Dureseti Chidambarrao, Weston, CT (US), US 2014/0061583 A1. [14] Rajni Gautam, Manoj Saxena, R.S. Gupta, Mridula Gupta, Two Dimensional Analytic Subthreshold Model Of Nanoscale Cylindrical MOSFET including Impact Of Localized Charges, J. Of Comput. Theor. Nanosci. 9 (2012) 1e9. [15] Chunsheng Jiang, Renrong Liang, Jimg Wang, Jun Xu, A two dimensional Numerical Model for Short Channel Junctionless Double Gate MOSFET, AIP Adv. 5 (2015) 057122. [16] Cong Li, Yiqi Zhuang, Ru Han, Gang Jin, Subthreshold Behaviour Models for short-channel junctionless trimaterial cylindrical surrounding-gate MOSFET, Microelectron. Reliab. 54 (2014) 1274e1281. [17] Manoj Kumar, Subhasis Haldar, Mridula Gupta, R.S. Gupta, Impact of Gate Material Engineering(GME) on Analog/RF Performance of Nanowire Schottky-barrier Gate All Around (GAA) MOSFET for Low Power Wireless Applications: 3D T-cad Simulation, Volume 45, November 2014, pp. 1508e1514, 11. [18] Narain Arora “MOSFET Modelling for Device Simulation Theory and Practice” International series on Advances in solid state Electronics and Technology, Copyright @ 2007 World Scientific Publishing Co. Re. Ltd., ISBN-13 978-981-256-862-5, ISBN- 10 98 1 -256-862-X.
Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Numerical modeling of Subthreshold region of junctionless double surrounding gate MOSFET (JLDSG) Sonam Rewari a, Subhasis Haldar b, Vandana Nath c, S.S. Deswal d, R.S. Gupta a, * a
Department Of Electronics and Communication Engineering, Maharaja Agrasen Institute Of Technology, 110086, New Delhi, India Department Of Physics, Motilal Nehru College, University Of Delhi, 110021, New Delhi, India c University School Of Information and Communication Technology, Guru Gobind Singh Indraprastha University Sector - 16C, Dwarka 110078, New Delhi, India d Department Of Electrical and Electronics Engineering, Maharaja Agrasen Institute Of Technology, 110086, New Delhi, India b
a r t i c l e i n f o
a b s t r a c t
Article history: Received 18 September 2015 Received in revised form 20 November 2015 Accepted 22 November 2015 Available online 30 November 2015
In this paper, Numerical Model for Electric Potential, Subthreshold Current and Subthreshold Swing for Junctionless Double Surrounding Gate(JLDSG) MOSFEThas been developed using superposition method. The results have also been evaluated for different silicon film thickness, oxide film thickness and channel length. The numerical results so obtained are in good agreement with the simulated data. Also, the results of JLDSG MOSFET have been compared with the conventional Junctionless Surrounding Gate (JLSG) MOSFET and it is observed that JLDSG MOSFET has improved drain currents, transconductance, outputconductance, Transconductance Generation Factor (TGF) and Subthreshold Slope. © 2015 Elsevier Ltd. All rights reserved.
Keywords: Junctionless Modeling Double surrounding gate(DSG) MOSFET SCE’s Surrounding gate(SG)
1. Introduction MOSFET size is approaching nanoscale regime. The reduction in device size has led to several problems such as Short Channel Effects (SCE's) and Hot Carrier Effects (HCE's) [1e4]. Multigate transistor such as Double Gate (DG) MOSFET, Triple Gate (TG) MOSFET and cylindrical Surrounding Gate (SG) MOSFET [1e4] are feasible solutions to aforesaid problems. SG MOSFET is one of the best architectures to reduce SCE's as this gate completely surrounds the silicon pillar, thus enhancing gate controllability to a much larger extent. SCE's can further be mitigated by employing cylindrical Double Surrounding Gate (DSG) MOSFET. DSG MOSFET is a double gate architecture employed over a surrounding gate structure. It has two cylindrical gates, one above and one below the silicon film. The higher current drive and lower leakage is also obtained by employing DSG MOSFET apart from improved intrinsic characteristics [5e8]. The improved performance is attributed to the additional inner gate which provides an enhanced control over the channel. Another issue associated with SG MOSFET is the abrupt Source Drain junction formation [9]. This problem can be liquidated by using Junctionless (JLT) MOSFET. In JLT MOSFET source-channel-drain are heavily doped with same type of doping i.e. they are uniformly doped. For n type MOSFET doping is Nþ- Nþ- Nþ and for p type MOSFET it is Pþ- Pþ- Pþ. Thus, there is no abrupt source drain junction formation because of homogeneous doping in source-channel-drain. Also, the thermal budget for manufacturing is significantly reduced as JLT has
* Corresponding author. E-mail addresses: [email protected] (S. Haldar), [email protected] (V. Nath), [email protected] (S.S. Deswal), rsgupta1943@ gmail.com (R.S. Gupta). http://dx.doi.org/10.1016/j.spmi.2015.11.026 0749-6036/© 2015 Elsevier Ltd. All rights reserved.
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no doping concentration gradients [10]. Junctionless Surrounding Gate (JLSG) MOSFET has reduced short channel effects along with homogeneous doping in source-channel-drain [9].In this article, we propose a Numerical Model for Junctionless Double Surrounding Gate (JLDSG) MOSFET as it helps us to understand device physics. JLDSG MOSFET inculcates advantages of JLSG MOSFET and DSG MOSFET both. By employing JLDSG MOSFET we can reduce SCE's and also eliminate the issue of abrupt Source Drain junction formation. 2. Devicestructure and fabrication issues A 3-D structure of cylindrical JLDSG MOSFET is shown in Fig. 1 a and Fig. 1 b shows the Cutplane view of JDSG MOSFET with two gates, an inner gate GATE1 (below the silicon film) and an outer gate GATE2 (above the silicon film) having same metal gate workfunction using silicon dioxide as dielectric.Both the gates, GATE1 and GATE2 are made up of platinum having the same metal workfunction of 5.56 eV with uniformly doped silicon across source-channel-drain with ND ¼ 1019 cm3 for n type MOSFET, thickness of silicon film tsi ¼ 20 nm, oxide thickness tox ¼ 2 nm, oxide permittivity εox ¼ 3.9 (Fig. 2). ATLAS 3D device simulator has been used for simulations with Shockley-Read-Hall (SRH) recombination model with concentration dependent lifetimes is used to account for minority recombination. The Boltzmann transport model is used as a drift diffusion model. To incorporate the effect of high doping in the channel especially for junctionless transistor, the Band Gap Narrowing (BGN) model has been used in simulation. Concentration dependent mobility model (CONMOB) along with Lombardi CVT model is used because it considers large temperature range with parallel and perpendicular field dependent mobility. Fig. 3(a). shows JLDSG MOSFET with two gates, an inner gate(G1) and outer gate (G2) and Fig. 3(b) shows a single gateJLSG MOSFET on silicon film (tsi ¼ 20 nm). In JLDSG MOSFET the gate action is from two sides, one because of the inner gate (G1) and the other because of the outer gate (G2). Thus, the control of gate over the silicon film is increased in JLDSG MOSFET and the effective gate voltage increases. Fabrication feasibility of CSDG MOSFET has been recently addressed by Hanna et al. [12] and Tekleab et al. [13]. They have successfully fabricated a cylindrical surrounding gate with an inner charge control gate. Their design process flow starts from the oxide mandrel patterning followed by sacrificial and structural spacer formation and then etching and cleaning process are performed. To pattern a shell body a sacrificial pillar structure is patterned followed by dielectric/gate deposition with other processing steps. 3. Numerical model 2-D Poisson's equation in cylindrical coordinates is solved under the appropriate boundary conditions using the superposition method [14] to obtain expressions for Electric potential and Subthreshold Current. 2-D Poisson's equation in cylindrical coordinates is expressed as:
1 v v2 v2 qN ðфðr; zÞÞ þ 2 фðr; zÞ þ 2 фðr; zÞ ¼ D r vr 3 si vr vz
(1)
where ND is the uniform doping concentration, ф(r,z) is the potential distribution in the silicon film. In superposition technique the resultant solution of potential can be decomposed into one dimensional long channel solution (V(r)) which satisfies one dimensional Poisson's equation and two dimensional short channel solution (U(r,z)) which satisfies two dimensional Laplace's equation i.e.
фðr; zÞ ¼ VðrÞ þ Uðr; zÞ
Fig. 1. a. 3-D View of cylindrical JLDSG MOSFET. b. Cut plane View of cylindrical JLDSG MOSFET.
(2)
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Fig. 2. Cross-sectional View of cylindrical JLDSG MOSFET.
Then the Eq. (1) becomes
1 v v2 q ND ðVðrÞÞ þ 2 VðrÞ ¼ r vr 3 si vr
(3)
and
1 v v2 v2 ðUðr; zÞÞ þ 2 Uðr; zÞ þ 2 Uðr; zÞ ¼ 0 r vr vr vz
(4)
The boundary conditions employed for the solution of 2D potential ф(r,z) are:
ðiÞ ф teff ; z ¼ фos ðzÞ
(5)
ðiiÞ ф teff tsi ; z ¼ фis ðzÞ
(6)
vфðr; zÞ ðiiiÞ vr
r¼teff
¼ J Vgs фos ðzÞ
(7)
vфðr; zÞ ðivÞ ¼ J Vgs фis ðzÞ vr r¼teff tsi
(8)
ðvÞ фðr; 0Þ ¼ Vbi
(9)
ðviÞ фðr; LÞ ¼ Vbi þ Vds
(10)
teff¼tm þ tox þ tsi,J ¼ Cεoxsi , Vbi ¼ 0 for JLDSG MOSFET,Cox is obtained by series combination of outer oxide capacitance Coxo and the inner oxide capacitance Coxi. Coxo is represented
Coxo ¼
εox
ðtm þ tox þ tsi Þðtm þ tox þ tsi Þln 1 þ ðtm þttoxox þtsi Þ
(11)
asCoxi is represented as:
Coxi ¼
εox ðtm þ tox Þln 1 þ ttoxm
(11a)
εox is the dielectric permittivity of oxide,фos(z) is the constant potential present at the outer surface, фis(z) is the constant potential present at the inner surface.
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Fig. 3. Effect of gates on silicon film for JLDSG MOSFET and JLSG MOSFET.
The resultant solution of Eq. (3) can be considered as parabolic approximation:
VðrÞ ¼ P0 þ P1 r þ P2 r2
(12)
where qNd tsi d P0 ¼ Vgseff P1 t þ J1 P2 t 2 þ 2t ¼ d t ,P 1 eff J 2 ,P2 ¼ 2, d ¼ εsi ,Vgseff ¼ Vgs Vfb, Vfb is the flat band voltage. The solution of Eq. (4) can be obtained as
Uðr; zÞ ¼
∞ X
J0 ðhn rÞðMn expðhn zÞ þ Nn expðhn zÞÞ
(13)
n¼1
where J0 and J1 are the bessel functions of order 0 and 1 respectively, Mn and Nn are the constants evaluated using boundary conditions (9) and (10) and are given in Appendix, an are the Eigen values of
J1
teff teff Cox ¼ J0 an an εsi an
(14)
The resultant solution can be expressed as:
фðr; zÞ ¼ VðrÞ þ
∞ X
J0 ðhn rÞðMn expðhn zÞ þ Nn expðhn zÞÞ
(15)
n¼1
Where hn ¼ a1n . The Subthreshold current, Isub [14] is given as:-
Isub ¼ 2:R:p:m:k:T:hi :Z 0
1e L
0 B @
q:Vds k:T
1 Z
teff
e 0
фðr;zÞ k:T
(16) 1 dz
C dr A
wherek ¼ 1.38 1023 J/K is the Boltzmann's constant, T ¼ 300 K, hi¼1.45 1010 cm3 is the intrinsic carrier density, m¼1300 cm2/Vs is the electron mobility. The Subthreshold Slope, SS is written as:-
SS ¼
1 d dVgs
logðIsub Þ
(17)
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4. Results and discussion Fig. 4 shows the potential distribution at the center of JLDSG MOSFET for different channel length. It can be clearly observed that as the channel length decreases, minimum central potential rises upwards becauseof the reduction in the charge control linear region which causes the potential to shift towards the source region and so this source potential affects the minimum potential at the center of the channel [15]. The Numerical results so obtained are in good agreement with the simulated results. Fig. 5 shows thepotential distribution at the center of JLDSG MOSFET for different silicon film thickness. It can be clearly observed that as the silicon film thickness increases, minimum surface potential decreases. This is because as silicon film thickness increases, the gate control over the channel gets weakened [16], leading to lowering of surface potential and thus, minimum surface potential. The Numerical results obtained are in good agreement with the simulated results. Fig. 6 shows thepotential distribution at the center of JLDSG MOSFET for various oxide thicknesses. The Numerical results so obtained are in good agreement with the simulated results. Vertical electric field is created due to the presence of oxide layer between the metal and the semiconductor. As oxide thickness increases this vertical electric field is reduced because the gate control over the channel weakens. So, as the oxide thickness increases, minimum surface potential is pulled upwards [16]. Fig. 7.Shows the variation of Subthreshold current with the gate to source voltage for different channel length. It can be noted that as the channel length reduces Ioff current increases. this increase in Ioff current is due to short channel effects (SCE's) which creep in when channel length reduces [15]. The Numerical results so obtained are in good agreement with the simulated results. Fig. 8.Shows the variation of Subthreshold current with the gate to source voltage for different silicon film thickness. It can be noted that as the film thickness increases off current decreases because the gate controllability over the channel decreases [16]. The Numerical results so obtained are in good agreement with the simulated results. Fig. 9. Shows the variation of Subthreshold current with the gate to source voltage for different oxide thickness. It can be noted that as the oxide thickness increases, Subthreshold drain current increases. This is so because in JLSG MOSFET, when thickness of oxide layer increases depletion of electrons becomes difficult because of reduced vertical electric field [16]. The Numerical results so obtained are in good agreement with the simulated results. Fig. 10. Shows the variation of Subthreshold slope with channel length for different silicon film thickness. As the silicon film thickness increases the Subthreshold slope of JLDSG MOSFET degrade and drifts away from the ideal value because the silicon area has increased for larger silicon film thickness and so the gate control over the channel has decreased [15]. The Numerical results so obtained are in good agreement with the simulated results. Fig. 11 shows the variation of Subthreshold slope with channel length for different oxide thickness. It can be noted that as the oxide thickness increases, Subthreshold slope (SS) degrades, this is because of limited impact of gate due to increased oxide thickness [16]. The Numerical results so obtained are in good agreement with the simulated results. 5. JLDSGMOSFET a potential device The simulation of the device has been carried out using the ATLAS 3-D device simulator [11].For a fair comparison between JLSG MOSFET and JLDSG MOSFET the threshold voltage is kept same as 0.25 V by changing the workfunction at L ¼ 18 nm.The
Fig. 4. Potential Distribution along the channel at the center for different Channel Length.
S. Rewari et al. / Superlattices and Microstructures 90 (2016) 8e19
Fig. 5. Potential Distribution along the channel at the center for different silicon film thickness.
Fig. 6. Potential Distribution along the channel at the center for different oxide thickness.
Fig. 7. Subthreshold Current as a function of Gate to Source Voltage in JLDSGMOSFET for different Channel Length.
13
Fig. 8. Subthreshold Current as a function of Gate to Source Voltage in JLDSG MOSFET for different silicon film thickness.
Fig. 9. Subthreshold Current as a function of Gate to Source Voltage in JLDSG MOSFET for different oxide thickness.
Fig. 10. Subthreshold Slope as a function of Channel Length in JLDSG MOSFET for different silicon film thickness.
S. Rewari et al. / Superlattices and Microstructures 90 (2016) 8e19
15
Fig. 11. Subthreshold Slope as a function of Channel Length in JLDSG MOSFET for different oxide thickness.
Table 1 Summarizes the various device structure parameters for JLDSG MOSFET. Parameters
JLDSG MOSFET
JLSG MOSFET
Channel length (nm) Channel doping (/cm3) Silicon oxide thickness (nm) Silicon thickness (nm) Gate work function (eV) Length of S/D (nm)
30,40,50 1 1019 2 10 5.56 15
30,40,50 1 1019 2 10 5.7 15
threshold voltage has been calculated using the linear extrapolation method [18]. In this method, threshold voltage is defined as that gate voltage which is obtained by extrapolating the linear portion of the Ids, versus Vgs, characteristics, from the point of maximum slope, to zero drain current Ids. Note that the point of maximum slope is that point where the transconductance gm ¼ vIds/vVgs is maximum. This threshold voltage is often called the extrapolated Vth. This is the most common method of determining Vth and is the defacto industry standard. The various device parameters have been tabulated in Table 1 for both the devices. Fig. 12. Shows the variation of drain current, Ids with the gate voltage, Vgs Improved drain current has been observed in JLDSG MOSFET over JLSG MOSFET.An improvement of 41.98 times in Ion/Ioff ratio of JLDSG MOSFET has been
Fig. 12. Variation of Drain current with Gate to Source Voltage.
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S. Rewari et al. / Superlattices and Microstructures 90 (2016) 8e19
Fig. 13. Variation of Drain current with Drain to Source Voltage.
observed over JLSG MOSFET.In JLSGMOSFET depletion layer is formed in the channel region because of the vertical electric field created due to the applied gate voltage.Lateral conduction begins through the center of the silicon film as the gate voltage is further increased beyond the flat band voltage (VFB). In JLDSG MOSFET there are two gates, consequently there is an enhanced gate control over the channel leading to larger effective gate voltage.So, two inversion layers are formed in the channel region of JLDSG MOSFET leading to improved drain current, transconductance, output conductance and Subthreshold slope. Thus, higher Ion and lower Ioff have been noted in JLDSG MOSFET over JLSG MOSFET. Fig. 13 shows the variation of drain current with drain to source voltage for different channel lengths (L ¼ 18 nm, 24 nm, 30 nm) for JLSG MOSFET and JLDSG MOSFET. It is seen that as the channel length decreases drain current increases. Due to larger gate control over the channel higher drain currents have been observed in JLDSG MOSFET for all the channel lengths. Fig. 14 illustrates the variation of transconductance, gm with the gate voltage. Transconductance (gm) governs the gain of a device and peak value directs higher cut off frequency [17]. So, a higher value of transconductance is always desirable. As the drain current is improving for different gate voltages in JLDSG MOSFET over JLSG MOSFET, gm is also improving. An improvement in gm of JLDSG MOSFET by 1.82 times for channel length L ¼ 18 nm, 2.098 times for L ¼ 24 nm and 2.23 times for L ¼ 30 nm over gm of JLSG MOSFET has been observed. Transconductance Generation Factor(TGF) of any device at a fixed drain voltage depicts the ability to convert the dc power into ac gain and is defined as TGF can be defined as:
Fig. 14. Variation of Transconductance with gate to source voltage.
S. Rewari et al. / Superlattices and Microstructures 90 (2016) 8e19
Fig. 15. Variation of Transconductance Generation Factor(TGF) with gate to source voltage.
Fig. 16. Variation of Output Conductance with drain to source voltage.
Fig. 17. Variation of Subthreshold Slope with gate to source voltage.
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TGF ¼
gm Ids
Fig. 15.Shows the variation of Transconductance Generation Factor(TGF) with gate to source voltage at Vds ¼ 1.0 V. Thus, JLDSG MOSFET has larger capability to convert larger dc power into ac gain in comparison to JLSG MOSFET. Fig. 16 shows the variation of the output conductance with the drain voltage for JLDSG MOSFET and JLSG MOSFET at various channel length. It can be clearly seen that JLDSG MOSFET has higher output conductance than JLSG MOSFET. The enhanced output conductance can be attributed to the higher drain current which is obtained in the double gate architecture. Fig. 17 shows the variation of Subthreshold Slope with the gate to source voltage for JLSG MOSFET and JLDSG MOSFET. Subthreshold Slope for a MOSFET in Subthreshold region can be defined as the slope of the drain current-gate voltage curve. Off to On switching capability of the device is determined by the Subthreshold Slope (SS). Ideally at room temperature its value is 60 mv/decade. SS for JLDSG MOSFET is less and closer to 60 mV/decade than the JLSG MOSFET. This improvement is due to improved Subthreshold characteristics owing to enhanced control over the channel. 6. Conclusion A Numerical model has been developed for JLDSG MOSFET for Potential, Subthreshold Current and Subthreshold Slope. Using the analytic model the Subthreshold performance has been verified for various channel length (L ¼ 30 nm, 40 nm, 50 nm), different silicon film thickness (tsi ¼ 8 nm, 9 nm, 10 nm) and different oxide thickness (tox ¼ 2 nm, 3 nm). The Numerical results so obtained are in good agreement with the simulated results. Also, JLDSG MOSFET has been found a potential device over JLSG MOSFET. Acknowledgment Authors are grateful to the Director, Maharaja Agrasen Institute of Technology, Delhi and All India Council for Technical Education, Government of India for financial assistance to carry out this research work. Appendix
Mn ¼
L2n L1n expðhn LÞ 2 sinhðhn LÞ
(A1)
Nn ¼
L1n expðhn LÞ L2n 2 sinhðhn LÞ
(A2)
2 L1n ¼
2
4 Vbi Vgseff t 2 J12 hn teff
8 193 0 J h t = 1 n eff §teff < teff tsi teff J1 hn teff @ J0 hn teff A 5 þ þ 2 t J2 hn teff teff ; hn hn teff 1 2 2 hn : eff (A3)
2
L2n ¼
2 4 Vbi þ Vds Vgseff t 2 J12 hn teff 193 = J0 hn teff A 5 ;
8 0 t J h t J h t < 1 1 n n eff eff eff §t t t eff eff @ þ si þ 2 t J2 hn teff teff hn hn teff 1 2 2 hn : eff (A4)
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