- Email: [email protected]
Off-state avalanche-breakdown-induced on-resistance degradation in SGO–NLDMOS
Solid-State Electronics 81 (2013) 27–31
Contents lists available at SciVerse ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Off-state avalanche-breakdown-induced on-resistance degradation in SGO–NLDMOS Shifeng Zhang, Yan Han ⇑, Koubao Ding, Jiaxian Hu, Bin Zhang, Wei Zhang, Huanting Wu Institute of Microelectronics & Photoelectronics, Zhejiang University, Hangzhou, Zhejiang 310027, PR China
a r t i c l e
i n f o
Article history: Received 6 November 2012 Received in revised form 25 December 2012 Accepted 28 December 2012 Available online 28 February 2013 The review of this paper was arranged by Prof. S. Cristoloveanu
a b s t r a c t In this paper, on-resistance (Ron) degradation induced by off-state avalanche breakdown in a 40 V LDMOS with step-shaped gate oxide (SGO–LDMOS) is investigated. Ron unexpectedly decreases at the beginning of stress, which is different from the phenomenon described in works on LDMOS with uniform gate oxide (UGO–LDMOS). Based on the experiment data and TCAD simulation results, two degradation mechanisms are proposed. That is the generation of positive oxide-trapped charges at the bird’s beak region near source and formation of interface state at the bird’s beak region near source and drain respectively. Crown Copyright Ó 2013 Published by Elsevier Ltd. All rights reserved.
Keywords: Step-shaped gate oxide LDMOS Avalanche breakdown On-resistance degradation
1. Introduction Lateral double-diffused MOS device (LDMOS) is widely used in power intergraded technologies owing to its compatibility with the standard CMOS devices and its power-handling capabilities. When it is used in unclamped inductive switching (UIS) applications, the LDMOS device may be subjected to avalanche breakdown during the on-to-off-state transient [1–3]. Repeatedly operating under avalanche breakdown could result in device degradation, and even device failure. However, the hot-carrier reliability of device under off-state avalanche breakdown condition has not attracted as much attention as the hot-carrier reliability under saturation condition [3–10], and only few papers have focus on this issue [1–12]. The avalanche-breakdown-induced on-resistance Ron degradation of LDMOS transistors with uniform gate oxide (UGO–LDMOS) has been presented in paper [1]. Its off-state breakdown voltage is 20 V. However, for the higher supply voltage applications (40 V or higher for example), field oxide is usually employed and used to form a step for the poly field plate. The field oxide under the poly-gate is regarded as thick gate oxide. In this paper, the on-resistance degradation induced by off-state avalanche breakdown in a 40 V n-type LDMOS transistor with stepshaped gate oxide (SGO–LDMOS) is investigated. The anomalous phenomenon of on-resistance degradation is disclosed. The Ron ⇑ Corresponding author. Tel./fax: +86 0571 87953116. E-mail address: [email protected] (Y. Han).
shows a significant reduction before it increases to be larger than its fresh value, which is different from that of LDMOS with uniform gate oxide as shown in paper [1]. Based on the experiment results and TCAD simulations, the avalanche-breakdown-induced onresistance Ron degradation mechanisms are proposed. 2. Device structure The devices studied in this paper are processed in 0.35 lm Bipolar-CMOS–DMOS (BCD) smart-power technology. Fig. 1a and b shows the cross section of the UGO–LDMOS and the SGO–LDMOS. The SGO–LDMOS structure is identical with the UGO–LDMOS except a step-shaped gate oxide under the polysilicon. Some important parameters for the two devices are the same, given as follows: the thickness of the thin gate oxide is 7 nm, the channel length is 0.5 lm, the gate width is 20 lm. And the UGO–LDMOS and SGO–LDMOS have the following characteristics: the drift region lengths are 1.5 lm and 2.5 lm, the off-state breakdown voltages are around 12.5 V and 40 V, the threshold voltages are all 0.7 V, the on-state resistances are 100 X and 230 X. The representative operating voltages of SGO– LDMOS are Vgs = 3.3 V and Vds = 25 V. 3. Experiment Constant-current pulse stressing is adopted to simulate the damage generated by avalanche breakdown during the fast onto-off-state transient. The pulse stressing is applied to the drain,
0038-1101/$ - see front matter Crown Copyright Ó 2013 Published by Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.sse.2012.12.012
28
S. Zhang et al. / Solid-State Electronics 81 (2013) 27–31
Body Source
Gnd Oxide
P+
Gate
N+
P+
Drain
N+
Gnd Oxide
P+
P- Body N- Well
Lch
Ldrift
0.5um
1.5um
P- sub
(a) UGO-LDMOS Gnd
P+
Body Source Oxide
P+
Drain
Gate Oxide
N+
N+
Gnd Oxide
P+
P- Body N- Well
Lch
Fig. 2. Relationship between Ron degradation and the number of pulse under different current level.
Ldrift
0.5um
2.5um
P- sub
(b) SGO-LDMOS Fig. 1. Schematic cross section of the devices studied in this paper.
with gate, source and body ground. Varieties of current levels ranging from 1 lA to 1 mA are performed, and the pulse width is 0.1 s. The on- resistance Ron is measured at Vgs = 3.3 V and Vds = 0.1 V after stressing. Fig. 2 illustrates the variation of on-resistance (DRon) with respect to the number of pulse under different current levels in UGO–LDMOS and SGO–LDMOS. The minus represents a reduction. For the SGO–LDMOS, it is quite obvious that Ron exhibits a significant decrease at the first hundreds of pulses, and higher current level brings about greater Ron reduction. With the number of pulse further increases, Ron will rise quickly and ultimately degrade to be larger than its fresh value. By comparison, the variation of UGO–LDMOS’s Ron is measured. It is always increasing all through the experiment, just as reported in [1]. Fig. 3 shows the Id variation of SGO–LDMOS at different Vds with respect to the number of pulse. It is obvious that the Id shift at Vds = 25 V (saturation condition) is far less than that at Vds = 0.1 V (linear condition). For Vds = 25 V, the Id shift is only less than 1% at the first hundreds of pulse. But for Vds = 0.1 V, the Id shift is about 5% and the degradation comes to saturation later. 4. TCAD simulations In order to discuss the physical mechanism responsible for the Ron degradation, TCAD simulations are performed. In this paper, Tsuprem4 is used for the process simulation. And MEDICI is used for electrical analysis for the device structure obtained from Tsuprem4. Fig. 4 shows the simulated contour of current flow for the device biased at Vgs = 3.3 V with Vds = 0.1 V and Vds = 25 V, respectively. When Vds is biased at 0.1 V, the current flows are close to the Si/SiO2 interface on the drift region. While Vds = 25 V, the current flows are pushed away from the top surface of drift region. Hence, the Id for Vds = 0.1 V is more sensitive to positive oxidetrapped charges and interface states than the Id for Vds = 25 V. It provides the verification for the foregoing statement in Fig. 3. Fig. 5 shows the vertical electric field (Ey) along the Si/SiO2 interface under avalanche breakdown. It can be seen that there
Fig. 3. The Id variation of SGO–LDMOS at different Vds with respect to the number of pulse.
are two highest electric field peak values. The first highest peak value exists at the boundary between the gate oxide and the field oxide, especially at the bird’s beak region. It is caused by the bird’s beak effect. And its direction is negative, which is favorable for hot holes injection. The second highest peak value exists at another bird’s beak region near drain, but it is favorable for hot electrons injection. Other two smaller electric field peak value exist at the channel region and poly field plate edge, respectively. Fig. 6 shows the simulated 2-D impact ionization (ii) rate distribution in the device under avalanche breakdown. It can be observed that there are two obvious ii rate peaks existing in drift region along the Si/SiO2 interface. The first one exists at the boundary between the gate oxide and the field oxide (point A). The second ii rate peak exists at another bird’s beak region (point B). With the pulse current level increasing (from 1 lA to 1 mA), the two ii rate peak values increase, and the ii rate generating range also becomes larger. That is to say, the interface states or positive oxidetrapped charges will appear in a wider area. Fig. 7 shows the simulated impact ionization rate along the Si/SiO2 interface under avalanche breakdown. It is obvious that the ii rate peak value at the point B is nearly three times larger than the one at point A. This is because that the avalanche breakdown occurs at the vertical p–n junction first. Thus, a great amount of current flows to the substrate through point B. But a small amount of current flows to the source. High current density with high electric field induces high ii rate. With the pulse current level increasing (from 1 lA to 1 mA),
S. Zhang et al. / Solid-State Electronics 81 (2013) 27–31
29
Fig. 4. Simulated contour of current flow for the device biased at Vgs = 3.3 V with Vds = 0.1 V and Vds = 25 V, respectively.
Fig. 5. Simulated vertical electric field (Ey) along the Si/SiO2 interface under avalanche breakdown.
the current flowing to the source also increase. So the ii rate at point A becomes lager. According to the simulated vertical electric field in Fig. 5 and the simulated impact ionization rate in Fig. 7, it can be concluded that positive oxide-trapped charges may generate at the bird’s beak region near source. And interface states will generate at the bird’s beak region near source and drain respectively. 5. Discussion Based on the experiment data and TCAD simulation results, two degradation mechanisms are proposed as follows: Mechanism 1: Generation of positive oxide-trapped charges at bird’s beak region near source. This mechanism plays the leading role at the beginning of the stressing, and comes to saturation later. The mechanism is confirmed by the simulated vertical electric field and impact ionization rate along the Si/SiO2 interface. Because trapping of holes in the oxide induces negative mirror charges at the bird’s
beak region near source, resulting in an effective increase in drift region concentration [13]. As a result, Ron decreases. The mechanism increases when the avalanche breakdown current increases. As the current increases, the impact ionization becomes more serious, and more hot holes can be injected into the oxide. Mechanism 2: Formation of interface state at the bird’s beak region near source and drain respectively. The second mechanism becomes obvious with the number of pulses increasing. Due to the increased scattering of the carriers at the interface states, the mobility of carriers is reduced, hence Ron will increase. This mechanism also increases with stressing current increasing. 6. Conclusion The off-state avalanche-breakdown-induced on-resistance Ron degradation in a 40 V n-type LDMOS with step-shaped gate oxide is investigated in this paper. Ron unexpectedly decreases at the beginning of stress, which is different from the phenomenon in
S. Zhang et al. / Solid-State Electronics 81 (2013) 27–31
(
(
(
(
(
(
(
(
30
Fig. 6. Simulated 2-D impact ionization rate distribution in the device under avalanche breakdown.
Fig. 7. Simulated impact ionization rate along the Si/SiO2 interface under avalanche breakdown.
LDMOS with uniform gate oxide. Then the vertical electric field and impact ionization rate along the Si/SiO2 interface are simulated to assist in providing better physical insights. Based on the experiment data and TCAD simulation results, two degradation mecha-
nisms are proposed. That is the generation of positive oxidetrapped charges at the bird’s beak region near source and formation of interface state at the bird’s beak region near source and drain respectively.
S. Zhang et al. / Solid-State Electronics 81 (2013) 27–31
References [1] Chen JF, Lee JR, Wu K-M, Huang T-Y, Liu CM, Hsu SL. Off-state avalanchebreakdown-induced on-resistance degradation in lateral DMOS transistors. IEEE Electr Dev Lett 2007;28(11):1033–5. [2] Pendharkar S, Efland T, Tsai C.-Y. Analysis of high current breakdown and UIS behavior of Resurf LDMOS (RLDMOS) devices. In: Proc symp power semicond devices ICs; 1998. p. 419–22. [3] Shekar MS, Williams RK, Cornell M, Luo M.-Y, Darwish M. Hot electron degradation and unclamped inductive switching in submicron 60-V lateral DMOS. In: Proc int rel phys symp; 1998. p. 383–90. [4] Moens P, den bosch GV, De Keukeleire C, Degraeve R, Tack M, Groeseneken G. Hot hole degradation effects in lateral nDMOS transistors. IEEE Trans Elec Dev 2004;51(10):1704–10. [5] Chen JF, Tian K-S, Chen S-Y, Wu K-M, Shih JR, Wu K. An investigation on anomalous hot-carrier-induced on-resistance reduction in n-type LDMOS transistors. IEEE Trans Dev Mater Rel 2009;9(3):459–64. [6] Brisbin D. Strachan A, Chaparala P. Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications. In: Proc int rel phys symp; 2002. p. 105–10.
31
[7] Chen JF, Tian K-S, Chen S-Y, Wu K-M, Liu CM. On-resistance degradation induced by hot-carrier injection in LDMOS transistors with STI in the drift region. IEEE Elec Dev Lett 2008;29(9):1071–3. [8] O’Donovan V, Whiston S, Deignan A, Chleirigh CN. Hot carrier reliability of lateral DMOS transistors. In: Proc IEEE int rel phys symp; 2000. p. 174–9. [9] Manzini S, Contiero C. Hot-electron-induced degradation in high-voltage submicron DMOS transistors. In: Proc int rel phys symp; 1996. p. 65–9. [10] Versari R, Pieracci A, Manzini S, Contiero C, Ricco B. Hot-carrier reliability in submicrometer LDMOS transistors. In: IEDM tech dig; 1997. p. 371–4. [11] Chen JF, Lee JR, Wu K-M, Huang T-Y, Liu CM. Mechanism and improvement of on-resistance degradation induced by avalanche breakdown in lateral DMOS transistors. IEEE Trans Elec Dev 2008;55(8):2259–62. [12] Liu Siyang, Sun Weifeng, Qian Qinsong, Zhu Jing. Comparisons of hot-carrier degradation behavior in SOI–LIGBT and SOI–LDMOS with different stress conditions. Solid-State Electron 2010;54(12):1598–601. [13] Zhang Shifeng, Han Yan, Ding Koubao, Zhang Bin, Hu Jiaxian. Investigation on hot-carrier-induced degradation of SOI NLIGBT. Microelectron Reliab 2011;51(6):1097–104.
Contents lists available at SciVerse ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Off-state avalanche-breakdown-induced on-resistance degradation in SGO–NLDMOS Shifeng Zhang, Yan Han ⇑, Koubao Ding, Jiaxian Hu, Bin Zhang, Wei Zhang, Huanting Wu Institute of Microelectronics & Photoelectronics, Zhejiang University, Hangzhou, Zhejiang 310027, PR China
a r t i c l e
i n f o
Article history: Received 6 November 2012 Received in revised form 25 December 2012 Accepted 28 December 2012 Available online 28 February 2013 The review of this paper was arranged by Prof. S. Cristoloveanu
a b s t r a c t In this paper, on-resistance (Ron) degradation induced by off-state avalanche breakdown in a 40 V LDMOS with step-shaped gate oxide (SGO–LDMOS) is investigated. Ron unexpectedly decreases at the beginning of stress, which is different from the phenomenon described in works on LDMOS with uniform gate oxide (UGO–LDMOS). Based on the experiment data and TCAD simulation results, two degradation mechanisms are proposed. That is the generation of positive oxide-trapped charges at the bird’s beak region near source and formation of interface state at the bird’s beak region near source and drain respectively. Crown Copyright Ó 2013 Published by Elsevier Ltd. All rights reserved.
Keywords: Step-shaped gate oxide LDMOS Avalanche breakdown On-resistance degradation
1. Introduction Lateral double-diffused MOS device (LDMOS) is widely used in power intergraded technologies owing to its compatibility with the standard CMOS devices and its power-handling capabilities. When it is used in unclamped inductive switching (UIS) applications, the LDMOS device may be subjected to avalanche breakdown during the on-to-off-state transient [1–3]. Repeatedly operating under avalanche breakdown could result in device degradation, and even device failure. However, the hot-carrier reliability of device under off-state avalanche breakdown condition has not attracted as much attention as the hot-carrier reliability under saturation condition [3–10], and only few papers have focus on this issue [1–12]. The avalanche-breakdown-induced on-resistance Ron degradation of LDMOS transistors with uniform gate oxide (UGO–LDMOS) has been presented in paper [1]. Its off-state breakdown voltage is 20 V. However, for the higher supply voltage applications (40 V or higher for example), field oxide is usually employed and used to form a step for the poly field plate. The field oxide under the poly-gate is regarded as thick gate oxide. In this paper, the on-resistance degradation induced by off-state avalanche breakdown in a 40 V n-type LDMOS transistor with stepshaped gate oxide (SGO–LDMOS) is investigated. The anomalous phenomenon of on-resistance degradation is disclosed. The Ron ⇑ Corresponding author. Tel./fax: +86 0571 87953116. E-mail address: [email protected] (Y. Han).
shows a significant reduction before it increases to be larger than its fresh value, which is different from that of LDMOS with uniform gate oxide as shown in paper [1]. Based on the experiment results and TCAD simulations, the avalanche-breakdown-induced onresistance Ron degradation mechanisms are proposed. 2. Device structure The devices studied in this paper are processed in 0.35 lm Bipolar-CMOS–DMOS (BCD) smart-power technology. Fig. 1a and b shows the cross section of the UGO–LDMOS and the SGO–LDMOS. The SGO–LDMOS structure is identical with the UGO–LDMOS except a step-shaped gate oxide under the polysilicon. Some important parameters for the two devices are the same, given as follows: the thickness of the thin gate oxide is 7 nm, the channel length is 0.5 lm, the gate width is 20 lm. And the UGO–LDMOS and SGO–LDMOS have the following characteristics: the drift region lengths are 1.5 lm and 2.5 lm, the off-state breakdown voltages are around 12.5 V and 40 V, the threshold voltages are all 0.7 V, the on-state resistances are 100 X and 230 X. The representative operating voltages of SGO– LDMOS are Vgs = 3.3 V and Vds = 25 V. 3. Experiment Constant-current pulse stressing is adopted to simulate the damage generated by avalanche breakdown during the fast onto-off-state transient. The pulse stressing is applied to the drain,
0038-1101/$ - see front matter Crown Copyright Ó 2013 Published by Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.sse.2012.12.012
28
S. Zhang et al. / Solid-State Electronics 81 (2013) 27–31
Body Source
Gnd Oxide
P+
Gate
N+
P+
Drain
N+
Gnd Oxide
P+
P- Body N- Well
Lch
Ldrift
0.5um
1.5um
P- sub
(a) UGO-LDMOS Gnd
P+
Body Source Oxide
P+
Drain
Gate Oxide
N+
N+
Gnd Oxide
P+
P- Body N- Well
Lch
Fig. 2. Relationship between Ron degradation and the number of pulse under different current level.
Ldrift
0.5um
2.5um
P- sub
(b) SGO-LDMOS Fig. 1. Schematic cross section of the devices studied in this paper.
with gate, source and body ground. Varieties of current levels ranging from 1 lA to 1 mA are performed, and the pulse width is 0.1 s. The on- resistance Ron is measured at Vgs = 3.3 V and Vds = 0.1 V after stressing. Fig. 2 illustrates the variation of on-resistance (DRon) with respect to the number of pulse under different current levels in UGO–LDMOS and SGO–LDMOS. The minus represents a reduction. For the SGO–LDMOS, it is quite obvious that Ron exhibits a significant decrease at the first hundreds of pulses, and higher current level brings about greater Ron reduction. With the number of pulse further increases, Ron will rise quickly and ultimately degrade to be larger than its fresh value. By comparison, the variation of UGO–LDMOS’s Ron is measured. It is always increasing all through the experiment, just as reported in [1]. Fig. 3 shows the Id variation of SGO–LDMOS at different Vds with respect to the number of pulse. It is obvious that the Id shift at Vds = 25 V (saturation condition) is far less than that at Vds = 0.1 V (linear condition). For Vds = 25 V, the Id shift is only less than 1% at the first hundreds of pulse. But for Vds = 0.1 V, the Id shift is about 5% and the degradation comes to saturation later. 4. TCAD simulations In order to discuss the physical mechanism responsible for the Ron degradation, TCAD simulations are performed. In this paper, Tsuprem4 is used for the process simulation. And MEDICI is used for electrical analysis for the device structure obtained from Tsuprem4. Fig. 4 shows the simulated contour of current flow for the device biased at Vgs = 3.3 V with Vds = 0.1 V and Vds = 25 V, respectively. When Vds is biased at 0.1 V, the current flows are close to the Si/SiO2 interface on the drift region. While Vds = 25 V, the current flows are pushed away from the top surface of drift region. Hence, the Id for Vds = 0.1 V is more sensitive to positive oxidetrapped charges and interface states than the Id for Vds = 25 V. It provides the verification for the foregoing statement in Fig. 3. Fig. 5 shows the vertical electric field (Ey) along the Si/SiO2 interface under avalanche breakdown. It can be seen that there
Fig. 3. The Id variation of SGO–LDMOS at different Vds with respect to the number of pulse.
are two highest electric field peak values. The first highest peak value exists at the boundary between the gate oxide and the field oxide, especially at the bird’s beak region. It is caused by the bird’s beak effect. And its direction is negative, which is favorable for hot holes injection. The second highest peak value exists at another bird’s beak region near drain, but it is favorable for hot electrons injection. Other two smaller electric field peak value exist at the channel region and poly field plate edge, respectively. Fig. 6 shows the simulated 2-D impact ionization (ii) rate distribution in the device under avalanche breakdown. It can be observed that there are two obvious ii rate peaks existing in drift region along the Si/SiO2 interface. The first one exists at the boundary between the gate oxide and the field oxide (point A). The second ii rate peak exists at another bird’s beak region (point B). With the pulse current level increasing (from 1 lA to 1 mA), the two ii rate peak values increase, and the ii rate generating range also becomes larger. That is to say, the interface states or positive oxidetrapped charges will appear in a wider area. Fig. 7 shows the simulated impact ionization rate along the Si/SiO2 interface under avalanche breakdown. It is obvious that the ii rate peak value at the point B is nearly three times larger than the one at point A. This is because that the avalanche breakdown occurs at the vertical p–n junction first. Thus, a great amount of current flows to the substrate through point B. But a small amount of current flows to the source. High current density with high electric field induces high ii rate. With the pulse current level increasing (from 1 lA to 1 mA),
S. Zhang et al. / Solid-State Electronics 81 (2013) 27–31
29
Fig. 4. Simulated contour of current flow for the device biased at Vgs = 3.3 V with Vds = 0.1 V and Vds = 25 V, respectively.
Fig. 5. Simulated vertical electric field (Ey) along the Si/SiO2 interface under avalanche breakdown.
the current flowing to the source also increase. So the ii rate at point A becomes lager. According to the simulated vertical electric field in Fig. 5 and the simulated impact ionization rate in Fig. 7, it can be concluded that positive oxide-trapped charges may generate at the bird’s beak region near source. And interface states will generate at the bird’s beak region near source and drain respectively. 5. Discussion Based on the experiment data and TCAD simulation results, two degradation mechanisms are proposed as follows: Mechanism 1: Generation of positive oxide-trapped charges at bird’s beak region near source. This mechanism plays the leading role at the beginning of the stressing, and comes to saturation later. The mechanism is confirmed by the simulated vertical electric field and impact ionization rate along the Si/SiO2 interface. Because trapping of holes in the oxide induces negative mirror charges at the bird’s
beak region near source, resulting in an effective increase in drift region concentration [13]. As a result, Ron decreases. The mechanism increases when the avalanche breakdown current increases. As the current increases, the impact ionization becomes more serious, and more hot holes can be injected into the oxide. Mechanism 2: Formation of interface state at the bird’s beak region near source and drain respectively. The second mechanism becomes obvious with the number of pulses increasing. Due to the increased scattering of the carriers at the interface states, the mobility of carriers is reduced, hence Ron will increase. This mechanism also increases with stressing current increasing. 6. Conclusion The off-state avalanche-breakdown-induced on-resistance Ron degradation in a 40 V n-type LDMOS with step-shaped gate oxide is investigated in this paper. Ron unexpectedly decreases at the beginning of stress, which is different from the phenomenon in
S. Zhang et al. / Solid-State Electronics 81 (2013) 27–31
(
(
(
(
(
(
(
(
30
Fig. 6. Simulated 2-D impact ionization rate distribution in the device under avalanche breakdown.
Fig. 7. Simulated impact ionization rate along the Si/SiO2 interface under avalanche breakdown.
LDMOS with uniform gate oxide. Then the vertical electric field and impact ionization rate along the Si/SiO2 interface are simulated to assist in providing better physical insights. Based on the experiment data and TCAD simulation results, two degradation mecha-
nisms are proposed. That is the generation of positive oxidetrapped charges at the bird’s beak region near source and formation of interface state at the bird’s beak region near source and drain respectively.
S. Zhang et al. / Solid-State Electronics 81 (2013) 27–31
References [1] Chen JF, Lee JR, Wu K-M, Huang T-Y, Liu CM, Hsu SL. Off-state avalanchebreakdown-induced on-resistance degradation in lateral DMOS transistors. IEEE Electr Dev Lett 2007;28(11):1033–5. [2] Pendharkar S, Efland T, Tsai C.-Y. Analysis of high current breakdown and UIS behavior of Resurf LDMOS (RLDMOS) devices. In: Proc symp power semicond devices ICs; 1998. p. 419–22. [3] Shekar MS, Williams RK, Cornell M, Luo M.-Y, Darwish M. Hot electron degradation and unclamped inductive switching in submicron 60-V lateral DMOS. In: Proc int rel phys symp; 1998. p. 383–90. [4] Moens P, den bosch GV, De Keukeleire C, Degraeve R, Tack M, Groeseneken G. Hot hole degradation effects in lateral nDMOS transistors. IEEE Trans Elec Dev 2004;51(10):1704–10. [5] Chen JF, Tian K-S, Chen S-Y, Wu K-M, Shih JR, Wu K. An investigation on anomalous hot-carrier-induced on-resistance reduction in n-type LDMOS transistors. IEEE Trans Dev Mater Rel 2009;9(3):459–64. [6] Brisbin D. Strachan A, Chaparala P. Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications. In: Proc int rel phys symp; 2002. p. 105–10.
31
[7] Chen JF, Tian K-S, Chen S-Y, Wu K-M, Liu CM. On-resistance degradation induced by hot-carrier injection in LDMOS transistors with STI in the drift region. IEEE Elec Dev Lett 2008;29(9):1071–3. [8] O’Donovan V, Whiston S, Deignan A, Chleirigh CN. Hot carrier reliability of lateral DMOS transistors. In: Proc IEEE int rel phys symp; 2000. p. 174–9. [9] Manzini S, Contiero C. Hot-electron-induced degradation in high-voltage submicron DMOS transistors. In: Proc int rel phys symp; 1996. p. 65–9. [10] Versari R, Pieracci A, Manzini S, Contiero C, Ricco B. Hot-carrier reliability in submicrometer LDMOS transistors. In: IEDM tech dig; 1997. p. 371–4. [11] Chen JF, Lee JR, Wu K-M, Huang T-Y, Liu CM. Mechanism and improvement of on-resistance degradation induced by avalanche breakdown in lateral DMOS transistors. IEEE Trans Elec Dev 2008;55(8):2259–62. [12] Liu Siyang, Sun Weifeng, Qian Qinsong, Zhu Jing. Comparisons of hot-carrier degradation behavior in SOI–LIGBT and SOI–LDMOS with different stress conditions. Solid-State Electron 2010;54(12):1598–601. [13] Zhang Shifeng, Han Yan, Ding Koubao, Zhang Bin, Hu Jiaxian. Investigation on hot-carrier-induced degradation of SOI NLIGBT. Microelectron Reliab 2011;51(6):1097–104.