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On-chip testing of embedded p.l.a.s.
784
World Abstracts on Microelectronics and Reliability
Bayes nonparametric estimation of time-dependent failure rate. A. G. COLOMBO, D. COSTANTINI and R. J. JAARSMA. IEEE Trans. Reliab. R-34 (2) 109 (1985). This paper discusses Bayes nonparametric estimation of time-dependent failure rates. A point and an interval estimate of the quantiles of the failure process are given for both complete and censored samples. The prior degree-of-belief about the failure rate is expressed in the form of a hypothetical sample. A numerical example is discussed. Integration of reliability and capacity in performance measure of a telecommunication network. K. K. AGGARWAL. IEEE Trans. Reliab. R-34 (2) 184 (1985). Two important characteristics for the performance of a telecommunication network are its reliability and capacity. Previous analytic methods have been used either to determine the reliability or capacity disregarding the other parameter. This leads to erroneous conclusion about the performance of the network. This paper suggests a method to integrate these two important measures by defining a weighted reliability index. The states which lead to at least one available path between the terminal nodes are identified and probability of each of these is multiplied by a normalized weight. The sum of these products is the performance index of the network. An example illustrates the method and thereafter several practical situations are discussed. Failure analysis of ECL memories by means of voltage contrast measurements and advanced preparation techniques. A. DALLMAN, G. MENZEL, R. WEYL and F. Fox. 23 a. Proc. Reliab. Phys. Symp. 224 (1985). After 4-6 weeks of testing, the computer installed ECL 100K memories showed defects such as loss of stored information. To analyse the failures, the ceramic housing of some samples were opened and the protection layers were removed. The preparation of the memories left any detectable characteristics uninfluenced. By means of SEM scanning and cross sectioning Al-fingers could be found which were located between the bit lines (2nd level metallization) and the collector contacts (1 st level metallization). These irregularities appeared in nearly all cells, both the intact and defect cells. To perform voltage contrast measurements in the first level metallization, holes of about 5 #m in diameter were prepared into the isolation oxide. As a result of the voltage contrast measurements, the bit line voltage levels were reproducibly too low and the signals of the world lines and the collector contacts of defect and intact memory cells were very different. These results suggested failures in the isolation oxide, which led in conjunction with the Al-fingers to conduction bridges between the bit lines and the substrate or the collector contacts. In order to ensure this suggestion, some Al-fingers were eliminated by applying an etching process as well as soft Nd-YAG laser pulses. In both cases some defect memory cells could be "repaired". On-chip testing of embedded p.l.a.s.P. WARMA,A. P. AMBLER and K. BAKER. J. Instn Electron. Radio Engrs 55 (9) 306 (1985). Rising test generation costs, compounded by the problem of module inaccessibility, have led to a surge of interest in self-testing methods for p.l.a.s. This paper considers the problems associated with the on-chip testing of p.l.a.s, deeply embedded in v.l.s.i, systems and presents a method of on-chip testing which uses the input/output registers of the p.l.a, as test aids. An 8-input x 45 product term x 6-output built-in testable p.l.a., which has been implemented in n.m.o.s., is described. Units of equipment available using cannibalization for repairpart support. DONALD L. BYRKETT. IEEE Trans. Reliab. R-34 (1) 25 (1985). This paper presents a mathematical model to predict the number of units of equipment available in the future. The components of this equipment are subject to Poisson failures and replacements are obtained by canni-
balization. A numerical example is presented, and some difficulties encountered in the practical application of this model are discussed.
Addressable inverter matrix for process and device characterRation. MARTIN G. BUEHLERand HOSHYARR. SAYAH.SolidSt. Technol. 185 (1985). The addressable inverter matrix consists of 222 invcrters each accessible with the aid of a shift register. The structure has proven useful in characterizing the variability of inverter transfer curves and in diagnosing processing faults. For good 3 #m CMOS bulk inverters investigated in this study, ~ standard deviation of the inverter threshold voltage was less than one percent and the inverter gain (the slope of the inverter transfer curve at the inverter threshold voltage) was less than three percent. The average noise margin for the inverters was near 2 V for a Voo of 5 V. The specific faults studied included undersize pull-down transistor widths and various open contacts in the matrix. On reliability evaluation by network decomposition. ALI M. RUSrtDL IEEE Trans. Reliab. R-33 (5) 379 (1984). A simple algorithm for evaluating the symbolic terminal-pair reliability of a complex system is presented. The system graph is decomposed into two subgraphs through a minimal cut. The system success is expressed in terms of certain successes of these subgraphs, and then changed into an equivalent disjoint expression which is directly converted on a one-to-one basis into a reliability expression. It yields unusually simple reliability expressions. The algorithm can be computerized but has not been done. Three examples illustrate the algorithm and compare it with other algorithms. A system reliability model with classes of failures. ANNA HAC. IEEE Trans. Reliab. R-34 (1) 29 (1985). This paper presents an approach to system reliability involving s-dependence of the workload as well as the system configuration. Four classes of failures are described and then incorporated into the workload model. Mean time to failure and the system reliability are the functions of parameters estimated by monitoring a real system. The model allows multiple classes of users and priority requests to be represented. The model is validated using measurement data collected in an IBM installation. Reliability assurance during the production of telecommunications equipment D. SCHLOSSER. Feinwerktechn. Messtechn. 93 (4) 207 (1985). (In German.) A report is given of measures taken and results obtained during the production of equipment used on the earth and which, in contrast to space devices, is accessible (multiplex equipment, wiring systems for wire-bound transmission and directional radio apparatus). The aim of the techniques described is to supply equipment which as far as possible guarantee troublefree operation within the serviceability period called for by the customer, which in some cases exceeds one and a half decades. The effects of the reliability assurance measures in the manufacturing plant on the costs of material inventories, manufacture and testing, as well as on processing times, necessitate, in addition, a continuous critical examination of their effectiveness and expedience. The linear software reliability model and uniform testing. MARTIN TRACHTENBERG. IEEE Trans. Reliab. R-34 (1) 8 (1985). The Jelinski-Moranda, Shooman, and Musa software reliability models all predict that the software error detection rate in a software system is a linear function of the detected errors. The basic differences among the models are that the error rates are, respectively, in terms of calendartime, manpower, and computer-time. The models are simple to use for estimating the number of errors still in the tested software. Published studies generally show that error rates during system testing correlate best with the Musa model, and
World Abstracts on Microelectronics and Reliability
Bayes nonparametric estimation of time-dependent failure rate. A. G. COLOMBO, D. COSTANTINI and R. J. JAARSMA. IEEE Trans. Reliab. R-34 (2) 109 (1985). This paper discusses Bayes nonparametric estimation of time-dependent failure rates. A point and an interval estimate of the quantiles of the failure process are given for both complete and censored samples. The prior degree-of-belief about the failure rate is expressed in the form of a hypothetical sample. A numerical example is discussed. Integration of reliability and capacity in performance measure of a telecommunication network. K. K. AGGARWAL. IEEE Trans. Reliab. R-34 (2) 184 (1985). Two important characteristics for the performance of a telecommunication network are its reliability and capacity. Previous analytic methods have been used either to determine the reliability or capacity disregarding the other parameter. This leads to erroneous conclusion about the performance of the network. This paper suggests a method to integrate these two important measures by defining a weighted reliability index. The states which lead to at least one available path between the terminal nodes are identified and probability of each of these is multiplied by a normalized weight. The sum of these products is the performance index of the network. An example illustrates the method and thereafter several practical situations are discussed. Failure analysis of ECL memories by means of voltage contrast measurements and advanced preparation techniques. A. DALLMAN, G. MENZEL, R. WEYL and F. Fox. 23 a. Proc. Reliab. Phys. Symp. 224 (1985). After 4-6 weeks of testing, the computer installed ECL 100K memories showed defects such as loss of stored information. To analyse the failures, the ceramic housing of some samples were opened and the protection layers were removed. The preparation of the memories left any detectable characteristics uninfluenced. By means of SEM scanning and cross sectioning Al-fingers could be found which were located between the bit lines (2nd level metallization) and the collector contacts (1 st level metallization). These irregularities appeared in nearly all cells, both the intact and defect cells. To perform voltage contrast measurements in the first level metallization, holes of about 5 #m in diameter were prepared into the isolation oxide. As a result of the voltage contrast measurements, the bit line voltage levels were reproducibly too low and the signals of the world lines and the collector contacts of defect and intact memory cells were very different. These results suggested failures in the isolation oxide, which led in conjunction with the Al-fingers to conduction bridges between the bit lines and the substrate or the collector contacts. In order to ensure this suggestion, some Al-fingers were eliminated by applying an etching process as well as soft Nd-YAG laser pulses. In both cases some defect memory cells could be "repaired". On-chip testing of embedded p.l.a.s.P. WARMA,A. P. AMBLER and K. BAKER. J. Instn Electron. Radio Engrs 55 (9) 306 (1985). Rising test generation costs, compounded by the problem of module inaccessibility, have led to a surge of interest in self-testing methods for p.l.a.s. This paper considers the problems associated with the on-chip testing of p.l.a.s, deeply embedded in v.l.s.i, systems and presents a method of on-chip testing which uses the input/output registers of the p.l.a, as test aids. An 8-input x 45 product term x 6-output built-in testable p.l.a., which has been implemented in n.m.o.s., is described. Units of equipment available using cannibalization for repairpart support. DONALD L. BYRKETT. IEEE Trans. Reliab. R-34 (1) 25 (1985). This paper presents a mathematical model to predict the number of units of equipment available in the future. The components of this equipment are subject to Poisson failures and replacements are obtained by canni-
balization. A numerical example is presented, and some difficulties encountered in the practical application of this model are discussed.
Addressable inverter matrix for process and device characterRation. MARTIN G. BUEHLERand HOSHYARR. SAYAH.SolidSt. Technol. 185 (1985). The addressable inverter matrix consists of 222 invcrters each accessible with the aid of a shift register. The structure has proven useful in characterizing the variability of inverter transfer curves and in diagnosing processing faults. For good 3 #m CMOS bulk inverters investigated in this study, ~ standard deviation of the inverter threshold voltage was less than one percent and the inverter gain (the slope of the inverter transfer curve at the inverter threshold voltage) was less than three percent. The average noise margin for the inverters was near 2 V for a Voo of 5 V. The specific faults studied included undersize pull-down transistor widths and various open contacts in the matrix. On reliability evaluation by network decomposition. ALI M. RUSrtDL IEEE Trans. Reliab. R-33 (5) 379 (1984). A simple algorithm for evaluating the symbolic terminal-pair reliability of a complex system is presented. The system graph is decomposed into two subgraphs through a minimal cut. The system success is expressed in terms of certain successes of these subgraphs, and then changed into an equivalent disjoint expression which is directly converted on a one-to-one basis into a reliability expression. It yields unusually simple reliability expressions. The algorithm can be computerized but has not been done. Three examples illustrate the algorithm and compare it with other algorithms. A system reliability model with classes of failures. ANNA HAC. IEEE Trans. Reliab. R-34 (1) 29 (1985). This paper presents an approach to system reliability involving s-dependence of the workload as well as the system configuration. Four classes of failures are described and then incorporated into the workload model. Mean time to failure and the system reliability are the functions of parameters estimated by monitoring a real system. The model allows multiple classes of users and priority requests to be represented. The model is validated using measurement data collected in an IBM installation. Reliability assurance during the production of telecommunications equipment D. SCHLOSSER. Feinwerktechn. Messtechn. 93 (4) 207 (1985). (In German.) A report is given of measures taken and results obtained during the production of equipment used on the earth and which, in contrast to space devices, is accessible (multiplex equipment, wiring systems for wire-bound transmission and directional radio apparatus). The aim of the techniques described is to supply equipment which as far as possible guarantee troublefree operation within the serviceability period called for by the customer, which in some cases exceeds one and a half decades. The effects of the reliability assurance measures in the manufacturing plant on the costs of material inventories, manufacture and testing, as well as on processing times, necessitate, in addition, a continuous critical examination of their effectiveness and expedience. The linear software reliability model and uniform testing. MARTIN TRACHTENBERG. IEEE Trans. Reliab. R-34 (1) 8 (1985). The Jelinski-Moranda, Shooman, and Musa software reliability models all predict that the software error detection rate in a software system is a linear function of the detected errors. The basic differences among the models are that the error rates are, respectively, in terms of calendartime, manpower, and computer-time. The models are simple to use for estimating the number of errors still in the tested software. Published studies generally show that error rates during system testing correlate best with the Musa model, and