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Parasitic breakdown control in HVIC process integration
Microelectronic Engineering 15 (1991) 377-380 Elsevier
377
Parasitic breakdown control in HVIC process integration A.F.J. Murray, W.A. Lane, C.G. Cahill, J.D. Barrett Institute of Advanced Microelectronics, National Microelectronics Research Centre, University College, Lee Maltings, Prospect Row, Cork, Ireland. Abstract This paper presents an investigation of two problems crucial to parasitic control in HVIC's." The first is a spacing problem, where the breakdown of an n-well is shown to be critically dependent on the spacing to the field-implant. The second is a wiring problem, where a grounded polysilicon field plate is used to prevent inversion of the silicon surface under a 200-V wire. 1. ~ T R O D U C T I O N High-voltage integrated circuits (HVIC's) are needed for applications such as motor drivers, switching power supplies, flat panel displays for personal and laptop computers, and telecommunications. High voltage LDMOS devices have been implemented in existing low voltage CMOS processes [1], allowing high-voltage transistors to be integrated on the same chip as low voltage control circuitry. The RESURF principle [2] has been used to fabricate LDMOS devices in a thin epitaxial layer with junction isolation, and obtain breakdown voltages in excess of 1000-V [3]. With such a wide range of configurations available, control of parasitics at high voltages becomes important in the design of HVIC's. Generally, the parasitics are associated with: 1. technological constraints imposed by the process which are unimportant in the low voltage case, but become critical when high-voltage operation is needed e.g. isolation, spacing. 2. circuit related problems encountered when running high voltage lines between devices. These are often at voltages higher than the highest supply e.g. chargep u m p e d gate control for MOSFETs in high-side drivers. 2. N - W E L L T O F I E L D I M P L A N T
SPACING
Specifically, we investigated a 200-V HVIC process obtained by modifying a 5#m15-V analogue n-well CMOS process. The p-substrate is doped at 1E15cm -3. The 0167-9317/91/$3.50 © 1991 - Elsevier Science Publishers B.V. All rights reserved.
378
A.F.J. Murray et aL / Parasitic breakdown control
surface concentration of the n-well is 5.5E15cm -3. The junction depth is 6.7/zm. A field-threshold adjust implant (surface concentration 7E16cm -3) is necessary to prevent inversion of the silicon surface under field oxide, and to isolate n-wells; for the low voltage case, this implant causes no problems. However, for HVIC's, voltages approaching the 'natural' well breakdown are needed, and so careful spacing of the field implant/guard band is needed. i
~. 0
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i
i
40_ 35_
39C 36C 33C 30C 270. 240. 21C 18C 15C 12C
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-4 -2 0 2 4 6 Misalignment (Microns)
8
10 11
]
20_ ~ . ~ ,.] 5
,
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10 15 20 25 30 35 40 45 50 Breakdown (Volts*l O)
Figure 2: Measured breakdown for n-well, and n-well with field implant across a Figure 1: Breakdown Voltage vs Misalignwafer. Left hatch is n-well, right hatch is ment. n-well with field implant. We have investigated this spacing problem by taking 3/zm as the nominal spacing, and 'misaligning' this by plus or minus 4prn. 3#m is the design rule spacing for the lowvoltage circuitry. Fig. 1 shows simulated n-well breakdown versus misalignment, carried out using PISCES2B. The nominal 3pro spacing (0 rnisalignment) gives a breakdown well below the n-well value, and so clearly the minimum acceptable worstcase spacing is 7/~m (drawn) for the high-voltage circuitry. This will keep us at the 'natural' well breakdown up to - 2 p m misalignment. Experimental support for these simulations is shown in fig. 2, which gives histogram plots of measured data, showing breakdown of the n-well both with and without the field-threshold implant. The measured breakdown is 175-V for a drawn spacing of 3#rn. For the nominal spacing of 3/zrn the simulated value is 188-V. Breakdown occurs at the n-well-field implant junction at the surface (fig. 3). The measured spread lies well within the simulated range. Discrepancy between the measured and simulated well 'natural' breakdown is probably due to the 3D spherical nature of the real well corners. [4,5]. 3. W I R I N G
The second problem does not occur in low voltage CMOS, as field thresholds are set to be greater than VDn; (our Vt! is set to 22-V). In order to run 200-V lines between devices, a polysilicon field plate technique is adopted (fig. 4). A 1.5/zrn CVD oxide between grounded poly and metal lines now supports the 200 volts.
A.EJ. Murray et aL / Parasitic breakdown control
379
A problem could potentially occur at the edge of the polysilicon field plate, where too thin a field oxide thickness could lead to either inversion or avalanche breakdown at the n-well surface due to high electric fields. However, the full two-carrier impact ionisation model in PISCES2B has shown that for an oxide thickness of l # m , the hole concentration at the surface only reaches ~ 10%m -a at 200-V (fig. 5). Also, despite an electric field of ~ 3.2ESV/cm at the field plate edge (fig. 6), the current between well and substrate did not exceed 1E-11 Amps/micron at 200-V. The breakdown voltage was found to be 288-V (407-V without the field plate). *x',2 ~ . . . . . ._-_ _ -; - " "aE'?T.-.==5.._ ]"i /
g
200-V
- - -
/
~20 o c o
4~
Distant@
P-substrate
(microns) $ PISCES2D 51[¥4CO D a t a SytSamB
4 FEB-91
Figure 3: Junction and depletion region spreading at reverse bias of 145V for device with p-implant misaligned by -4pro, showing total current vectors corresponding to the area of impact ionisation.
Figure 4: Schematic of grounded field-plate structure. Dimensions are in microns. N-well and field implant are 7#m drawn apart.
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8 12 16 2 0 2 4 Distance (Microns)
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Figure 6: Electric field O.lpm inside siliFigure 5: Hole concentration along silicon con surface at 200-V. Spike corresponds to surface at 200-V. field-plate edge. Fig. 7 shows how the electric fields at the silicon surface and in the oxide vary with a
380
A.F.J. Murray et aL / Parasitic breakdown control
CVD oxide thickness of 1.5pro and a variable field oxide thickness, and with a field oxide thickness of l#rn and a variable CVD oxide thickness. For a fixed field oxide thickness of l # m and a variable CVD oxide thickness of 0.5 to 1.5#m, the oxide field varies from 4.5E+06 to 2.05E+06 V / c m respectively. The surface field varies from 3.6E+05 to 3.2E+05 V/cm. For a fixed CVD oxide thickness of 1.5#m and a variable field oxide thickness of 0.5 to 1.4#m, the oxide field remains constant at 2.05E+06 V/cm, and the surface field varies from 4.40E+06 to 2.65E+05 V / c m respectively. As might be expected, the peak oxide field occurred at the poly field plate corner and is generally higher than acceptable for CVD oxide reliability. Technological constraints prohibit thicknesses greater than this so some form of field plate contouring is appropriate.
4
Figure 7: Variation in surface and oxide fields for varying CVD and field oxide thicknesses. (Inverted triangle shows variation in oxide field for changing CVD oxide and constant field oxide thicknesses. Triangle shows variation in surface field for same. Square shows variation in oxide field for changing field oxide and constant CVD oxide thicknesses. Circle shows variation in surface field for same.)
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I I t I 1.2 0.4 0.6 0.8 1 Oxide Thickness (Microns)
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4. C O N C L U S I O N S In order avoid premature breakdown of the high voltage devices, n-well to field implant spacing is vital. A spacing of 3pro drawn is needed for the low voltage circuitry, and 7prn drawn for the high voltage circuitry. A grounded polysilicon field plate has effectively stopped inversion of the silicon surface at 200-V, but created an oxide reliability problem in it's place. 5. A C K N O W L E D G E M E N T S
This work was funded by the International Fund for Ireland. Special thanks is also due to Orla O' Halloran for testing the devices. 6. R E F E R E N C E S [1] M.R. Duncan et al, E S S D E R C 89, p. 535. [2] J.A. Appels et al, I E D M Tech. Dig., paper 10.1, p. 238, 1979. [3] M.F. Chang et al, I E E E Trans. on Electron Devices, vol. ED-33, p. 1992, 1986. [4] S.M. Sze et al, Solid-State Electronics, vol. 9, p. 831, 1966. [5] A. Yabuta et al, I E E E Trans. on Electron Devices, vol. ED-37, p. 1132, 1990.
377
Parasitic breakdown control in HVIC process integration A.F.J. Murray, W.A. Lane, C.G. Cahill, J.D. Barrett Institute of Advanced Microelectronics, National Microelectronics Research Centre, University College, Lee Maltings, Prospect Row, Cork, Ireland. Abstract This paper presents an investigation of two problems crucial to parasitic control in HVIC's." The first is a spacing problem, where the breakdown of an n-well is shown to be critically dependent on the spacing to the field-implant. The second is a wiring problem, where a grounded polysilicon field plate is used to prevent inversion of the silicon surface under a 200-V wire. 1. ~ T R O D U C T I O N High-voltage integrated circuits (HVIC's) are needed for applications such as motor drivers, switching power supplies, flat panel displays for personal and laptop computers, and telecommunications. High voltage LDMOS devices have been implemented in existing low voltage CMOS processes [1], allowing high-voltage transistors to be integrated on the same chip as low voltage control circuitry. The RESURF principle [2] has been used to fabricate LDMOS devices in a thin epitaxial layer with junction isolation, and obtain breakdown voltages in excess of 1000-V [3]. With such a wide range of configurations available, control of parasitics at high voltages becomes important in the design of HVIC's. Generally, the parasitics are associated with: 1. technological constraints imposed by the process which are unimportant in the low voltage case, but become critical when high-voltage operation is needed e.g. isolation, spacing. 2. circuit related problems encountered when running high voltage lines between devices. These are often at voltages higher than the highest supply e.g. chargep u m p e d gate control for MOSFETs in high-side drivers. 2. N - W E L L T O F I E L D I M P L A N T
SPACING
Specifically, we investigated a 200-V HVIC process obtained by modifying a 5#m15-V analogue n-well CMOS process. The p-substrate is doped at 1E15cm -3. The 0167-9317/91/$3.50 © 1991 - Elsevier Science Publishers B.V. All rights reserved.
378
A.F.J. Murray et aL / Parasitic breakdown control
surface concentration of the n-well is 5.5E15cm -3. The junction depth is 6.7/zm. A field-threshold adjust implant (surface concentration 7E16cm -3) is necessary to prevent inversion of the silicon surface under field oxide, and to isolate n-wells; for the low voltage case, this implant causes no problems. However, for HVIC's, voltages approaching the 'natural' well breakdown are needed, and so careful spacing of the field implant/guard band is needed. i
~. 0
>~. > ,.n
i
i
40_ 35_
39C 36C 33C 30C 270. 240. 21C 18C 15C 12C
30_ 25_
~ "6 6
z
15_ 10_ 5_ L3 0
-6
-4 -2 0 2 4 6 Misalignment (Microns)
8
10 11
]
20_ ~ . ~ ,.] 5
,
-t .~ ,
, I~.~,
r~;
10 15 20 25 30 35 40 45 50 Breakdown (Volts*l O)
Figure 2: Measured breakdown for n-well, and n-well with field implant across a Figure 1: Breakdown Voltage vs Misalignwafer. Left hatch is n-well, right hatch is ment. n-well with field implant. We have investigated this spacing problem by taking 3/zm as the nominal spacing, and 'misaligning' this by plus or minus 4prn. 3#m is the design rule spacing for the lowvoltage circuitry. Fig. 1 shows simulated n-well breakdown versus misalignment, carried out using PISCES2B. The nominal 3pro spacing (0 rnisalignment) gives a breakdown well below the n-well value, and so clearly the minimum acceptable worstcase spacing is 7/~m (drawn) for the high-voltage circuitry. This will keep us at the 'natural' well breakdown up to - 2 p m misalignment. Experimental support for these simulations is shown in fig. 2, which gives histogram plots of measured data, showing breakdown of the n-well both with and without the field-threshold implant. The measured breakdown is 175-V for a drawn spacing of 3#rn. For the nominal spacing of 3/zrn the simulated value is 188-V. Breakdown occurs at the n-well-field implant junction at the surface (fig. 3). The measured spread lies well within the simulated range. Discrepancy between the measured and simulated well 'natural' breakdown is probably due to the 3D spherical nature of the real well corners. [4,5]. 3. W I R I N G
The second problem does not occur in low voltage CMOS, as field thresholds are set to be greater than VDn; (our Vt! is set to 22-V). In order to run 200-V lines between devices, a polysilicon field plate technique is adopted (fig. 4). A 1.5/zrn CVD oxide between grounded poly and metal lines now supports the 200 volts.
A.EJ. Murray et aL / Parasitic breakdown control
379
A problem could potentially occur at the edge of the polysilicon field plate, where too thin a field oxide thickness could lead to either inversion or avalanche breakdown at the n-well surface due to high electric fields. However, the full two-carrier impact ionisation model in PISCES2B has shown that for an oxide thickness of l # m , the hole concentration at the surface only reaches ~ 10%m -a at 200-V (fig. 5). Also, despite an electric field of ~ 3.2ESV/cm at the field plate edge (fig. 6), the current between well and substrate did not exceed 1E-11 Amps/micron at 200-V. The breakdown voltage was found to be 288-V (407-V without the field plate). *x',2 ~ . . . . . ._-_ _ -; - " "aE'?T.-.==5.._ ]"i /
g
200-V
- - -
/
~20 o c o
4~
Distant@
P-substrate
(microns) $ PISCES2D 51[¥4CO D a t a SytSamB
4 FEB-91
Figure 3: Junction and depletion region spreading at reverse bias of 145V for device with p-implant misaligned by -4pro, showing total current vectors corresponding to the area of impact ionisation.
Figure 4: Schematic of grounded field-plate structure. Dimensions are in microns. N-well and field implant are 7#m drawn apart.
le16+
320t . . . . . . . .
le14+
28ojr
240+
le12~ e?,
le10+
v~
loa
o o
le6_-
-~ 0
Ie4:
-i-
oE
200.' 160_
v
12£ 8( 4O
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.
.
.
.
4
8 12 16 20 2 4 D i s t a n c e (Microns)
0 28
32
4
8 12 16 2 0 2 4 Distance (Microns)
. . . . ;1 28
32
Figure 6: Electric field O.lpm inside siliFigure 5: Hole concentration along silicon con surface at 200-V. Spike corresponds to surface at 200-V. field-plate edge. Fig. 7 shows how the electric fields at the silicon surface and in the oxide vary with a
380
A.F.J. Murray et aL / Parasitic breakdown control
CVD oxide thickness of 1.5pro and a variable field oxide thickness, and with a field oxide thickness of l#rn and a variable CVD oxide thickness. For a fixed field oxide thickness of l # m and a variable CVD oxide thickness of 0.5 to 1.5#m, the oxide field varies from 4.5E+06 to 2.05E+06 V / c m respectively. The surface field varies from 3.6E+05 to 3.2E+05 V/cm. For a fixed CVD oxide thickness of 1.5#m and a variable field oxide thickness of 0.5 to 1.4#m, the oxide field remains constant at 2.05E+06 V/cm, and the surface field varies from 4.40E+06 to 2.65E+05 V / c m respectively. As might be expected, the peak oxide field occurred at the poly field plate corner and is generally higher than acceptable for CVD oxide reliability. Technological constraints prohibit thicknesses greater than this so some form of field plate contouring is appropriate.
4
Figure 7: Variation in surface and oxide fields for varying CVD and field oxide thicknesses. (Inverted triangle shows variation in oxide field for changing CVD oxide and constant field oxide thicknesses. Triangle shows variation in surface field for same. Square shows variation in oxide field for changing field oxide and constant CVD oxide thicknesses. Circle shows variation in surface field for same.)
3.6. 3.2. 2.8. E ~o
>
2.4. 2 1.6. 1.2. 0.8_ 0.4.
~
,-,A v
0
I I t I 1.2 0.4 0.6 0.8 1 Oxide Thickness (Microns)
I 1.4
1.6
4. C O N C L U S I O N S In order avoid premature breakdown of the high voltage devices, n-well to field implant spacing is vital. A spacing of 3pro drawn is needed for the low voltage circuitry, and 7prn drawn for the high voltage circuitry. A grounded polysilicon field plate has effectively stopped inversion of the silicon surface at 200-V, but created an oxide reliability problem in it's place. 5. A C K N O W L E D G E M E N T S
This work was funded by the International Fund for Ireland. Special thanks is also due to Orla O' Halloran for testing the devices. 6. R E F E R E N C E S [1] M.R. Duncan et al, E S S D E R C 89, p. 535. [2] J.A. Appels et al, I E D M Tech. Dig., paper 10.1, p. 238, 1979. [3] M.F. Chang et al, I E E E Trans. on Electron Devices, vol. ED-33, p. 1992, 1986. [4] S.M. Sze et al, Solid-State Electronics, vol. 9, p. 831, 1966. [5] A. Yabuta et al, I E E E Trans. on Electron Devices, vol. ED-37, p. 1132, 1990.