Physical and electrical analysis of silicon dioxide thin films produced by electron-cyclotron resonance chemical-vapour deposition

J,ill ELSEVIER

MICROELECTRO~C ENGINEERING Microelectronic Engineering 36 (1997) 53-60

Physical and electrical analysis of silicon dioxide thin films produced by electron-cyclotron resonance chemical-vapour deposition D. l_andheer', L.-A. Ragnarssonb, and S. Belkouch" "National Research Council of Canada, Institute for Microstructural Sciences Ottawa, Canada, K1A 0R6 bChalmers University of Technology, Department of Solid-State Electronics S-412 96 GiSteborg, Sweden,

High-quality silicon dioxide films have been deposited in the temperature range 150-425 °C by electron-cyclotron resonance chemical-vapour deposition (ECR-CVD) using an oxygen plasma with silane introduced downstream. The interface state densities of 10 nm thick films measured by the high-low frequency CV method have values in the range of 3-5xl01°eV'tcm"2."lhirty secood anneals in flowing nitrogen in the temperature range 850-950 °C reduced the values to below the sensitivity limit, 2x10 t° eV'lem"2. The electrical performance of the films has been correlated with their silanol content as determined by Fourier-transform infrared spectroscopy and the surface and interface roughness as determined by atomic-force microscopy. Negative Fowler-Nordheim stress measurements performed on Al-gated capacitors with 19.1 nm thick films deposited at 300 °C and annealed for 30 s at 900 °C exhibited positive charging and interface state generation rates larger than as those of Al-gated capacitors with thermal oxides. The excess generation of both the positive charge and interface states can be described by processes with cross-sections of 3 - 4 x 1 0 "t9 c m 2. The nature of the interface traps and the prospects for reducing their concentration by polysilicon gate processing are discussed. 1. I N T R O D U C T I O N Plasma techniques used to produce gate insulators must be accompanied by low levels of plasma damage due to ion bombardment, UV radiation, and hydrogenrelated processes. Electron-cyclotron resonance (ECR) plasmas can meet these requirements and chemicalvapour deposition with an ECR source (ECR-CVD) using molecular oxygen and silane have been shown to produce excellent silicon dioxide films at low temperatures [1-4]. Recent work at this laboratory [4] with a single magnet source has been shown to produce oxide films free of sputter contamination from the chamber walls. This is a consequence of the buildup of oxide on the walls and the shape of the ion trajectories produced by a single magnet source in the "magnetic beach" configuration. The films have been analysed by spectroscopic ellipsometry and shown to be homogeneous with no measurable interface layer despite the fact that the initial stages of film growth are dominated by plasma oxidation [4]. The purpose of this paper is to further describe the electrical properties of the oxide films deposited by 0167-9317/97/$17.00 © Elsevier Science B.V. All rights reserved. PIR S0167-9317(97)00014-2

ECR-CVD and the factors that have an influence on these properties. A series of films deposited on silicon at substrate temperatures in the range 150-425 °C have been analysed for their hydrogen content using Fourier transform infrared spectroscopy (FTIR), and their interface quality using an atomic force microscope (AFM). Al-gated capacitors with 10 nm thick oxides on silicon substrates have been fabricated and measured using the high-low capacitance-voltage (CV) technique to determine the interface state density and trapped charge as a function of deposition temperature. Silicon dioxide films with measurable concentrations of hydrogen-bearing species might be vulnerable to post-processing damage during heat treatments [5] such as polysilicon gate-implant anneals. To assess whether these oxides would improve during the processing that would accompany the fabrication of full metal-oxide-semiconductor (MOS) field-effect transistors, some films were given 30 s post-deposition anneals (POAs) in the temperature range 850-950 °C. Some of the interface states in as-deposited films are passivated by hydrogen during processing and a post-metallization anneal (PMA) at elevated

54

D. Landheer et aL / Microelectronic Engineering 36 (1997) 53-60

temperatures passivates most of the remaining states. Hot electrons injected into the oxide at fluences Qi,~ >-10.3 C/cm ,2 in the "trap-creation" regime, release hy:lrogen from defects near the anode [6]. This results in the creation of interface states. Measuring the density of interface states generated by injecting hot electrons by Fowler-Nordheim tunnelling (FNT) is a simple way of characterizing the Si/SiO 2 interface, giving a more complete assessment of their quality than measurements of the trapped charge or interface state density in asdeposited or hydrogen-annealed films. FNT stress also results in the generation of positive charge in the oxide, primarily near the interfaces [7]. Injection of high fluences from the gate using high fields results in positive charge which contains both anomalous positive charge (APC or slow states) and trapped hole components [8,9]. In this paper the interface state and positive charge generation caused by FNT injection has been assessed for 18-20 nm thick ECR-CVD oxides given a 30 s POA at 900 °C and the results compared to those obtained for thermal oxides grown at 1050 °C. For these studies the hot electrons were injected from A1 gates using fields > 9.0 MV/cm.

2. EXPERIMENTAL The oxides were deposited in a multi-chamber stainless vacuum system designed for the processing of I00 mm diameter silicon wafers in ultra-high vacuum [3]. The passive parts of the system are maintained at a pressure of<3xl0* Pa, but the base pressure in the ECR chamber was higher due to residual water from previous depositions. Si (100) wafers, 5 ~ - c m p-type, were given a modified RCA clean [3] which ended with a 2 min immersion in 1% HF solution, a final 5 min rinse in DI water and a nitrogen blow dry. After transfer of the wafers into the the ECR chamber 100 sccm o f t 2 was introduced into the single magnet source (ASTEX S1000) resulting in oxygen partial pressures of 0.54 Pa (4.1 mTorr). A 13 cm diameter gas distribution ring introduced 1 sccm of a 1:3 SiH4/He mixture at a plane 15 cm from the wafer. To create the plasma 230 W of microwave power at 2.54 Ghz was applied, resulting in an absorbed power of 190 W. Depositions were done with the substrate heater set to temperatures between 150 and 425 °C, as measured with a thermocouple pressed against the back of the wafer. The sample stage potential was held at +5V, just above floating potential,

to produce a small cathodic field across the oxide. From langmuir probe measurements it was estimated [4] that ions reach the surface with about 10 eV of energy. Some samples were given a 30 s post-deposition anneal in flowing nitrogen in a rapid thermal annealing system immediately after removal from the deposition system. A Nicolet Model 550 Fourier transform infrared spectrometer was used to measure the absorbance of 100 nm thick films. The intensity of the Sill and water peaks at 2260 and 3420 cm -1, respectively, were below the sensitivityof the instrument. The frequency and FWHM of the Si-O asymmetric stretch vibration and the absorbance of the SiOH peak at 3650 cm "1 were obtained from the spectra and the concentration of silanol was calculated using the sensitivity factor of Pliskin [10]. The thickness of the films was determined using a single-wavelength ellipsometer (Rudolph Scientific AutoEl I~ operating at a wavelength of 633 nm. For the 100 nm films the refractive index was also calculated. A Park Scientific Instruments (model SFM-BD2210) atomic force microscope operating in the contact mode was used to determine the root-mean-square deviations of the surface height R,.,= of 10 nm thick films. An average of 4 measurements over separate 2 I.tm x 2 lam areas were made on each sample and some of the areas were remeasured to ensure that the surface remained unaffected by previous scans. Other pieces of the same samples were etched for two minutes in 2% I-IF acid, rinsed for 5 minutes in DI water, blown dry, and analysed to get a measure of the roughness of the underlying Si/SiO 2 interface. An as-received wafer was given the same treatment to assess the contribution of the original substrate condition to the roughness measurements. Electrical measurements were made on films 8-20 nm thick. Al-gated capacitors with areas in the range 1-6 xl0 -~cm2were formed by evaporation through a shadow mask followed by a 20 minute anneal in forming gas at 380 °C. InGa eutectic was used for the back contact. Quasi-static capacitance-voltage (QSCV) measurements were performed by scanning from inversion to accumulation at a ramp rate of 0.1 V/s and 1 MHz (HFCV) measurements were performed by stepping at a rate of one 0.1 V step per second. Interface state densities were obtained using the high-low method [11] following the procedure described by Uren and Brunson [12] to determine the gate voltage at midgap Vms,oxide capacitance C~ and substrate doping. The centroid of the areal density of trapped charge N, was calculated from

D. Landheer et al./Microelectronic Engineering 36 (1997) 53-60 the flatband voltage, Vm using the expression N , = Co~(V~-Vt~'qA, where Va, is the flatband voltage shift for the AI/SIO~dSiMOS diode in the absence of trapped charge, A is the capacitor area, and q the electron charge. Films 18-20 nm thick for the Fowler-Nordheim injections were deposited at 150 and 300 °C and given a 30 s POA at 900 °C in flowing nitrogen. For comparison thermal oxides 18.5 nm thick, also on 5 f~cm p-type substrates, were prepared by thermal oxidation using an ultra-dry oxygen process at 1050 °C. A current density of 10"4 AJcm2 was injected from the gate and the required gate voltage was recorded. Injection was stopped periodically to obtain the QSCV and HFCV curves and the data were analysed assuming a constant gate oxide capacitance and substrate doping during each run. For these measurements the calculated value of the midgap capacitance was used to obtain the midgap voltage from the HFCV characteristics. The flatband voltage V~ and the threshold voltage V,h, were determined using the HFCV curve and the calculated flatband and threshold capacitances. The total areal density of interface states Ni, was obtained from the stretch-out of the I-tI:L-Wcurve between V~ and V,h using the relationship aN,,=Co~(AV~-,~VI~)/qA. It is often assumed that the interface states are acceptor-like above midgap and donor-like below midgap, a behaviour characteristic of the Pb centre [ 13]. During the FNT measurements, the change in the centroid of the areal density of charge in the bulk/,No, can then be related to the change in the midgap voltage aV,,s by AN~ = Co,zaV~/qA. If the energy level separating donor- and acceptor-like behaviour occurs for a gate voltage Vo ~ V,,s,/,N°~ may include a contribution from positive (I/o > V,~) or negative interface (Vo < V~) charges. The increase in the bulk trapped charge and interface states were simulated using a simple linear kinetic model that uses a summation over j traps with capture cross-sectious ¢3 and areal densities N~ of the form ,~N(Q~,) = ~F N~[1-exp(-Q,,a/q)]. Fits of the paratr~ters ~ and aj to the measured data were obtained using this equation in a Levenberg-Marquardt routine that minimizes X2. To assess whether charge nontmiformities or hydrogen passivation of the Boron dopant in the substrate were significantly effecting the CV measurements, the procedure first used by Brews and Lopez [14] and described in Ref. [15] was used to calculate the doping concentration at several points

55

during the FNT stress experiments. This method calculates the doping from the capacitance in the depletion region of the HFCV curve. Although some deviations in effective doping density were observed they were not large enough to significantly effect the calculated values of interface state density or trapped charge.

3. RESULTS AND DISCUSSION 3.1. Physical Characteristics The deposition rate and silanol content of the 100 nm thick films are shown in Fig. (1). The silanol concentration decreases with increasing temperature since hydrogen species are more easily desorbed at higher tenveratures. The silanol concentration measured for the oxide deposited at 300 °C (0.4 wt %) corresponds to lx1015 hydrogen atoms/cm2 in a 100 nm thick film. This is close to the sensitivity limit for the measurement which is -0.2 wt % (as SiOH). In comparison, the SiOH concentration measured for RPECVD oxides deposited at temperatures above 200"C was estimated to be below the sensitivity limit of 0.5-1 at. % (0.4-0.8 wt %) [16]. After 30 s anneals in nitrogen in the temperature range between 850 and 950 °C no silanol can be detected in any of the films. In fact, it has been shown that the OH groups can be eliminated from oxide films by annealing in vacuum at temperatures as low as 400 °C [ 16]. The relation between the FWHM and frequency of the Si-O asymmetric stretch vibration for the data shown in Fig. (2) falls on the "universal curve" described in Ref. [17] and our values are closer to those observed for thermal oxides than those reported for unannealed oxide films produced by RPECVD [17]. For fully-relaxed 1

-

w

-

,

-

i

•

|

-

i

1.4

-

2.2._, 2.1

1.2 "

~

~ l pl ~

1.0 0.8

2.0

O

0.6 ~,

1.9

0.4 1.8-

0.2

1.7-

0.0 i50" 2 ~ 250 3 0 0 3 5 0 400 Deposition Temp. (°C)

450

Figure 1. Deposition rate and silanol content vs deposition temperature.

D. Landheer et al./Microelectronic Engineering 36 (1997) 53-60

56 1069

,

-

.

-

,

-

•

-

w

-

i

83

---o-- Freq. •r

1068

82

~ 1067. ~1066

80".-7

1065' 1 5 0 2 0 0 250 " 300 " 350 " 400 Deposition Temp. (°C)

79 450

Figure 2. Frequency and FWHM of the Si-O stretch vibration vs deposition t e ~ a t u r e . thermal oxides >50 nm thick the value of the stretch frequency is 1078.5 cm"~[18], larger than the highest value, 1068 cm -~, observed in Fig. (2). As-grown thermal oxides with a refractive index of 1.466, the average value measured for the ECR-CVD oxides, have a stretch frequency of 1073.5 cm"t [19]. The refractive index of the films is almost constant with deposition temperature, varying from 1.465 to 1.468 between 150 and 425 *C. This small variation indicates that density variations are not responsible for the observed shift of the stretch frequency. The decrease in silanol concentration at higher temperatures should result in a frequency shift in the direction opposite to that observed [20]. It can be concluded that the as-deposited ECR-CVD oxides have a somewhat different network structure than thermal oxides. The results of the AFM measurements do not show 4.0

-6 ' ~- D m unannealed

,--, 3.5,

- - o - - D~

3.0 "7

--o--

Nt

'"- Nt unannealed

o~ 2.5

-5

significant variations with deposition temperature and there is no significant difference between the results for the as-deposited samples and those annealed for 30 s at 900 °C in nitrogen. Although there is some scattering in the data it is apparent that the etched surfaces (R,,,, = 0.10) are significantly rougher than the unetched ones (R,~ = 0.08). The as-received wafer had a value of R,,,~ = 0.08 nm after the HF dip and DI water rinse. These results indicate that the ECR-CVD deposition slightly increased the roughness of the Si/SiO 2 interface but this is not evident at the oxide surface. The R,,~ value obtained by AFM is considerably lower than the R, (average of the absolute value of the height deviations) value of 0.3 nm reported by Ohmi et aL [21] for silicon wafers given a dip in 0.5 % HF. This discrepancy could represent instrumental variations or the fact that we have used smoother wafers for our measurements. The low R,~ is consistent with the low interface state densities reported here. 3.2 Interface

61

~>0

-4.2

l.O 800

-i SSO 9(10 9:50 Annealing Temp. (~C)

•

•

•

•

•

150" 200" 250" 300" 350" 4~0

0 1000

Figure 3. Midgap interface state density D ~ and trapped charge Nt vs temperature for 30 s POAs.

a)

450

900 °C POA

-3 ~ • •

B

~" t.5

Charge

no POA

-2

,~ 2.0

States and Trapped

The midgap interface state density decreases for 30 s POAs, reaching a minimum at 900 °C for the film deposited at 150 ~C, as shown in Fig. (3). For this reason subsequent POAs were performed at 900 °C. The Crapped charge N t also shown in Fig. (3) decreases with increasing temperature and is still decreasing at the highest POA temperature (950 °C) investigated here. Figs. (4) and (5) show, respectively, D~, and N t as a function of deposition temperature for unannealed

0

$ •

b)

8

150 " 200 250 " 3(10 " 3 5 0 " Deposition Temp. (°C)

400 " 450

Figure 4. Midgap interface state density D ~ vs deposition temperature: a) unannealed films, b) films given a 30 s POA at 900 °C.

D. Landheer et al./Microelectronic Engineering 36 (1997) 53-60

i

-6

•

i

•

-

i

•

i

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i

-

i

/

•

•

-4.

• •

•

•

a)

2

~'~

no POA

.~ -~

Z"

0 150 " 2 0 0 " 2 5 0 " 3 0 0 " 3.50 " 4 0 0

450

57

referred to as "parasitic" or "subcutaneous oxidation"). The results indicate that the silane fragments, including hydrogen, present during the initial ECR plasma oxidation do not result in significant degradation of the interface. Since the oxidation of 2-3 nm occurs in a few seconds [4], these fragments may simply not have time to do damage before the reactive sites are occupied by oxygen.

9 0 0 *C P O A

-6

-~ _

0

1........... 1 •

150

200

•

•

250

300

* •

350

b)

•

400

450

Deposition Temp. (°12) Figure 5. Trapped charge N, for the films of Fig. (4). films and those given a 30 s POA at 900 *C. None of the data show a strong variation with deposition temperature; however, D ~ exhibits a significant decrease after the 900 °C anneal. The 18.5 am thick thermal oxide capacitors used for the FNT stress ~ e m e n t s had an initial value of D ~ = 1.0xl0t°eV%m "2,which is close to the estimated limit of sensitivity of 2x10 ~°eV'lcm"2 for 5 ~-cm substrates (p. 354 in Ref. [15]). This sample also had an initial negative trapped charge of N, = -2.3x10 tl cm"2. Since oxides usually have a positive fixed charge this indicates that at least some of the negative charge observed in the ECR oxides after the 30 s POAs is a result of the Al gate processing. Thus, the values of N, for the annealed films shown in Figs. (3) and (5b) may have been lower directly after removal from the annealing furnace and before evaporation of the gates. The values of D ~ in Fig. (4) can be compared to those obtained using the two step RPECVD process described by Lucovsky et al. [22]. Their interface state densities are very similar to those reported here. The temperature window for the first step of their process was 200 - 300 *C and higher temperatures produced higher interface state densities. With a pre-deposition layer produced at 300"C the interface state density was insensitive to the temperature of the deposition step in the range 200-400 *C. It was hypothesized that the preoxidation step is necessary since it excludes hydrogen during formation of the Si/SiO2 interface and hydrogen exposure was observed to lead to an increase in D~,. In our single step ECR-CVD process the first stage of growth is dominated by a plasma oxidation (variously

3.3. Fowler-Nordheim Stress Prior to the Fowler-Nordheim stress measurements, the current was measured as a function of applied voltage for capacitors made from all three oxides, the thermal oxide and the ECR-CVD oxides deposited at 150 and 350 *C and annealed for 30 s at 900 °C. All yielded characteristics free of trapping ledges and exhibited breakdown fields >10 MV/cm. The barrier heights for injection from the aluminium cathode were obtained from Fowler-Nordheim plots. These relate the density of injected current J and barrier height 0~ using the expression J = CEexp(-B/E), with B = 4(2m.')~(qbb)~/(3lgl) and C a constant. A value of the reduced electron mass m," = 0.4 [23] was used in these calculations, and E, the field near the gate, was calculated from the applied potential, and the flatband voltage shiR for the Al-SiO~tSi MOS structure. For the deposited oxides and the thermal oxide a value ~ = 3.1 eV was obtained. This compares with a reported value of 3.2 eV [23]. The initial potentials (thickness; field) required to inject a current of 10~ AJcm2 during the FNT stress measurements were, for the thermal oxide -17.8 V (18.5 nm; 9.0 MV/cm), for the 150 °C deposited oxide -19.3 V (19.9 nm; 9.2 MV/cm), and for the 300 ~C deposited oxide -19.5 V (19.1 rim; 9.7 MV/cm). The potentials required to maintain a constant current varied by :e0.1 V. By comparing the maximum shift in gate voltage with the change of flatband voltage it can be estimated that the trapped charge is within 1 nm of the Si/SiO 2 interface [24]. This is consistent with previous observations [7] which show that bulk negative charges are detrapped by the high-fields used for the injection. Figs. (6) shows the interface state density as a function of energy above the valence band edge for several values of the injected charge for the ECR-CVD oxide deposited at 300 °C. The data exhibits a hump above midgap, a feature which has been observed to be prominent in thermal oxides after avalanche electron injection [25, 26], Fowler-Nordheim injection from the substrate [27-29], or exposure to atomic hydrogen [30].

58

D. Landheer et al./ Microelectronic Engineering 36 (1997) 53-60 to

4

~k"

1'0"4A/cm" '

"

'1 ]I

i

1 ~

3"

afterPMA104 AJcm2 • •

"~O 2-

~ _~---"- ~

m•

1 f

0.4

0.2

016 E - E (eV)

018

1.0

0.00

•

0.02

0.04

0.06

300 *C

0.08

0.I0

Fluence(C/c•2) Figure 6. Density of interface states as a function of energy above the valence band edge for an oxide film deposited at 300 *(2 and given a 30 s POA at 900 °C. a) 0.0 C / c • 2, b) 9.7x10 "4C/cm~, c) 5.6x10 "J C/cm2, d) 0.016 C/cm2. The increase in the number of interface states ,aN, and trapped charges zuVo,are shown for the thermal oxide and the deposited films as a function of injected charge in Figs. (7) and (8). respectively. The parameters obtained by fitting the linear kinetic model for the thermal oxide and the oxide deposited at 300 °(I are summarized in Table (1). It was found that aN,, and zxN~, could be well fit using two traps. In each case, using three traps did not significantly reduce X2 while one trap models led to a significant increase. The fits are shown as the solid lines in Figs. (7) and (8). The value of Nu for our thermal oxide has an initial slope that is not resolved with the fluence increments used in the measurements of Fig. (7). This abrupt increase is associated with the high cross-section (a.,l) trap shown in Table (1) which is characteristic of 5

d-"

10aA/cm• " after PMA • •• • 3/ •ll

4-

"-2 2-

'•

-

,

"

~.I..

•

~

m• f

• I50*C o * 300"(2 • thermal

l-

O~ 0.00

0.02

o.~

o.lz

o.bs

o.to

Fluence (C/cm 2) Figure 7. Change in the density of interface states ,~V, obtained vs charge injected from the AI gate for capacitors with deposited and thermal oxide.

Figure 8. Change in the trapped charge zNo, obtained from the shiftsin V,~ vs charge injected from the AI gate for the films of Fig. (7). interface states associated with trapped holes. The concentrationfor thistrap shown in Table (I) is close to that observed in M O S devices with polysilicon gates. [6,3 I]. Surprisingly, it is not seen in the deposited oxides, indicating that they may have a lower concentrationof the oxygen vacancies near the interface responsible for hole trapping [32]. Using injection from Al gates at fields of 9.5 M V / c m on 30 n m thermal oxide films Vuillaun~ et al. [28] found a cross-section for interfacestate generation at midgap of 7x10 "18c m "2.This is higher than the crosssections(a.., 2) for the second trap shown for both oxides in Table (I) ( 2.4xI0 is cm'2). They calculated a saturation value for Di, = 4x10 n e V % m "2 at ambient temperature, consistent with the trap concentration for our thermal oxide. The rate of interface state generation for the deposited films observed in Fig. (7) is considerably larger than that observed for the thermal oxide film. The second interface trap for the oxide deposited at 300 °C has a cross-section (qa) and concentration comparable to that observed for the thermal oxide. It is the trap in the deposited oxide with cross-section ~,1 = 3.3x10"19 cm ~, not observed for the thermal oxide, that is associated with the high-fluence increase in Di,~ in the deposited oxide and we speculate that it may be related to a non-P~ centre pro&wed by hydrogen exposure [30]. Our cross-sections and trap densities for positive charge generation in the 300 °C deposited oxide also are corapared with those for the thermal oxide in Table (1). Two traps were observed by Roh et al. [27] for APC generation in rapid-thermal oxides. They suggested that the smaller cross-section (Oo,I = 5x10 "t9 cm "2) trap was

D. Landheer et al. / Microelectronic Engineering 36 (1997) 53-60

59

Table 1 Parameters extracted from data of Fi[s. (7) and (8) usin[ linear kinetic models with two tra[as.

Ni#

~#

Ni,2

a~,2

No#

Oo.

No,2

Oo#

(cm':)

(cm"2)

(cm"2)

(cm"~)

(cm"2)

(cm"~)

(cm"2)

(cm'~)

ECR-CVD 300 °C

1.1 xl013

3.3 xl0 a9

2.9 xl012

5.0 xl0 -is

1.1 xl013

3.9 xl0 -19

1.1 xl012

1.6 xl0 -iv

thermal 1050°(=

2.1 xl0 n

>1 xl0 -16

2.0 xl0 t2

2.4 xl0 -is

2.5 xl0 n

1.8 xl0 -Is

9.2 xl0 H

3.6 xl0 -.7

associated with the APC generation mechanism of DiMaria et al. [6] in which hydrogen creates APC without the generation of holes. The first positive charge trap and the first interface trap for the 300 °C deposited oxide in Table (1) have comparable densities and crosssections with values (3-4x10 a9 cm'2). It should be kept in mind that some of the slow states (APC) will respond with lime constants shorter than the inverse of the sweep rate used in these measurements [33] and these will cause a stretch-out of the CV curves which will increase the calculated interface state density. At the same time, it is possible that the APC and interface states with this cross-section are associated with the same creation mechanism. Inoue et al. [29] have suggested that the interface states generated in the upper half of the bandgap observed in Fig. (6) are trivalent silicon dangling bonds or oxygen dangling bonds (non-bridging oxygen) within a few angstroms of the interface. The same defects further away from the interface could be responsible for the APC states. Either of these defects could be created directly if hy:lrogen broke weak Si-O bonds. They could also be created if hydrogen atoms recombined with the hydrogen on Si-H (creating silicon dangling bonds) or Si-OH (creating non-bridging oxygen) groups. The rate for the generation of interface traps by atomic hydrogen reported by Cartier and Stathis [30] requires orders of magnitude more hydrogen than has been measured by FTIR in our films, thus it is likely that the presence of carriers enhances the generation rate. The parameters for the low cross-section (at#) positive charge trap in the thermal oxide in Table (1) are quite different from that for the deposited oxide, but they may still be related to the same defect. The discrepancy may be a consequence of the oversimplification represented by the linear-kinetic model which obscures the details of a complicated process involving the release of hydrogen by hot electrons, its transport to the

interface, and the formation of traps. The high-cross-section trap observed by Roll et al. [27] (Ooa = l x l 0 "17 c m "2) they attributed to the interaction of hydrogen with trapped holes. It has a comparable cross-section and concentration for the deposited and thermal oxides in Table (1), indicating that the deposited oxide films have levels of holetrapping comparable to that of the thermal oxide, in contradiction to the observations for the interface state generation, where it was concluded that the deposited oxides had lower levels of hole trapping. 4. CONCLUSIONS The as-deposited oxides produced by ECR-CVD have midgap interface state densities that are scattered around 3-5x101° eV'lcm"2, relatively independent of deposition temperature. A 30 s anneal at 900 °C reduces this by a factor of 2-3. The lowest value of interface state density measured, D ~ = 1.2xl0~°eV'lcm'2 was obtained for a sample deposited at 350 °C and annealed for 30 s at 900 °C but lower values might be attainable because the n~as~n'~nts are at the limit of their sensitivity. The levels of trapped charge in the films after 30 s postdeposition anneals were comparable to those observed for thermal oxide films, probably limited by the Al gate processing. These results show that the films deposited using the one-step ECR-CVD process have interfaces comparable to those produced by the two-step RPECVD process. Although the Si/SiO~ interface may be slightly rougher than the as-received wafer, these measurements coupled with previous measurements testifying to the purity and homogeneity of these films, makes them a promising candidate for gate insulators in MOS devices, particularly those that are limited to low thermal budgets. The Fowler-Nor~eim stress re~asurements indicate

60

D. Landheer et al. / Microelectronic Engineering 36 (1997) 53-60

that the deposited oxides have hole trapping rates comparable to or lower than that of thermal oxides. It is apparent, however, that at the highest injected fluence for our experiments (0.1 C/cmZ), the interface state density and trapped positive charge after injection is larger for the oxide deposited at 300 °C than for the thermal oxide produced at 1050 °C. More work needs to be done to determine the exact nature of the species responsible for the excess trap generation. It has been shown that polysilicon gate processing results in a dramatic improvement in the electrical properties of the oxides produced by RPECVD [34], likely by a combination of h~drogen reduction and defect precursor annealing. This is likely to be true also for the oxides produced by ECR-CVD.

Acknowledgements We would like to thank M. Tomiinson for technical assistance, and J. EIIUl of Northern Telecom Electronics who provided the thermal oxide samples.

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