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Physical and electrical characterization of Ni–Si Phase transformation
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Thin Solid Films 517 (2008) 1186 – 1190 www.elsevier.com/locate/tsf
Physical and electrical characterization of Ni–Si Phase transformation S.Y. Tan a,⁎, Chih-Wei Chen b , I-Tse Chen c , Chu-Wei Feng c a
c
Department of Electrical Engineering, Chinese Culture University, Taipei 111, Taiwan, ROC b Institute off Microelectronics, National Cheng Kung University, Tania 701, Taiwan, ROC Graduate Institute of Materials Science and Nanotechnology, Chinese Culture University, Taipei 111, Taiwan, ROC Available online 1 July 2008
Abstract The thermal stability and phase characteristics involved in processing nickel silicided films formed on three different gate dielectric layers (SiO2, HfSiO, and HfO2) were investigated. The electrical properties and surface morphology of Ni-Silicides formed by Ni–Si solid-state reaction were examined by X-ray diffraction (XRD), sheet resistance, atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), and capacitance–voltage (C–V) curves. Results show that the Ni-Silicide formations undergo a phase transformation from a low resistivity-NiSi to a high resistivity-NiSi2 phase, which has a strong dependence on annealing temperature despite underlying gate dielectric materials. It has been found that a mixed-phase of Ni2Si, NiSi and NiSi2 was commonly observed during phase transformation. A unique integration process was developed to obtain a thermally stable NiSi phase at high temperatures, which proved to delay the conversion of intermediate silicide phases to its terminal phase (NiSi2) effectively. The focus of the present work is to facilitate the correlations of Ni–Si phase transformation with its electrical and morphological properties. © 2008 Elsevier B.V. All rights reserved. Keywords: Phase transformation; Electrical property; Silicidation; Nickel silicide
1. Introduction The Ni/Si solid-state reaction has been studied widely in recent years [1–4]. The increasing use of nickel silicide as the contact material for leading-edge CMOS devices is evident upon comparing some of the key properties of NiSi with CoSi2 and TiSi2. Scaling down CMOS devices requires eliminating gate depletion. A fully silicided (FUSI) metal gate can eliminate gate depletion by an equivalent oxide thickness (EOT) of 0.2 to 0.3 nm for sub-45 nm node and beyond [5–7]. NiSi is potentially an attractive material due to its low resistivity, less consumption of Si, and its capability to maintain low resistivity even for channel lengths down to 0.1 μm [5,8,9]. However, NiSi is not a thermodynamically stable phase, as it converts to the higher resistivity phase of NiSi2. More seriously, in the thickness range of interest to silicide applications, NiSi agglomeration takes place at even lower temperatures than normally expected from a phase
⁎ Corresponding author. Tel.: +886 972172847; fax: +886 2 2862 5230. E-mail address: [email protected] (S.Y. Tan). 0040-6090/$ - see front matter © 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2008.06.087
transition [3,4]. Therefore, the thermal stability of NiSi thin film and the phase transformation from NiSi to NiSi2 are important for understanding the properties of Ni-FUSI and improving the device fabrication processes. In this paper we demonstrated a unique silicide formation process to maintain a thermal stable of NiSi phase at high processing temperatures regardless underlying gate dielectric materials. The key element to achieve this challenge is to introduce a fine tuned two-step annealing process. Several measurement techniques such as XRD, Resistivity, AFM, CV and XPS were carried out to understand its physical and electrical properties. The correlations between its electrical and morphological changes during Ni–Si phase transformation were established. 2. Experiments P type (100) oriented silicon substrates were used to obtain three different gate structures, Ni-FUSI/poly-Si/SiO2, Ni-FUSI/ poly-Si/HfO2 and Ni-FUSI/poly-Si/HfSiO stacks. The Ni-FUSI gate stacks were fabricated using a modified conventional CMOS flows. For gate dielectric fabrications, SiO2 layers were
S.Y. Tan et al. / Thin Solid Films 517 (2008) 1186–1190
thermally grown by dry oxidation (SiO2) of 2 nm using a Vertical Furnace system at temperature around 800 °C. HfO2 and HfSiO with thickness of 8 nm were deposited by metal organic chemical vapor deposition (MOCVD) at temperature of 500 °C with O2 gas and deposited rate at 0.6 nm/min. The undoped Poly-Si layers of about 100 nm were deposited using a low-pressure chemical vapor deposition (LPCVD) with temperature at around 620 °C. Samples were then implanted with As having dosage of 8 × 1015 cm− 2 and implant energy of 20 keV, followed by a soak annealing at 1100 °C in N2 ambient for 5 s. On the other hand, some samples were left without implantation as references. The implant equipment was Varian Ion Implant Systems-E220HP/E500HP Implanter. After Poly-Si deposition, the Ni film was deposited by using a metal-physics vapor deposition (PVD) technique with deposition rate at 1 nm/s. The film thickness of Ni was 65 nm to ensure the tNi/tSi thickness ratio at ~0.65 (65 nm/100 nm). The fully silicidation (FUSI) was carried out by using a two-step annealing process. The first anneal step was done at a low temperature of 400 °C for 120 s in an N2 ambient after depositing nickel films. The unreacted nickel was etched away by NH4OH:H2O2:H2O solution. A second annealing step was at a higher temperatures ranging from 550 °C to 850 °C for 60 s in an N2 ambient. The process sequences can be schematically presented using a unified scheme as shown in Fig. 1. To study the kinetics of Ni–Si phase transformation stacking on three different gate dielectric materials, samples were characterized by X-ray diffraction (XRD) using Cu Kα radiation for phase identification. Besides, the electrical sheet resistance of nickel silicide film was measured by four-point probe to correlate with XRD data. The topography of films was captured by Digital Instruments AFM since AFM images are convenient to calculate the surface roughness and characterize the grain size distribution of nickel silicide films. For the XPS measurements, Al Kα excitation and a VG Scientific Microlab 310F electron analyzer were used. The base pressure was ~ 10− 9 Torr for the XPS measurements. The capacitance– voltage (C–V) of metal-insulator-semiconductor (MIS) capaci-
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Fig. 2. A. XRD patterns of nickel silicide on SiO2 films (20 Å) for deposited Ni to Poly-Si thickness ratio at 0.65 and different temperatures for second annealing process at 550 °C, 700 °C, and 850 °C. B. XRD patterns of nickel silicide on HfO2 films (80 Å) for deposited Ni to Poly-Si thickness ratio at 0.65 and different temperatures for second annealing process at 550°C, 700 °C, and 850 °C. C. XRD patterns of nickel silicide on HfSiO films (80 Å) for deposited Ni to Poly-Si thickness ratio at 0.65 and different temperatures for second annealing process at 550 °C, 700 °C, and 850 °C.
tors was measured using Agilent 4155 precision semiconductor parameter analyzer and Agilent 4284A impedance analyzer. 3. Results and discussion 3.1. X-ray diffraction analysis
Fig. 1. A schematic diagram of integration flow for Ni-FUSI formation.
Several silicide phases have been found in the Ni–Si system. During the stages of the nickel reaction with silicon, at low temperature, Ni-rich phases formed. Ni2Si is generally the predominated phase at low temperatures and early stage of the reaction, forming a layer that grows by diffusion-limited kinetics [10,11]. At higher temperatures and as Ni is consumed, NiSi nucleates and grows by diffusion-limited kinetics. As the reaction proceeds for the case of a Ni film on a Si substrate, NiSi
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grows fully consuming the Ni-rich silicides. NiSi2 nucleates and grows at higher temperatures. The formation of the different Ni–Si phases can also depend on the film thickness and thermal condition during the reaction [12]. In order to understand the sequence of the nickel reaction with silicon, and obtain a thermally stable of NiSi phase at high thermal budget, we introduced a unique two-step thermal annealing process. Furthermore, ion implantation of As impurities into poly-Si layer with initial Ni thickness at 65 nm during FUSI formation was considered and intent to gain the thermal stability of NiSi film, which, by pushing the phase transformation of NiSi to NiSi2 at higher temperatures. We found that the XRD data shows that Ni–Si phase change strongly depend on the second annealing temperature [3]. In Fig. 2A, B, and C, the XRD patterns show that there are two strong peaks in the 2θ at 45.331 and 47.331 after the second annealing temperature at 550 °C. Those peaks represent the existence of NiSi phase [12]. Once the thermal annealing temperature at 700 °C, the NiSi phase remained thermally stable and as a dominated phase regardless underlying gate dielectric materials. Furthermore, if a high thermal annealing temperature at 850 °C, the XRD patterns show that NiSi2 (2θ = 28.58 and 47.41) was formed on both HfO2 and SiO2 dielectric layer in a Ni–Si matrix, which co-exist with NiSi phase. Nevertheless, the XRD data show that the NiSi phase can stay thermally stable. For NiSi formed on HfSiO dielectric layer with a thickness ratio (tNi/tSi) at 0.65, NiSi remained as a primary phase in Ni–Si matrix even at temperature reaching 850 °C (Fig. 2C). HfSiO has shown more stable amount than others. Therefore, the key in leading a thermally robust NiSi is to implement a two-step thermal anneal process incorporating with high tNi/tSi ratio at 0.65. 3.2. Electrical characteristic — sheet resistance and C–V analysis To understand the stages of the Ni–Si reaction, a series of second annealing temperatures (550 °C–850 °C) was considered in the experiments. The sheet resistance measurements
Fig. 3. Sheet resistance (Rs) vs temperature of 2nd anneal process in a two-step thermal annealing Ni-FUSI process for tNi/tSi = 0.65 with either undoped poly-Si or As doped poly-Si (8 × 1015cm− 2). The increase of Rs with increasing of temperature.
Fig. 4. C–V characteristics dependence of annealing condition for HfO2 MIS capacitors. (annealing at 450 °C, 550 °C and 650 °C).
were conducted on each wafer at different experimental conditions. The average sheet resistance data was based on the origin of 49 measurement sites on each wafer. The average sheet resistance data after different thermal treatment temperatures is plotted in Fig. 3. After the first annealing step (400 °C), the average sheet resistance of all samples was maintained below 10 Ω /□. When the second annealing temperatures around at 550 °C, the average sheet resistances shift down to less than 3 Ω/□ regardless underlying gate dielectric materials (SiO2, HfO2, or HfSiO). For Ni–Si system, it is known that the formation of Ni2Si occurs at around 250 °C, and NiSi starts the agglomeration process at 600 °C [11]. The formation of NiSi2, on the other hand, is a nucleation-controlled process, which takes place at temperatures around 700–750 °C for thin NiSi films in contact with Si. In Fig. 3, sheet resistance measurement shows that when annealing the films from 700 to 850 °C, the resistance for the film continues to increase. However, although the resistance has increased to a very high value at temperatures of 850 °C, the XRD patterns show that there still exist multiphases of Ni–Si (NiSi and NiSi2). At a high temperature around 850 °C, the HfSiO samples show relatively a lower sheet resistance value amount of other gate dielectric materials at high temperatures. It implies that HfSiO is more stable at high temperatures since relatively less NiSi2 phase formed. The increase of sheet resistance is due to a higher fraction of NiSi2
Fig. 5. C–V characteristics dependence of annealing condition for HfSiO MIS capacitors. (annealing at 550 °C, 700 °C and 850 °C).
S.Y. Tan et al. / Thin Solid Films 517 (2008) 1186–1190
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Fig. 6. AFM images of Ni/Si samples annealed at different temperatures for three different dielectric materials (A) SiO2 (B) HfO2 (C) HfSiO.
phase contenting with Ni–Si matrix. A mixed-phase of NiSi and NiSi2 was commonly observed. Furthermore, Figs 4 and 5 show that the C–V characteristics were apparently affected by the annealing temperature. Large increase in equivalent oxide thickness (EOT) was observed for higher annealing temperature. HfO2 has more interface trapping density than HfSiO, indicating that HfSiO is a thermally stable gate dielectric material at high temperatures. It shows our two-step annealing process with a tNi/tSi thickness ratio at 0.65 can push the NiSi2 phase occurred at temperatures above 850 °C successfully. In addition, a mixedphase of nickel silicide (NiSi and NiSi2) can easily be identified by the value of sheet resistance after a thermal processing. The XRD patterns and sheet resistance value showed a very good correlation on identifying the phases of nickel silicide during the transformation.
~ 5.0 nm between 525 °C and 700 °C annealing. For SiO2 and HfO2 (see Fig. 6A and B), the dramatic increase of Rms at 850 °C is partly due to the irregular nucleation of NiSi2, resulting in a mixture of NiSi and NiSi2 phases, whereas relatively less on HfSiO (see Fig. 6C). Above 900 °C, the transformation of nickel silicide was completed and NiSi film was fully agglomerated and NiSi2 phase largely dominates on nickel silicide film. The mean square roughness (Rms) corresponding to the agglomeration of nickel silicide film increases sharply.
3.3. AFM analysis The surface topography of NiSi samples which having tNi/tSi ratio at 0.65 and annealed at different temperatures were obtained by AFM. In Fig. 6A, B, and C, nickel monosilicide thin films are smooth, and both the uniformity and continuity gradually degrade with the increase of annealing temperature. The Rms (mean square roughness) which corresponds to the NiSi film agglomeration increases slightly from ~ 4.0 nm to
Fig. 7. Core-electron level Si 2p spectra of nickel silicide thin films with different phase contents.
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3.4. XPS analysis Phase dependent Si 2p spectra observed at normal emission for nickel silicide layer is shown in Fig. 7. The samples with a different sheet resistance value (1.4, 81.37, and 5.1 Ω /□) were chosen for the analysis. In our works, we found that the NiSi phase has lowest sheet resistance value at less than 2 Ω/□. Once the NiSi transformed to NiSi2, the sheet resistance increases sharply to be above 120 Ω/□ due to agglomeration of NiSi films. For a Ni-riched Ni2Si, the sheet resistance is between 3– 10 Ω/□. To gain insight into the chemical nature of the Ni–Si at the surface, we analyzed the Si Auger peaks at 98.6 eV and 103.3 eV. Fig. 7 shows Si 2p peaks obtained from the surface of nickel silicide films. Once the NiSi transformed to NiSi2, The Si 2p peaks are broadened and shifted to lower binding energy with respect to a different phase of Ni–Si. Apparently the spectra shift with Ni–Si phase transformation. 4. Conclusion The phases and electrical properties of nickel-silicide films were studied by stacking with a different gate dielectric material (SiO 2, HfSiO, and HfO 2) and varying thermal anneal temperatures during nickel silicide formation. The present of NiSi as a dominant phase can stably remain at a high thermal temperature by tuning Ni to Si thickness ratio ~ 0.65 and doping with As impurities in Poly-Si. A mixed-phase of nickel silicide layer was commonly observed during phase transformation. And, it can be effectively identified by some nondestructive techniques such as sheet resistance measurement, XRD, AFM and XPS analysis. In fact, the NiSi phase has lowest sheet resistance which is less than 2 Ω/□. Once the NiSi transformed to NiSi2, the sheet resistance increases sharply to be above 120 Ω/□ due to agglomeration of NiSi films. Film agglomeration is one of the crucial parameters that influence the electrical properties of the nickel silicided films. Consistently, the phenomena can be clearly observed on a different gate dielectric material (SiO2, HfO2 and HfSiO). The electrical resistivity
change is generated by film agglomeration, corresponding to the roughness changes, phase transformation and binding energy changes. HfSiO is a thermally stable gate dielectric material at high temperatures due to a less interface trapping density. The correlations of Ni–Si phase transformation with its electrical and physical properties were established. Acknowledgments The authors would like to thank Ivy Yang, Chin-Lung Sung and Wen-Fa Wu for technical and process integration assistance at National Device Laboratories. This work was supported by the National Science Council under award no. NSC97-2221-E034-001. References [1] C. Lavoie, R. Purtell, C. Cabral, F.M. d'Heurle, J.M.E. Harper, Electrochem. Soc. Symp. 2002/11 (2002) 455. [2] O. Kazuya, A. Kanna, H. Akira, T. Yoshiaki, Mater. Res. Soc. Symp. Proc. 717 (2002) 77. [3] S.Y. Tan, C.L. Sung, W.F. Wu, J. Mater. Sci.: Mater. Electron. 18 (2007) 847. [4] S.Y. Tan, Hsien-Chia Chiu, Hu Chun-Yen, Mater. Res. Soc. Symp. Proc 958 (2007) 197. [5] H. Iwai, T. Ohgura, S. Ohmi, Microelectron. Eng. 60 (2002) 157. [6] A. Hokazono, K. Ohuchi, M. Takayanagi, Y. Watanabe, S. Magoshi, Y. Kato, T. Shimizu, et al., IEDM Tech. Dig. (2002) 639. [7] J.P. Lu, D. Miles, J. Zhao, A. Gurba, Y. Xu, C. Lin, M. Hewson, et al., IEDM Tech. Dig. (2002) 371. [8] A. Lauwers, A. Steegen, M. de potter, R. Lindsay, A. Satta, H. Bender, K. Maex, J. Vac. Sci. Technol., B 19 (2001) 2026. [9] A. Lauwers, M. de Potter, O. Chamirian, R. Lindsay, C. Demeurisse, C. Vrancken, K. Maex, Microelectron. Eng. 64 (2002) 131. [10] F. Heurle, C.S. Petersson, J.E.E. Baglin, S.J. Placa, C.Y. Wong, J. Appl. Phys. 55 (1984) 4208. [11] J.A. Kittl, A. Lauwers, O. Chamirian, M.A. Pawlak, M. Van Dal, A. Akheyar, M. De Potter, A. Kottantharayil, G. Pourtois, R. Lindsay, K. Maex, Mater. Res. Soc., Symp. Proc. 810 (2004) 31. [12] J.A. Kittl, A. Lauwers, M.A. Pawlak, M. Van Dal, A. Veloso, K.G. Anil, G. Pourtois, C. Demeurisse, T. Schram, B. Brijs, M. De Potter, C. Vrancken, K. Maex, Microelectron. Eng. 82 (2005) 441.
Thin Solid Films 517 (2008) 1186 – 1190 www.elsevier.com/locate/tsf
Physical and electrical characterization of Ni–Si Phase transformation S.Y. Tan a,⁎, Chih-Wei Chen b , I-Tse Chen c , Chu-Wei Feng c a
c
Department of Electrical Engineering, Chinese Culture University, Taipei 111, Taiwan, ROC b Institute off Microelectronics, National Cheng Kung University, Tania 701, Taiwan, ROC Graduate Institute of Materials Science and Nanotechnology, Chinese Culture University, Taipei 111, Taiwan, ROC Available online 1 July 2008
Abstract The thermal stability and phase characteristics involved in processing nickel silicided films formed on three different gate dielectric layers (SiO2, HfSiO, and HfO2) were investigated. The electrical properties and surface morphology of Ni-Silicides formed by Ni–Si solid-state reaction were examined by X-ray diffraction (XRD), sheet resistance, atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), and capacitance–voltage (C–V) curves. Results show that the Ni-Silicide formations undergo a phase transformation from a low resistivity-NiSi to a high resistivity-NiSi2 phase, which has a strong dependence on annealing temperature despite underlying gate dielectric materials. It has been found that a mixed-phase of Ni2Si, NiSi and NiSi2 was commonly observed during phase transformation. A unique integration process was developed to obtain a thermally stable NiSi phase at high temperatures, which proved to delay the conversion of intermediate silicide phases to its terminal phase (NiSi2) effectively. The focus of the present work is to facilitate the correlations of Ni–Si phase transformation with its electrical and morphological properties. © 2008 Elsevier B.V. All rights reserved. Keywords: Phase transformation; Electrical property; Silicidation; Nickel silicide
1. Introduction The Ni/Si solid-state reaction has been studied widely in recent years [1–4]. The increasing use of nickel silicide as the contact material for leading-edge CMOS devices is evident upon comparing some of the key properties of NiSi with CoSi2 and TiSi2. Scaling down CMOS devices requires eliminating gate depletion. A fully silicided (FUSI) metal gate can eliminate gate depletion by an equivalent oxide thickness (EOT) of 0.2 to 0.3 nm for sub-45 nm node and beyond [5–7]. NiSi is potentially an attractive material due to its low resistivity, less consumption of Si, and its capability to maintain low resistivity even for channel lengths down to 0.1 μm [5,8,9]. However, NiSi is not a thermodynamically stable phase, as it converts to the higher resistivity phase of NiSi2. More seriously, in the thickness range of interest to silicide applications, NiSi agglomeration takes place at even lower temperatures than normally expected from a phase
⁎ Corresponding author. Tel.: +886 972172847; fax: +886 2 2862 5230. E-mail address: [email protected] (S.Y. Tan). 0040-6090/$ - see front matter © 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2008.06.087
transition [3,4]. Therefore, the thermal stability of NiSi thin film and the phase transformation from NiSi to NiSi2 are important for understanding the properties of Ni-FUSI and improving the device fabrication processes. In this paper we demonstrated a unique silicide formation process to maintain a thermal stable of NiSi phase at high processing temperatures regardless underlying gate dielectric materials. The key element to achieve this challenge is to introduce a fine tuned two-step annealing process. Several measurement techniques such as XRD, Resistivity, AFM, CV and XPS were carried out to understand its physical and electrical properties. The correlations between its electrical and morphological changes during Ni–Si phase transformation were established. 2. Experiments P type (100) oriented silicon substrates were used to obtain three different gate structures, Ni-FUSI/poly-Si/SiO2, Ni-FUSI/ poly-Si/HfO2 and Ni-FUSI/poly-Si/HfSiO stacks. The Ni-FUSI gate stacks were fabricated using a modified conventional CMOS flows. For gate dielectric fabrications, SiO2 layers were
S.Y. Tan et al. / Thin Solid Films 517 (2008) 1186–1190
thermally grown by dry oxidation (SiO2) of 2 nm using a Vertical Furnace system at temperature around 800 °C. HfO2 and HfSiO with thickness of 8 nm were deposited by metal organic chemical vapor deposition (MOCVD) at temperature of 500 °C with O2 gas and deposited rate at 0.6 nm/min. The undoped Poly-Si layers of about 100 nm were deposited using a low-pressure chemical vapor deposition (LPCVD) with temperature at around 620 °C. Samples were then implanted with As having dosage of 8 × 1015 cm− 2 and implant energy of 20 keV, followed by a soak annealing at 1100 °C in N2 ambient for 5 s. On the other hand, some samples were left without implantation as references. The implant equipment was Varian Ion Implant Systems-E220HP/E500HP Implanter. After Poly-Si deposition, the Ni film was deposited by using a metal-physics vapor deposition (PVD) technique with deposition rate at 1 nm/s. The film thickness of Ni was 65 nm to ensure the tNi/tSi thickness ratio at ~0.65 (65 nm/100 nm). The fully silicidation (FUSI) was carried out by using a two-step annealing process. The first anneal step was done at a low temperature of 400 °C for 120 s in an N2 ambient after depositing nickel films. The unreacted nickel was etched away by NH4OH:H2O2:H2O solution. A second annealing step was at a higher temperatures ranging from 550 °C to 850 °C for 60 s in an N2 ambient. The process sequences can be schematically presented using a unified scheme as shown in Fig. 1. To study the kinetics of Ni–Si phase transformation stacking on three different gate dielectric materials, samples were characterized by X-ray diffraction (XRD) using Cu Kα radiation for phase identification. Besides, the electrical sheet resistance of nickel silicide film was measured by four-point probe to correlate with XRD data. The topography of films was captured by Digital Instruments AFM since AFM images are convenient to calculate the surface roughness and characterize the grain size distribution of nickel silicide films. For the XPS measurements, Al Kα excitation and a VG Scientific Microlab 310F electron analyzer were used. The base pressure was ~ 10− 9 Torr for the XPS measurements. The capacitance– voltage (C–V) of metal-insulator-semiconductor (MIS) capaci-
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Fig. 2. A. XRD patterns of nickel silicide on SiO2 films (20 Å) for deposited Ni to Poly-Si thickness ratio at 0.65 and different temperatures for second annealing process at 550 °C, 700 °C, and 850 °C. B. XRD patterns of nickel silicide on HfO2 films (80 Å) for deposited Ni to Poly-Si thickness ratio at 0.65 and different temperatures for second annealing process at 550°C, 700 °C, and 850 °C. C. XRD patterns of nickel silicide on HfSiO films (80 Å) for deposited Ni to Poly-Si thickness ratio at 0.65 and different temperatures for second annealing process at 550 °C, 700 °C, and 850 °C.
tors was measured using Agilent 4155 precision semiconductor parameter analyzer and Agilent 4284A impedance analyzer. 3. Results and discussion 3.1. X-ray diffraction analysis
Fig. 1. A schematic diagram of integration flow for Ni-FUSI formation.
Several silicide phases have been found in the Ni–Si system. During the stages of the nickel reaction with silicon, at low temperature, Ni-rich phases formed. Ni2Si is generally the predominated phase at low temperatures and early stage of the reaction, forming a layer that grows by diffusion-limited kinetics [10,11]. At higher temperatures and as Ni is consumed, NiSi nucleates and grows by diffusion-limited kinetics. As the reaction proceeds for the case of a Ni film on a Si substrate, NiSi
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grows fully consuming the Ni-rich silicides. NiSi2 nucleates and grows at higher temperatures. The formation of the different Ni–Si phases can also depend on the film thickness and thermal condition during the reaction [12]. In order to understand the sequence of the nickel reaction with silicon, and obtain a thermally stable of NiSi phase at high thermal budget, we introduced a unique two-step thermal annealing process. Furthermore, ion implantation of As impurities into poly-Si layer with initial Ni thickness at 65 nm during FUSI formation was considered and intent to gain the thermal stability of NiSi film, which, by pushing the phase transformation of NiSi to NiSi2 at higher temperatures. We found that the XRD data shows that Ni–Si phase change strongly depend on the second annealing temperature [3]. In Fig. 2A, B, and C, the XRD patterns show that there are two strong peaks in the 2θ at 45.331 and 47.331 after the second annealing temperature at 550 °C. Those peaks represent the existence of NiSi phase [12]. Once the thermal annealing temperature at 700 °C, the NiSi phase remained thermally stable and as a dominated phase regardless underlying gate dielectric materials. Furthermore, if a high thermal annealing temperature at 850 °C, the XRD patterns show that NiSi2 (2θ = 28.58 and 47.41) was formed on both HfO2 and SiO2 dielectric layer in a Ni–Si matrix, which co-exist with NiSi phase. Nevertheless, the XRD data show that the NiSi phase can stay thermally stable. For NiSi formed on HfSiO dielectric layer with a thickness ratio (tNi/tSi) at 0.65, NiSi remained as a primary phase in Ni–Si matrix even at temperature reaching 850 °C (Fig. 2C). HfSiO has shown more stable amount than others. Therefore, the key in leading a thermally robust NiSi is to implement a two-step thermal anneal process incorporating with high tNi/tSi ratio at 0.65. 3.2. Electrical characteristic — sheet resistance and C–V analysis To understand the stages of the Ni–Si reaction, a series of second annealing temperatures (550 °C–850 °C) was considered in the experiments. The sheet resistance measurements
Fig. 3. Sheet resistance (Rs) vs temperature of 2nd anneal process in a two-step thermal annealing Ni-FUSI process for tNi/tSi = 0.65 with either undoped poly-Si or As doped poly-Si (8 × 1015cm− 2). The increase of Rs with increasing of temperature.
Fig. 4. C–V characteristics dependence of annealing condition for HfO2 MIS capacitors. (annealing at 450 °C, 550 °C and 650 °C).
were conducted on each wafer at different experimental conditions. The average sheet resistance data was based on the origin of 49 measurement sites on each wafer. The average sheet resistance data after different thermal treatment temperatures is plotted in Fig. 3. After the first annealing step (400 °C), the average sheet resistance of all samples was maintained below 10 Ω /□. When the second annealing temperatures around at 550 °C, the average sheet resistances shift down to less than 3 Ω/□ regardless underlying gate dielectric materials (SiO2, HfO2, or HfSiO). For Ni–Si system, it is known that the formation of Ni2Si occurs at around 250 °C, and NiSi starts the agglomeration process at 600 °C [11]. The formation of NiSi2, on the other hand, is a nucleation-controlled process, which takes place at temperatures around 700–750 °C for thin NiSi films in contact with Si. In Fig. 3, sheet resistance measurement shows that when annealing the films from 700 to 850 °C, the resistance for the film continues to increase. However, although the resistance has increased to a very high value at temperatures of 850 °C, the XRD patterns show that there still exist multiphases of Ni–Si (NiSi and NiSi2). At a high temperature around 850 °C, the HfSiO samples show relatively a lower sheet resistance value amount of other gate dielectric materials at high temperatures. It implies that HfSiO is more stable at high temperatures since relatively less NiSi2 phase formed. The increase of sheet resistance is due to a higher fraction of NiSi2
Fig. 5. C–V characteristics dependence of annealing condition for HfSiO MIS capacitors. (annealing at 550 °C, 700 °C and 850 °C).
S.Y. Tan et al. / Thin Solid Films 517 (2008) 1186–1190
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Fig. 6. AFM images of Ni/Si samples annealed at different temperatures for three different dielectric materials (A) SiO2 (B) HfO2 (C) HfSiO.
phase contenting with Ni–Si matrix. A mixed-phase of NiSi and NiSi2 was commonly observed. Furthermore, Figs 4 and 5 show that the C–V characteristics were apparently affected by the annealing temperature. Large increase in equivalent oxide thickness (EOT) was observed for higher annealing temperature. HfO2 has more interface trapping density than HfSiO, indicating that HfSiO is a thermally stable gate dielectric material at high temperatures. It shows our two-step annealing process with a tNi/tSi thickness ratio at 0.65 can push the NiSi2 phase occurred at temperatures above 850 °C successfully. In addition, a mixedphase of nickel silicide (NiSi and NiSi2) can easily be identified by the value of sheet resistance after a thermal processing. The XRD patterns and sheet resistance value showed a very good correlation on identifying the phases of nickel silicide during the transformation.
~ 5.0 nm between 525 °C and 700 °C annealing. For SiO2 and HfO2 (see Fig. 6A and B), the dramatic increase of Rms at 850 °C is partly due to the irregular nucleation of NiSi2, resulting in a mixture of NiSi and NiSi2 phases, whereas relatively less on HfSiO (see Fig. 6C). Above 900 °C, the transformation of nickel silicide was completed and NiSi film was fully agglomerated and NiSi2 phase largely dominates on nickel silicide film. The mean square roughness (Rms) corresponding to the agglomeration of nickel silicide film increases sharply.
3.3. AFM analysis The surface topography of NiSi samples which having tNi/tSi ratio at 0.65 and annealed at different temperatures were obtained by AFM. In Fig. 6A, B, and C, nickel monosilicide thin films are smooth, and both the uniformity and continuity gradually degrade with the increase of annealing temperature. The Rms (mean square roughness) which corresponds to the NiSi film agglomeration increases slightly from ~ 4.0 nm to
Fig. 7. Core-electron level Si 2p spectra of nickel silicide thin films with different phase contents.
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3.4. XPS analysis Phase dependent Si 2p spectra observed at normal emission for nickel silicide layer is shown in Fig. 7. The samples with a different sheet resistance value (1.4, 81.37, and 5.1 Ω /□) were chosen for the analysis. In our works, we found that the NiSi phase has lowest sheet resistance value at less than 2 Ω/□. Once the NiSi transformed to NiSi2, the sheet resistance increases sharply to be above 120 Ω/□ due to agglomeration of NiSi films. For a Ni-riched Ni2Si, the sheet resistance is between 3– 10 Ω/□. To gain insight into the chemical nature of the Ni–Si at the surface, we analyzed the Si Auger peaks at 98.6 eV and 103.3 eV. Fig. 7 shows Si 2p peaks obtained from the surface of nickel silicide films. Once the NiSi transformed to NiSi2, The Si 2p peaks are broadened and shifted to lower binding energy with respect to a different phase of Ni–Si. Apparently the spectra shift with Ni–Si phase transformation. 4. Conclusion The phases and electrical properties of nickel-silicide films were studied by stacking with a different gate dielectric material (SiO 2, HfSiO, and HfO 2) and varying thermal anneal temperatures during nickel silicide formation. The present of NiSi as a dominant phase can stably remain at a high thermal temperature by tuning Ni to Si thickness ratio ~ 0.65 and doping with As impurities in Poly-Si. A mixed-phase of nickel silicide layer was commonly observed during phase transformation. And, it can be effectively identified by some nondestructive techniques such as sheet resistance measurement, XRD, AFM and XPS analysis. In fact, the NiSi phase has lowest sheet resistance which is less than 2 Ω/□. Once the NiSi transformed to NiSi2, the sheet resistance increases sharply to be above 120 Ω/□ due to agglomeration of NiSi films. Film agglomeration is one of the crucial parameters that influence the electrical properties of the nickel silicided films. Consistently, the phenomena can be clearly observed on a different gate dielectric material (SiO2, HfO2 and HfSiO). The electrical resistivity
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