Preliminary analysis of RISC architectures performance

North-Holland Microprocessing and Microprogramming 14 (1984) 133-137

133

Preliminary Analysis of RISC Architectures Performance Helnye Azaria Dept. of Electrical and Computer Engineering, Ben-Gurion University of the Negev Beer Sheva 84 105, Israel Analysing architecture performance is a step of utmost importance and interest in the process of computer architecture design. The paper deals particularly with special architectures of the Reduced Instruction Set Computer Space (RISCS) in order to obtain a preliminary evaluation of RISC's architectures performance and the approach to an optimal instruction set for an effective High Level Language Computer (HLLC). The new modular microcomputer consisting of instruction groups modules called MODHEL that has sdready been proposed has facilitated the investigation of the performance of a set of computers allocated within the RISCS. A comparative study of the dynamic instruction mix of four benchmark programs is performed with respect to the VAX 11/780, RISCI (Berkeley) and five versions of MODHEL. Preliminary results indicate that there is a strong chance that RISC-type computers could be designed to function as efficient low-cost systems. Keywords:

i.

Computer Performance, Computer Architecture Performance Evaluation, Special Computer Architecture, Reduced Instruction Set Computers, Instruction Modularity.

INTRODUCTION

can be obtained by using the Reduced InstrDction Set Computer (RISC) approach, E15,16,17,18~ •

The performance factor of an architecture is extremely difficult to analyse and measure: in a computer system both the implementation and the architecture affect this factor, that depends also on the kind of application. "A more proper use of the term (performance) is to equate it to efficiency of problem solution" [i~. Thinking of the efficiency of problem solution in a High Level Language Computer (HLLC), one can see that other factors are involved, too. the compiler quality and language semantics [2]. The performance evaluation tools like simulation models or building a prototype [1,3,42 give results on the performance of all the system: software + hardware + application; it is very difficult to determine the contribution of the architecture itself on the results. A better way is a comparison analysis of architectures performance utilizing the same benchmark programs, when most of the other parameters that affect performance (compiler, language) are identical or are taken into account (execution speed) ~,6,7,8~. Despite the above, the term performa n c e _ ~ i soften equated to program execution speed LI,3,4,9J that depends specially on the implementation (affects the rate of processing), but also on the architecture (affects the amount of processing). One of the most critical issues in designing an architecture of a digital computer_~i~ the establishment of the Instruction Set ~l,10j. In the last years there have been several new studies relating to new architectures for HLLC with an alternative trend to the general trend~towards architectural complexity, Much better efficiency and computing effectivity

~1,12,13,14~.

The purpose of this study has been to investigate the architecture performance of different RISC with the aim of achieving information on the performance of those computers in order to find the approach to an optimal instruction set for ~ effective HLLC. To attain this goal a special purpose modular computer denoted MODHEL has already been proposed [ 2 ~ . Its instruction set is subdivided into eight subsets of instructions or instruction modules. Basically, each module contains two to six instructions belonging to the same category according to instructions for data movement (M0), program modification (M1) , arithmetic I (M2), logic (M4) , arithmetic II (M5) , I/O (M6) , miscellaneous (M7). When all of the instruction modules are activated, the overall instruction set is verry close, but not identical, to that of RISCI [13~ . When only its basic instruction module (M0), which is essential for any computer model, is activated, MODHEL becomes a SIC (Single Instruction Computer) [ 2 ~ . The MODHEL computer is designed in such a fashion that it can function with a variety of combinations of activated instruction modules, each combination is a different MODHEL model or a different RISC, termed as • Ck(M~i). k is the number of modules in the model; ~i is a logic expression which determines what modules i the model contains. There exist 2 i = 128 models (i = 0,1,2,...7). The MODHEL is a research-oriented computer, to be used in the investigation of the performance of various computer models in the RISC space. In order to obtain a preliminary evaluation of RISC's architectures performance, we choose a

134

14. Azaria / RISC Amhitectures Performance

comparative analysis based on the same four b e n c h m a r k p r o g r a m s (three versions of p u z z l e and quicksort) b e t w e e n RISCI, VAX 11/780 [13] and five models of MODHEL: CI(M0) , C2(M01) , C2(M02) , C3(M012) , C4(M0123). The analysis consists of an approach of the instruction set usage by the computer: the d y n a m i c i n s t r u c t i o n mix. There is a tentative indication that w i t h a total of 15 instructions (with 3 instruction modules) the M O D H E L can p e r f o r m almost just as e f f e c t i v e l y as the RISCI for a large class of p r o g r a m s of the type m e n t i o n e d above. If we add one more module (4 modules in all) and a number of instructions of 19) the p e r f o r m a n c e of the four b e n c h m a r k p r o g r a m s tested, becomes almost identical to that of the RISCI. A c t u a l l y there is not that much d i f f e r e n c e in using 17 or up to 32 instructions, since in all these cases we need a 5 bit opcode field. The analysis of the b e n c h m a r k p r o g r a m s and the comparison with p r e v i o u s results is r e p o r t e d in section 2, while the results of this comparison are d i s c u s s e d in section 3. C o n c l u s i o n s are given in section 4. 2.

BENCHMARKS A N A L Y S I S AND C O M P A R I S O N

There are two p r i n c i p a l approaches to analyze instruction usage by a computer: (a) The static i n s t r u c t i o n - f r e q u e n c y count a c c o r d i n g to the p r o g r a m listing of a task. (b) The d y n a m i c frequency count of instructions of a r u n n i n g program, on a specific computer. There exists a c o r r e l a t i o n b e t w e e n the results of the two approaches ~,i0]. The d y n a m i c count, however, is more r e l e v a n t for actual p e r f o r m a n c e evaluation of computer. In order to evaluate the p e r f o r m a n c e of MODHEL, o p e r a t i n g w i t h d i f f e r e n t combinations o f instruction modules (and thus being a d i f f e r e n t computer within the RISCS for each such combination), as compared to the RISC and other computers, two b e n c h m a r k p r o g r a m s were chosen. The b e n c h m a r k p r o g r a m s were "puzzle" and "qsort"; the same b e n c h m a r k s used by the RISC designers ~13,19~. The puzzle b e n c h m a r k was also used b y the M I P S designers [123 and the qsort by Intel r e s e a r c h e r s for the e v a l u a t i o n of i~Px86 vs. Mc68ooo

~o].

The puzzle p r o g r a m contains n u m e r o u s loops. It is e s s e n t i a l l y a r e c u r s i v e b i n - p a c k i n g p r o g r a m that solves a 3-dimensional puzzle. It displays many features of typical programs. There are three versions of this program: v e r s i o n A, accesses arrays w i t h subscripts and does not declare register variables, version B, where some local variables are c o n v e r t e d into r e g i s t e r variables, and v e r s i o n C (ppuzzle), w h e r e the arrays are a c c e s s e d by u s i n g pointers. The qsort (quicksort) p r o g r a m contains n u m e r o u s procedure calls and m e m o r y accesses. The recursive qsort p r o g r a m sorts 2600 fixed-length character strings, and has r e l a t i v e l y more m e m o r y

references than m o s t p r o g r a m s (the only unusual feature), [13]. A comparison was p e r f o r m e d with the four p r o g r a m s m e n t i o n e d above: puzzle (version A), puzzle (version B), puzzle (version B) , ppuzzle (version C) and qsort. As a starting p o i n t of the study, we choose to e v a l u a t e the following models of MODHEL (those models are e s t a b l i s h e d by a c o m b i n a t i o n of modules w h i c h contain the more b a s i c instructions) MODHEL version

Instruction Modules included

The M O D H E L model

M0

M0

C I ( M 0)

M01

M 0 + M1

C2(Mo1)

M02

g 0 + M2

C2(M02)

M012

M0 + M1 + M2

C3(M012)

M0123

M0 + M 1 + M2 + M 3

C4(M0123)

A total of five models, ranging from the primitive S i C - t y p e C I ( M 0) to a four-module, 19 instruc. tions model C4(M0123), the p e r f o r m a n c e of which, as will be indicated soon, is quite close to that of the RISCI. The total amount of d y n a m i c occurrences of the instructions involved in each of the b e n c h m a r k s has been r e p o r t e d for RISCI in Figure 15 of reference [133 . Since all of the RISCI instructions can be s y n t h e s i z e d with M O D H E L m o d e l ' s instructions, as shown in Table 1 of r e f e r e n c e [21] for model C I ( M 0) (Module 0) for instance, we can calculate the same results for the MODHEL versions considered. The results of these calculations are shown in Tables 1,2,3,4. Each of these tables is dedicated to one of the b e n c h m a r k programs: puzzle A, puzzle B, p p u z z l e and qsort, respectively. A comparison w i t h respect to V A X 11/780 and RISCI is p e r f o r m e d for the five M O D H E L versions, listed above. The entries in the tables are a t t a i n e d as explained in the following example: Take for instance the case of the JMP instruction in Table i. There are 1.73×106 o c c u r r e n c e s of JMP if the puzzle is run on the RISCI. A c c o r d i n g to Table 1 of reference [213 w h i c h synthesizes RISCI Instructions with CI(M0), we n e e d one M O V - t y p e instruction of Module 0 in o r d e r to p e r f o r m a jump (JMP) instruction. Therefore we add 1.73xi06 M O V instructions to each column of MODHEL entries of Table 1 (in the M O V row of course) when the modules do not have a JMP instruction. A c c o r d i n g to Table 1 of reference [21~ we n e e d two MOV type instructions of Module 0 in order to p e r f o r m an Increment (INC) or a DECREMENT (DEC) instruction. Three M O V type instructions of Module 0 are needed in order to p e r f o r m an A D D or SUB or SHIFT instruction. The h a n d l i n g of the ADD instruction, for instance, is slightly more complicated, since the RISCI does not have the INC and M O V register to register instructions, w h i c h it replaces by an ADD. Thus, not all of the ADD instructions of RISCI

H. Azaria /RISC Amhitectures Performance

are genuine addition instructions. Therefore, in order to c a l c u l a t e the n u m b e r of a d d i t i o n instructions we have to use b o t h the V A X and the R I S C columns. Similar c o n s i d e r a t i o n s apply to the SUB instruction. The RISC uses it i n s t e a d of VAX DEC and CMP instructions as well. The h a n d l i n g of the CMP instruction in M O D H E L is as a SUB instruction. For example: (No. D E C ~ I s C I =

(No. S U B ~ I s C I -

(No.CMP) (No. I N C ~ I s C I

=

(No. I N C / D E C ) v A x 0.~0

(No. MOV R e g , -

-

=

0.0

= 0.0

( N o . DEC) R I S C I =

0.80

(No. A D D ~ I s C I -

Reg)RISC I =

(No. A D ~ X

(No. INC{IsC I = 3.32 - 1.53 - 0.80

= 0.99

N o w in order to p e r f o r m the ADD and SUB instructions of the RISC we have to add to the M 0 column (No. of M O V instructions): 2 x

(No. of I N C / D E C ~ A X + 3 x

1 x

(No. of M O V R e g , R e g ~ i s c I + 3 x (No.CMP~A x-

1.6 + 4.59

The n u m b e r s are in units of 106 instructions. Other e n t r i e s are o b t a i n e d in a similar manner. The r e s u l t s of T a b l e s 1,2,3,4 are also s u m m a r i z e d in the graphs shown in Fig. i. These graphs illustrate the a p p r o a c h i n g of the total number of i n s t r u c t i o n o c c u r r e n c e s in each b e n c h m a r k p r o g r a m to the RISCI result, as a function of the change of the c o m b i n a t i o n of M O D H E L i n s t r u c t i o n modules.

(No. SUB~A x -

= 0.82 - 0 - 0.82

VAX

135

3.

DISCUSSION

OF THE C O M P A R I S O N

The four b e n c h m a r k p r o g r a m s (puzzle (A), p u z z l e (B), p p u z z l e and qsort), whose d y n a m i c instruction m i x has b e e n c o m p a r e d in the p r e v i o u s section, a c t i v a t e d from 17 to 36% of data m o v e m e n t instructions, from 43 to 65% of a r i t h m e t i c instr u c t i o n s and from 17 to 25% of p r o g r a m control instructions, i n c l u d i n g s u b r o u t i n e calls and returns. This is a r e a s o n a b l e m i x for a test, and a l t h o u g h there is n o t e n o u g h e v i d e n c e to d r a w d e f i n i t e final conclusions, there are some quite clear indications.

(No. of A D D ~ A X + =

+ 0.99 + 2.46 = 9.64

T h e r e f o r e for the C I ( M 0) Model: M 0 M O D H E L version we need for the p u z z l e (A) p r o g r a m a total of MOV i n s t r u c t i o n s of: 20.55 w h i c h are: 2.33 for JMP + NOP + CALL + RET instructions, 9.64 for A D D + SUB instructions, 3 x (2.47) = 7.41 for 8HF instructions, 0.04 + 1.67 = 1.71 for L O A D + STORE instructions.

The e n t r i e s in T a b l e s 1,2,3,4 indicate that even if we use a t h r e e - m o d u l e v e r s i o n of M012 and compare it w i t h r e s p e c t to RISCI, we get 50% more i n s t r u c t i o n s (dynamically) for p u z z l e (A,B), 10% m o r e for p p u z z l e and only 4% m o r e for qsort. It should be r e c a l l e d that the n u m b e r of instructions in e a c h m o d u l e is: M 0 6 M O V type instructions M 1 2 JMP, 2 CALL, 1 RET = 5 i n s t r u c t i o n s M 2 2 ADD, 2 SUB, = 4 instructions. We h a v e

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H. Azaria / RISC Architectures Performance

136

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about 50% of the total of RISCI instructions. There is a tentative indication that the M012 can p e r f o r m almost just as e f f e c t i v e l y as the RISCI for a large class of p r o g r a m s of the type m e n t i o n e d above. Of course, one w o u l d have to analyze and compare m a n y more b e n c h m a r k p r o g r a m s in order to make the above statement more definite. If we add just one more module (M3) , attaining C 4 (M0123) model, the p e r f o r m a n c e for the four b e n c h m a r k p r o g r a m s tested b e c o m e s almost identical to that of the RISCI. Since Module 3 contains only 4 shift-type instructions, the total number of instructions of C 4 is 19, about 61% of RISCI. Actually, there is not that m u c h difference in using 17 or up to 32 instructions, since in all these cases we n e e d a 5-bit opcode field. P r e l i m i n a r y analysis of the M O D H E L computers' p e r f o r m a n c e c l e a r l y indicates that it makes sense to design and implement RISC-type computers. Note that simple architecture is suitable to VLSI implementation, p e r m i t s the use of well known implementation techniques and r e d u c e d compiler complexity, then design costs can certainly be reduced. C a r e f u l VLSI design, with a m i n i m u m number of chips (eventually a s i n g l e - c h i p computer with a r e a s o n a b l e on-chip MM) can achieve h i g h - s p e e d p e r f o r m a n c e (200ns or less C P U - M cycle). HLL oriented design can d e f i n i t e l y be implemented [i13, adding e n h a n c e d Processor and M e m o r y M a n a g e m e n t features will d e f i n i t e l y n a r r o w the semantic gap in this design [11. Moreover with RISC architecture it is p o s s i b l e to combine on a single-chip, processor, m e m o r y and I/O

communications which allows multiple p r o c e s s o r s to work in parallel, a v o i d i n g the p e r f o r m a n c e b o t t l e n e c k by e x e c u t i n g p r o g r a m s from its o n - c h i p m e m o r y [22~. The c u r r e n t designs of RISC and M O D H E L w i t h their h a n d l i n g of subroutine param e t e r p a s s i n g (register window) , their threeaddress i n s t r u c t i o n s - and a p a r t i c u l a r attention to create H L L - i m p l e m e n t a t i o n and I/O communications o r i e n t e d instructions are d e f i n i t e steps in this direction. N (Mi~hOn I n s b r u ( t i ~ l l

g. i. ----

2

B e n c h m a r k Programs C o m p a r i s o n Results

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H. Azaria / RISC Architectures Performance

4.

CONCLUSIONS

Ar~ investigation of the Reduced Instruction Set Computer Space (RISCS) , allocated hetween the RISCI and the SIC (CMOVE) computer systems, has been initiated. Preliminary analysis and comparison results, using four benchmark programs, whose dynamic instruction mix has been compared, were accomplished using a new, research-oriented modular computer, called MODHEL, proposed by the author 121~. The modularity of MODHEL consists of the idea of using eight instruction modules. By activating different combinations of instruction modules, the MODHEL can act as different computers within the R[SCS. As a conclusion,there is a strong chance that RISCS may contain several computer models, which could be designed to function as viable, effective, efficient low-cost systems, we can add that this points towards a revolutionary trend in the complex computer world of today, slows the Complex instruction Set Computers (CISC) and encourages additional effort in the developing and perfectioning of RISC's. REFERENCES G. J. Myers, "Advances in Computer Architecture," 2nd. ed. Wiley, New York, 1982. L2J H. M. Levy, D. W. Clark, "On the Use of Benchmarks for Measuring System Performance," Computer Architecture News, Vo.. i0, No. 6, pp. 18-23, Dec. 1982. [31 D. Ferrari, "Computer Systems Performance Evaluation," Prentice-Hall, Inc., Englewood Cliffs, N.J., 1978. L4J M. F. Morris, P. F. Roth, "Tools and Techniques Computer Performance Evaluation for effective Analysis," Van Nostrand Reinhold Data Processing Series, 1982. [5j S. H. Fuller, W. E. Burr, "Measurement and Evaluation of Alternative Computer Architectures," Computer, Vol. i0, No. i0, pp. 24-35, Oct. 1977. [6J J. R. Larus, "A Comparison of Microcode, Assembly Code and High-Level Languages on the VAX-II and RISC I," Computer Architecture News, Vol. I0, No. 5, pp. 10-15, Sept. 1982. [71 D. A. Patterson, "A Performance Evaluation of the Intel 80286," Computer Architecture News, Vol. i0, No. 5, pp. 16-18, Sept.1982. [8j P. M. Hansen et al, "A Performance Evaluation of the Intel iAPX 432," Computer Architecture News, vol. i0, No. 4, pp. 17-26, June 1982. [9] D. A. Patterson, C. H. Sequin, "A VLSI RISC" Computer, Vol. l[i, No. 9, pp. 8-21, Sept. 1982. [i0] D. A. Fairclough, "A Unique Microprocessor Instruction Set," IEEE Micro, Vol. 2, No. 2, pp. 8-18, May 1982. [ii] D. T. Fitzpatrick et al., "A RISCy Approach to VLSI," VLSI Design, Vol. 2, No. 4, pp. 14-20, Fourth Qtr. 1981.

[127 [13]

LI4~

[157

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[17~

[18]

[19]

[i~

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137

J. Hennessy et al., "The MIPS Machine," Proc. COMPCON, Spring 82, San Francisco, pp. 2-7, Feb. 1982. D. A. Patterson, C. H. Sequin, "RISCI: A Reduced Instruction Set VLSI Computer," Proc. 8th Ann. Symp. on Computer Architecture, Minneapolis, pp. 443-457, May 1981. G. madin, "The 801 Minicomputer," Proc. Symp. Architectural Support for Programming Languages and Operating Systems, pp. 39-47, March 1982. R. Bernhard, "More Hardware Means Less Software," IEEE Spectrum, Vol. 18, No. 12, pp. 30-37, Dec. 1981. D. W. Clark, W. D. Strecker, "Comments on the Case of the Reduced Instruction Set Computer," Computer Architecture News, Vol. 8, No. 6, pp. 34-38, Oct. 15, 1980. D. A. Patterson, m. R. mitzel, "The Case for the Reduced Instruction Set," Computer Archi tecture News, Vol. 8, No. 6, pp. 25-33, Oct. 25, 1980. D. A. Patterson, R. S. Peipho, "Assessing RISC's in High-Level Language Support," IEEE Micro, Vol. 2, No. 4, pp. 9-19, Nov. 1982. Y. Tamir, Simulation and Performance Evaluation of the RISC Architecture, Memorandum No. UCB/ERL M81/17, U. of CA-Berkeley, 6 April, 1981. M. Moore et al., iAPX86 System Benchmark Report,Intel Corp.,Santa Clara,CA,Feb.1982. H. Azaria, D. Tabak "The MODHEL Microcomputer for RISCS Study", Microprocessing and Microprogramming Journal, Vol.12, Dec.1983,

[221 Pete Wilson, "Thirty-Two Bit Micro Supports Multiprocessing," Computer Design, pp. 143-150, June i, 1984. Helnye Azaria received the "Diplome d'Ingenieur d'Electronique" at the Ecole Polytechnique Feminine, Paris, (Sceaux) France in 1964, the M.Sc. in Electrical Engineering from the Technion, Haifa, Israel in 1972, the Ph.D. in Electrical and Computing Engineering from the Ben-Gurion University of the Negev, Beer-Sheva, Israel in 1983. From 1964 to 1970 Ms. Azaria was employed by the Nuclear Research Center, Negev, Israel and since 1970 by the Ben-Gurion University in Beer-Sheva, first as an Engineering Adviser and Teaching Assistant and since 1979 as a Lecturer. She is a Correspondent of EUROMICRO in Israel. Areas of interest: digital systems, microcomputers, computer architecture, multiprocessing and computer performance evaluation.