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Pseudorandom signal sampler for relaxed design of multistandard radio receiver
ARTICLE IN PRESS Microelectronics Journal 40 (2009) 991–999
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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Pseudorandom signal sampler for relaxed design of multistandard radio receiver Chiheb Rebai a,, Manel Ben-Romdhane a,b, Patricia Desgreys b, Patrick Loumeau b, Adel Ghazel a a b
´rieure des Communications de Tunis (SUP’COM), Cite´ technologique des Communications, 2088 El Ghazala, Ariana, Tunisia CIRTA’COM Research Lab, Ecole Supe LTCI-CNRS UMR 5141, Ecole Nationale Supe´rieure des Te´le´communications de Paris (TELECOM ParisTech), 46, Rue Barrault, 75634 Paris Cedex 13, France
a r t i c l e in fo
abstract
Article history: Received 21 May 2008 Received in revised form 14 January 2009 Accepted 20 January 2009 Available online 18 March 2009
This paper proposes a novel software defined radio (SDR) receiver design using non-uniform sampling (NUS) technique implemented by original design of a pseudorandom signal sampler (PSS) circuit for controlling data conversion to relax multistandard receiver circuit constraints. The proposed and designed NUS-based SDR receiver allows spectral alias suppression at integer multiples of sampling frequency offering the advantages of relaxing anti-aliasing filter (AAF), reducing the analog-to-digital converter (ADC) dynamic power consumption and the automatic gain control (AGC) range as well. The PSS circuit, generating pseudorandom clock signal, with enough time-quantization accuracy, was designed. The PSS is implemented in 65-nm digital CMOS technology and occupies 470 (mm)2. It features up to 200 MHz ‘‘mean clock’’ for 3.2 GHz main clock while drawing 242 mA for 1.2 V supply. Mixed experimental/simulation tests, of designed NUS-based SDR receiver, revealed a confirmation of alias-free performances and the achievement of a 72 dB (12-bit ADC) dynamic range after signal reconstruction. & 2009 Elsevier Ltd. All rights reserved.
Keywords: Software defined radio Non-uniform sampling Multistandard radio receiver Pseudorandom signal sampler
1. Introduction Nowadays, different wireless communication networks are offering multiple services to end-users through a large choice of radio standards: Bluetooth, WiFi, WiMAX, GSM, UMTS, etc. [1,2]. Marketing success of multi-services wireless communications is depending on the feasibility of low-cost and low-power radio user terminals supporting multistandard processing with relaxed constraints on receiver circuits [3]. Software defined radio (SDR) concept is established to reach the objectives of the receiver reconfigurability, the receiver flexibility and the multi-services access, replacing stacked receivers in today used mobile handsets. SDR implementation requires a multistandard RF front-end and a software implementation of baseband processing. Most research activities regarding SDR focus on optimizing RF receiver topologies such as homodyne, low-IF and RF subsampling [4]. SDR receiver architectures are intended to tune from 200 kHz to 20 MHz wide channels that are received from 800 MHz to almost 6 GHz [1]. However, conventional used architectures suffer from introducing high design constraints on anti-aliasing filter
Corresponding author. Tel.: +216 71857 499; fax: +216 71856 829.
E-mail addresses: [email protected] (C. Rebai), [email protected] (M. Ben-Romdhane), [email protected] (P. Desgreys), [email protected] (P. Loumeau), [email protected] (A. Ghazel). 0026-2692/$ - see front matter & 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2009.01.010
(AAF) and analog-to-digital converter (ADC) in case of wideband standards [2]. In addition and due to large dynamic specification for narrow band standards and the ADC technology limits, these architectures need also to use automatic gain control (AGC) in front of the ADC [5]. In this paper, the authors propose a novel SDR receiver design using non-uniform sampling (NUS) technique implemented by original design of a pseudorandom signal sampler (PSS) circuit for controlling ADC to relax constraints of receiver circuits supporting GSM/UMTS/WiFi multistandard processing. This new idea of using NUS technique for radio signals sampling allows the main advantage of suppressing spectral aliases at integer multiples of sampling frequency produced by conventional uniform sampling technique. This reduces, for designed NUS-based SDR receiver, the constraints on the AAF, relaxes the AGC dynamic range, and decreases the ADC dynamic power consumption. Non-uniform sampling theory and techniques are presented in various publications and used for some applications such as duty cycle measurement and spectrum analysis [6–8]. For practical implementation of NUS, some non-uniform signal sampler solutions are proposed in literature [9–16]. In works [9,11–13], non-uniform sampler design is based on chaotic oscillators implemented with discrete components. This design solution is not appropriate for monolithic integrated SDR receiver baseband stage. The second limitation is due to the generation of random continuous-time signal that needs the use of an extra component time-to-digital converter (TDC) for digital signal reconstruction in digital signal processing (DSP).
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The authors in [16] proposed an architecture which generates a time quantized signal sampler convenient for time quantized random sampling (TQ-RS) scheme and reconstruction in DSP. But the use of discrete delay component based on variable inductance lets this architecture not suitable for monolithic integrated SDR receiver baseband stage. Solutions presented in [10,15], that generate a single continuous-time non-uniform signal (mean frequency), are not useful for multistandard that requires a variable non-uniform signal at different mean frequencies according to each standard design specifications. In addition, as solutions in [9,11–13], a TDC is required in front of digital signal reconstruction processing. Finally, non-uniform ring oscillator proposed in [14] seems to be an interesting solution for SDR receiver baseband stage. However, this type of oscillator has an important length of inverters and depends on the chosen technology since inverter W/L CMOS parameter should be reworked to get the same inverter delay. Inverter number selection is done by a pseudorandom number generator (uniform density function). Nevertheless, the sampling periods of successive samples could overlap. This will cause a wrong sampling instant modifying the sampling point density function behavior. Hence, uniform density function is not guaranteed. This analysis of previous work contributions permits to conclude that existing non-uniform sampler generators still present several limitations in terms of circuit integrability, variable sampling frequency, probability density function, accuracy and power consumption. To overcome these limitations, the authors propose in this paper an original circuit design of a pseudorandom signal sampler controlling the ADC to reach relaxed design for NUS-based multistandard radio receiver. Proposed PSS is designed to guarantee a better accuracy, a higher sampling frequency range, a lower power consumption and a smaller area. The paper is organized as follows. In Section 2, NUS processing formulation and system level design of the proposed NUS-based SDR receiver are presented. Section 3 details the proposed PSS circuit design and highlights authors’ contributions by comparison to previous works. In Section 4, PSS circuit digital implementation on 65 nm digital CMOS technology and mixed experimental and simulation results for the proposed NUS-based ADC control are carried out to demonstrate the advantages of the proposed NUS-based architecture and compare its performance to that achieved previously.
2. NUS-based SDR receiver design considerations Among analog down-conversion topologies, the most adapted one for SDR processing is homodyne architecture. To illustrate the proposed design methodology, we have chosen enhanced GSM (925–960 MHz), UMTS (2110–2170 MHz) and IEEE802.11a (UNII12: 5.15–5.35 GHz, UNII3: 5.725–5.825 GHz) standards. Table 1 summarizes GSM/UMTS/WiFi standard specifications. The proposed design is looking forward to sharing RF front-end hardware Table 1 GSM/UMTS/WiFi standard specifications. Parameters
GSM
UMTS
802.11a
Channel width (MHz) Channel spacing (MHz) Required signal-to-noise ratio (dB) Noise figure (dB) Required ADC dynamic range (dB) Required ADC resolution (bits)
0.2 0.2 9 9.8 99 17
3.84 5 6.7 9 88.4 15
16.6 20 26.8 10 61.8 10
as much as possible to reduce receiver cost, size and power consumption. 2.1. NUS processing analytical formulation NUS process converts a continuous analog bandpass signal x(t) into its discrete representation xs(t) as indicated in Eq. (1) with tkotk+1. xs ðtÞ ¼ xðtÞ
þ1 X
dðt tk Þ
(1)
k¼1
The sampling instant sequence {tk} is defined as {tk, kAZ}a{kTs, kAZ} with Ts the mean of the sampling period. This random sequence can be defined by either jittered random sampling (JRS) [6], or additive random sampling (ARS) [7]. To obtain tk in JRS scheme, we add a random time tk to deterministic instants kTs. However, to obtain tk in ARS scheme, we add tk to the previous sampling instant tk1. If irregularities are appropriately chosen, they could provide the aliasing suppression. Alias-free processing is met when the sampling point density function assumes a constant value equal to the mean sampling frequency fs given by Eq. (2). pðtÞ ¼
þ1 X k¼0
pk ðtÞ ¼
1 ¼ fs Ts
(2)
where pk(t) is the probability density function of the random sampling point tk. This stationary condition is accomplished in case of ARS scheme, and in case of JRS scheme only for uniform probability density over ½12T s ; 12T s . Nevertheless, random sampling is not convenient to generate and precisely recover uniform sampling instants [6]. In most non-uniform sampler implementations, the sampling instants are, either randomly or pseudorandomly, analogically generated. Then, these sampling generated instants are digitized before being used in digital recovering process [15]. In [8], Wojtiuk proposed the time quantized random sampling scheme. Each random time, tk, is quantized to tq,k and represented by Eq. (3) according to Eq. (4).
tq;k ¼ nD with D ¼
Ts qT
ðn 1=2ÞDotk pðn þ 1=2ÞD
(3) (4)
where qT is the quantization time factor and n a positive integer number. The TQ-RS in case of JRS scheme for qT ¼ 4 is illustrated in Fig. 1. Wojtiuk proves that qT should be higher than 10 to satisfy stationary condition given by Eq. (2). To analyze these schemes behavior, a statistical parameter s/Ts is defined to evaluate the time set randomness where s2 is the variance of the random time set {tk} or the quantized random time set {tq,k}. For alias-free sampling, we demonstrate that a suitable random scheme over ½12T s ; 12T s is characterized by s/ Ts ¼ 0.288 [17]. Besides, in case of TQ-RS, s/Ts depends on the quantization time factor choice. After presenting NUS technique and particularly TQ-RS scheme, we ought to accommodate NUS to SDR receiver according to GSM/UMTS/WiFi standard specifications. 2.2. System level design of the NUS-based SDR receiver Proposed homodyne topology for NUS-based SDR receiver is illustrated in Fig. 2. This figure shows the use of a common RF front-end for NUS- and US- based receiver. At this stage the signal is first received by a multiband antenna [18], processed by an adequate RF filter selected through an RF switch [19], and fed
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Fig. 1. TQ-RS description for JRS scheme and qT ¼ 4.
Fig. 2. SDR-based radio receiver topology (a) conventional baseband processing and (b) NUS-based baseband processing.
to a multiband LNA [20] then down converted to baseband by (I, Q) mixers. At baseband, the NUS-based processing path (b) is different from US-based one illustrated in path (a). Baseband circuits are digitally controlled to select one of the standards. The anti-aliasing filters are programmable [21] and the ADCs have to quantize signal in several bands and satisfy constraints in terms of sampling frequency and dynamic range. Moreover, frequency synthesizer should be N-fractional to satisfy GSM fine resolution. It must also be multiband and fit the phase noise requirements [22]. The NUS-based baseband processing path (b) need to be completed by a digital implementation of reconstruction algorithm (RA) to recover uniform sampling [23]. We propose to present and discuss system level design methodology and results for NUS-based multistandard receiver baseband processing circuits. Obtained design results will be compared with US-based case in order to evaluate authors’ contribution advantages in terms of relaxed specifications for AAF, ADC and AGC. For this study receiver design is considered for both Nyquist and over-sampling data converters. For AAF filter design, the only previous received signals processing considered is the reduction, by the RF filter, of out-of-band blockers to in-band noise level. We neglect, for AAF design, the effect of other previous stages such as LNA and mixers since their gain and noise are equally added to test signal, interferers, in-band blockers and out-of-band blockers.
So, we consider, at the AAF input, signals being processed by RF filter. RF filter is designed to attenuate out-of-band blockers and bring them to the same level as in-band blockers. Hence, a bandpass filter response is chosen with bandwidth equal to the reception band. The maximum bandpass insertion loss is fixed to 3 dB. Matlab-based CAD by considering defined filter specifications allows the choice of Butterworth bandpass filters that have 5th, 3rd and 3rd orders, respectively, for GSM, UMTS and 802.11a to respect specified RF filter masks. Results of blocker level after RF filter, for the different design cases, are presented in Tables 2 and 3. The AAF order is computed by considering following design methodology:
AAF attenuates signal over channel bandwidth Bc/2. The inband attenuation Amax is equal to 0.3 dB. The rejection frequency is equal to Bc/2 under sampling frequency. The minimum attenuation Amin beyond ft is given by Eq. (5). Amin ¼ Nbl St þ SNRout
(5)
where Nbl is the interferer or blocker level at the required rejection frequency ft, St is the test signal equal to 3 dB over sensibility and SNRout is required signal-to-noise ratio by the received signal given in Table 1.
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Table 2 GSM/UMTS/WiFi receiver design specifications—AAF order for Nyquist rate. GSM
Sampling frequency (MHz) Blocker level after RF filter (dBm) AAF minimum attenuation (dB) Butterworth AAF order Maximum blocker level after AAF (dBm)
UMTS
802.11a
US
NUS
US
NUS
US
NUS
0.2 90 18 432 107.9
0.2 33 75 5 71.4
3.84 66 44.4 24 109.57
3.84 44 51.8 4 73.5
16.6 63 25.8 23 88.78
16.6 30 58.8 3 63.25
Table 3 GSM/UMTS/WiFi receiver design specifications—AAF order for over-sampled rate. GSM
OSR Sampling frequency (MHz) Blocker level after RF filter (dBm) AAF minimum attenuation (dB) Butterworth AAF order Maximum blocker level after AAF (dBm)
UMTS
802.11a
US
US
NUS
US
US
NUS
US
US
NUS
13 2.6 33 75 4 58.24
208 41.6 23 85 2 84.68
13 2.6 23 85 2 58.24
3 11.52 66 29.8 5 63.74
48 184.32 44 51.8 2 84.77
3 11.52 44 51.8 2 63.74
1 16.6 69 19.8 23 63.25
16 265.6 30 58.8 3 88.78
1 16.6 30 58.8 3 63.25
Table 4 GSM/UMTS/WiFi receiver design specifications. GSM
OSR Sampling frequency (MHz) Butterworth AAF order : ordAAF Maximum blocker level after RF filter and AAF with max(ordAAF) order: (NbAtt)max (dBm)
AGC use
Max gain (dB) Min gain (dB)
ADC Dynamic Range (dB) Equivalent bit number
AAF order, under Butterworth approximation, is computed by considering the presented design methodology and input signals being processed by RF filter for blocker levels at the required rejection frequencies.
Design results, given in Table 2, of AAF for US-based receiver using Nyquist converter show that high order AAF, therefore unfeasible, is required for that case. By sampling at a frequency over-sampling ratio (OSR) times higher than Nyquist frequency, to have feasible AAF order (less than 3) for US-based receiver, design results given in Table 3 show that we need high OSR values equal to 208, 48 and 16, respectively for GSM, UMTS and WiFi. This leads to high power consumption of the ADC especially in the case of wideband standards such as IEEE802.11a [24]. In addition, US-based receiver requires an AGC to reduce large dynamic ranges of narrow band standards such as GSM and UMTS requiring a 16-bit ADC. Hence, the use of AGC reduces ADC resolution to 10 bits for uniform sampling as shown in Table 4.
UMTS
802.11a
US
US
NUS
US
US
NUS
US
NUS
208 41.6 2 71.4
208 41.6 2 71.4
13 2.6 2 71.4
48 184.32 2 73.49
48 184.32 2 73.49
3 11.52 2 73.49
16 265.6 3 63.25
1 16.6 3 63.25
No
No
No
No
No
No
69.4 13
39.59 7
96 16
96 16
71.49 23
25.3 4
73.8 12
73.8 12
61.8 10
61.8 10
For the NUS-based receiver design, we look for a trade-off between relaxing AAF selectivity and decreasing the mean sampling frequency fs when operating in over-sampling mode. In fact, thanks to alias-free processing, we notice that TQ-RS allows digitizing analog bandwidth equal to qTfs/2. This increase of the AAF transition band, by the quantization time factor qT, allows the decrease of AAF order as confirmed in design results of Tables 2 and 3. Hence, a feasible AAF order, as shown in results of Table 4, is obtained with lower sampling frequency. Compared to US-based receiver, the OSR of NUS-based receiver is qT times less and is equal to 13, 3 and 1, respectively for GSM, UMTS and WiFi. The second advantage of the implicit over-sampling by qT is to avoid the AGC or to use a relaxed circuit. Indeed, reducing mean sampling frequency reduces ADC dynamic power consumption, and a commercially available ADC is easily found, as presented in Fig. 3, satisfying NUS-based SDR multistandard receiver specifications presented in Table 4. According to this result, required ADC is a 16-bit resolution running at a 16.6 MHz sampling frequency and a 132.8 MHz effective resolution bandwidth (ERBW). These ADC
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Fig. 3. Specifications of commercially available ADCs.
specifications are respected by the component AD9460 from Analog Devices [25]. However, if power consumption reduction is preferred, we propose to use at most a 14-bit ADC to reduce by ten times the power consumption compared to the 16-bit ADC. In that case, a relaxed AGC is required with a maximum of gain 25 dB instead of 69.4 dB for the US-based receiver. As a conclusion, design results of this section show that proposed NUS-based SDR receiver has more relaxed AAF constraints, reduced ADC dynamic power consumption and decreased AGC range compared to US-based receiver.
3. Pseudorandom signal sampler circuit design We propose to complete this work by a circuit design for pseudorandom signal sampler to achieve experimental verification of radio system performances obtained with proposed original design for the NUS-based SDR receiver. The PSS will generate pseudorandom clock signal, with enough timequantization accuracy, to control ADC for NUS operation and to achieve correct digital reconstruction. For an efficient design of the PSS circuit, we target following design specifications:
Accurate generation of sampling instants thanks to the time quantized jittered and additive random sampling.
Integrated PSS circuit independently of the chosen CMOS process technology.
Circuit depending only on external main clock frequency fCLK defining the minimum step D equal to 1/fCLK.
PSS circuit power consumption very low compared with ADC dynamic power consumption.
PSS output mean frequency being at least fs equal to 16.6 MHz with an accuracy of 1/(qTfs) equal to 3.765 ns for IEEE802.11a standard. For GSM and UMTS, the PSS circuit needs to generate a non-uniform signal at mean frequency of, respectively, 3 and 7.68 MHz.
3.1. Survey of non-uniform clock generation circuits Before presenting our solution we start by analyzing signal sampler circuits presented in previous works [9–16]. The non-uniform
ring oscillator based solution, proposed in [14], presents limitations due to introduced phase noise, important length of inverters and its dependency on chosen technology since inverter W/L parameter should be reworked to get the same inverter delay. Only a well chosen inverter delay allows sampling instant generation that respects NUS-based receiver operating requirements. However, the sample periods of successive samples could be overlapped and errors could occur when we non-uniformly sample and hold the analog signal. Design presented in [16] proposes the use of delay block to introduce irregularity on the sampling signal. The non-uniform generator requires a frequency division then adds a time delay to generate the non-uniform signal. The obtained signal is convenient for TQ-RS scheme and reconstruction in DSP. NUS frequency value fits our specifications. However the use, by this generator, of discrete variable inductance-based delay component do not allow a monolithic integrated implementation of the SDR receiver baseband stage. Chaotic oscillators-based non-uniform samplers presented in [9,11–13] use also discrete components and therefore are not appropriate for monolithic integrated SDR receiver baseband stage. Implementation of these oscillators needs to add an extra time-to-digital converter component for digital signal reconstruction in DSP. Integrated chaotic oscillator design is proposed in [10] and delivers 43.7 MHz mean sampling frequency. To meet NUSbased multistandard receiver requirements, the oscillator needs to allow frequency changing of generated non-uniform signal and to amplify at a low noise the output signal. Minimum step D, achieved by this oscillator, do not allow required signal sampler accuracy for TQ-RS scheme. Signal samplers designs in [15] need high accuracy time-todigital converter before digital reconstruction. Signal sampler design built on thermal noise generates random signal with a Gaussian probability density corresponding to JRS scheme which never guarantees the stationary condition given by Eq. (2). We conclude that both designs of [15] are not adapted to TQ-RS scheme and the signal reconstruction depends on the TDC accuracy. Neither simulation results nor implementation have been presented in that work. By considering discussed drawbacks of previous works regarding non-uniform signal generators, we will propose a novel circuit respecting design specifications presented in the beginning of this section.
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Fig. 4. Required phases for TQ-RS scheme for qT ¼ 8.
The Gray counter is controlled by an external uniform main clock fCLK and based on N ¼ log2(qT) D-latches. The signals {G0, G1, y, GN1} delivered by this counter are combined to generate the qT sampling phases with different duty cycles. Gray counter enumeration reduces the number of jumps between delivered signals {Gi}, then glitches are reduced in all subsequent combinational logic. However, the linear feedback shift register (LFSR) generates a binary pseudorandom sequence {L0, L1, y, LN1}. When controlled by qT times slower clock, the LFSR presents N length minimal characteristic polynomial given by Eq. (6). pðxÞ ¼ xN þ xm þ 1
(6)
where m should be absolutely chosen between 0 and N [26]. The generated pseudorandom numbers perform a uniform probability density function in case of JRS scheme, and are taken in the set of {0, 1, y, qT1}. Therefore, statistical parameter s/Ts is given in Eq. (7). sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi s 1 ðqT 1Þ2 1 ¼ (7) T s qT 12
Fig. 5. PSS circuit digital design architecture (N ¼ log2(qT)).
3.2. Pseudorandom signal sampler defined circuit To sample non-uniformly, we define several sampling phases instead of conventional uniform sampling. The solutions based on phases, noted {F0, F1, y, FqT1} and presented in Fig. 4, suffer from overlapping phases. This creates the loss of information due to the time shift between ADC present outputs and receiving the next phase. The delay between the two successive clock phases is the minimum spacing D defined in Eq. (3), and the phases duty cycles are equal. The question is how to generate these phases without overlapping between {F0, F1, y, F(qT/2)1} and {F(qT/2), y, FqT1}. We propose a new design, called PSS to overcome the overlap problem. Fig. 5 illustrates the block diagram of the PSS. For the phase design process, we precisely produce phase segmentation thanks to Gray counter. Combining function is defined to take care of falling down current phase before next phase rising edge.
For qT ¼ 16, we achieve a pseudorandom sequence characterized by s/Ts ¼ 0.27 which is the nearest value to the theoretical one (0.288), given in Section 2, for a small number of latches. The last stage is the multiplexer MUX qT:1 which acts as a selective combiner. It selects the phase Fi addressed by the generated pseudorandom number i each period of fdiv. The main clock fCLK has a period equal to the minimum spacing D needed for the TQ-RS scheme. In NUS-based SDR receiver, the main clock could be taken from a multiband phase-locked loop (PLL). The mean sampling frequency is fs ¼ fdiv ¼ fCLK/qT where fCLK is the main clock frequency delivered by the PLL. Two modifications have been done to improve the accuracy. First, instead of generating a qT divided clock, we control the LFSR by the first generated phase F0. This modification is necessary to obtain synchronization between the multiplexer inputs and addresses. Second, the multiplexer introduces some delay between phases selection. Therefore, the pseudorandom clock PSSout presents glitches which are shorter than the specified minimum spacing D. If they are not suppressed, ADC will wrongly sample the input signal. For that reason, the multiplexer output was fed through a D-latch controlled by the main clock fCLK to deliver pseudorandom clock PSSout. Resulting modified PSS architecture is presented in Fig. 6.
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Table 5 Instantaneous sampling periods, sampling frequencies and duty cycles for qT ¼ 16.
Fig. 6. PSS circuit modified digital design architecture (N ¼ log2(qT)).
Instantaneous sampling frequency fi takes values between minimum and maximum frequencies defined in Eq. (8). f CLK pf i pf CLK ð2qT 1Þ
(8)
For LFSR polynomial given by Eq. (6), the obtained frequencies are different from those given by Eq. (8). Indeed, pseudorandom numbers in case of qT equal to 16 are presented in Table 5. For each LFSR generated number i, we compute the instantaneous duty cycle DCi and the mean sampling period Ti, which is the D step occurrences between two successive positive edges, given by Eq. (9). T i ¼ ½qT iðkÞ þ iðk þ 1ÞD;
1pkpqT 1
(9)
where Ti is equal to 1/fi, fi is the instantaneous sampling frequency. We can then extract the minimum and maximum sampling frequencies as given in Table 5. ADC must be able to convert at mean sampling frequency fs and computed maximum sampling frequency must be two times lower than the effective resolution bandwidth. Reducing sampling at mean sampling frequency fs instead of uniform sampling at qTfs decreases ADC dynamic power consumption near qT times [27].
LFSR output i
DCi (%)
Ti
fi
1 2 4 9 3 6 13 10 5 11 7 15 14 12 8 Mean sampling frequency
50.00 50.00 50.00 43.75 50.00 50.00 18.75 37.50 50.00 31.25 50.00 6.25 12.50 25.00 50.00
17D 18D 21D 10D 19D 23D 13D 11D 22D 12D 24D 15D 14D 12D 9D
fCLK/17 fCLK/18 fCLK/21 fCLK/10 fCLK/19 fCLK/23 fCLK/13 fCLK/11 fCLK/22 fCLK/12 fsmin ¼ fCLK/24 fCLK/15 fCLK/14 fCLK/12 fsmax ¼ fCLK/9 fCLK/16
fs
obtained when using a main clock frequency between 16 MHz and 3.2 GHz. Despite inconvenience of existing non-uniform sampler architectures for NUS-based SDR receiver, PSS offers a large sampling frequency range, a smaller die area and a less power consumption as recapitulated in Table 6. The obtained pseudorandom signal sampler power consumption is lower than the values mentioned in [10,16] for the same generated mean sampling frequencies. For example, for fs ¼ 53.546 MHz, the design in [16] consumes 8.25 W and our design consumes 77.64 mW. For fs ¼ 43.7 MHz, the design in [10] consumes 2.7 mW and our design consumes 63.36 mW. PSS adapted to NUS-based SDR receiver specifications consumes only 4.35 mW at 3 MHz, 11.13 mW at 7.68 MHz and 24 mW at 16.6 MHz. The designed PSS delivers up to 200 MHz and this could furthermore relax constraints on the baseband for future standards and services specifications. If we include AGC only for GSM received signals, the NUSbased SDR receiver presented in Section 2 needs a 12-bit ADC at fs ¼ 16.6 MHz. The alias-free phenomenon, for designed NUSbased SDR receiver, was tested in a mixed experimental/simulation environment. This mixed test environment is set up as follows: a Matlab/Simulink reference model is defined for the sample-and-hold (S/H) circuit followed by a quantization bloc. A sine wave is applied at the input of S/H circuit. Non-uniform sampling achieved by the S/H circuit model is controlled by a physical signal delivered by the pseudorandom signal sampler hardware circuit. Quantized S/H output was processed with the cubic spline reconstruction algorithm. Obtained spectrum after reconstruction shows a dynamic range 72 dB which is near to 12bit ADC dynamic range. Fig. 8 shows quantized S/H output spectrum after reconstruction algorithm compared to spectrum in conventional uniform sampling processing.
4. PSS circuit implementation and evaluation results Functional verification of the proposed PSS architecture is synthesized in VHDL to generate fs ¼ 16.6 MHz. For qT ¼ 8 and 16, the statistical parameter s/Ts is, respectively, 0.254 and 0.275. The phases and pseudorandom numbers used to generate the pseudorandom clock PSSout are given in Fig. 7. To validate the proposed idea for circuit design, the PSS architecture described in the previous section, was implemented in CADENCE for a 65 nm digital CMOS technology. The signal generation as described above has been verified through electrical post-layout simulation. PSS occupies a 470 (mm)2. It allows up to mean sampling frequency fs equal to 200 MHz. PSS circuit consumes between 1.21 and 242 mA from 1.2 V supply for obtained frequency test between 1 and 200 MHz. These frequencies are
5. Conclusion In this paper, a new NUS-based SDR receiver implemented by an original design of a PSS circuit has been proposed to enhance multistandard radio signals digitalization while maintaining relaxed design constraints for receiver circuit baseband stages such as AAF, ADC and AGC. NUS-based receiver design was tuned for the best trade-off between relaxing AAF selectivity and decreasing the mean sampling frequency when operating in implicit over-sampling mode to reduce ADC dynamic power consumption. To compensate limitations of existing non-uniform oscillators in [10,16], PSS circuit design is based on an accurate generation of sampling instants in the time quantized jittered and
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Fig. 7. PSS generated phases measurement for qT ¼ 8, phase[i] represents Fi for 0pip(qT1) and lfsr_out[j] represents Lj for 0pjp(log2(qT)1).
Table 6 Performances comparison of existing sampler designs with proposed PSS. Ref.
fs (MHz)
Area
Power consumption
Technology
[16] [13] [14] [10] Proposed PSS in this paper
53.546 N.C. N.C. 43.7 1–200
185 mm 162 mm 3264 (mm)2 3350 (mm)2 N.C. 470 (mm)2
8.25 W N.C. N.C. 2.7 mW 1.45 mW at 1 MHz to 290.4 mW at 200 MHz 24 mW at 16.6 MHz
Printed circuit board Target 130 nm IBM Cu-11 Target 130 nm IBM Cu-11 Spice AMS SiGe 0.35 mm BiCMOS Target 65 nm digital CMOS
0 y__US y__PSS
Normalized Power Spectrum Density (dBm)
-20 -40 -60 -80 -100 -120 -140 -160 -180
0
1
2
3
4 5 Frequency (MHz)
6
7
8
9
Fig. 8. PSS controlled S/H output spectrum after cubic spline reconstruction (y_PSS) versus uniform sampling S/H output spectrum (y_US).
additive random sampling, an integrated PSS circuit independently of the chosen CMOS process technology and a circuit depending only on external main clock frequency fCLK defining the
minimum step D equal to 1/fCLK. The 65 nm digital CMOS technology implementation of designed PSS leads to a circuit occupation area of 470 (mm)2.
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The proposed NUS receiver architecture and PSS circuit performances were validated for GSM/UMTS/WiFi multistandard radio processing. The PSS circuit consumes between 1.21 and 242 mA from 1.2 V supply for frequency test between 1 and 200 MHz. Proposed NUS design allows a 72 dB (12-bit) ADC dynamic range and leads to a 45 dB reduction in required AGC maximum of gain compared with conventional uniform design.
Acknowledgement This work was supported financially by the CMCU organization (Comite´ Mixte de Coope´ration Universitaire) under Project code 06/G1125. References [1] A.A. Abidi, The path of the Software Defined Radio receiver, IEEE Journal of Solid-State Circuits 42 (5) (2007) 954–966. [2] M. Brandolini, P. Rossi, D. Manstretta, F. Svelto, Toward multistandard mobile terminals—fully integrated receivers requirements and architectures, IEEE Transaction on Microwave Theory and Techniques 53 (3) (2005) 1026–1038. [3] J.A. Kilpatrick, R.J. Cyr, E.L. Org, G. Dawe, New SDR architecture enables ubiquitous data connectivity, RF and Microwave Technology for Design Engineers (2006) 32–38. [4] R. Darraji, R. Barrak, C. Rebai, A. Ghazel, Y. Deval, F. Ghannouchi, Track and hold circuit design and implementation in 65 nm CMOS technology for RF subsampling receivers, in: IEEE International Conference on Electronics, Circuits and Systems, September 2008, pp. 1249–1252. [5] E. Buracchini, The software radio concept, IEEE Communications Magazine 38 (8) (2000) 138–143. [6] I. Bilinskis, A. Mikelsons, Randomized Signal Processing, Cambridge, Prentice Hall, 1992. [7] H.S. Shapiro, R.A. Silverman, Alias-free sampling of random noise, Journal Society for Industrial and Applied Mathematics 8 (2) (1960) 225–248. [8] J.J. Wojtiuk, Randomized Sampling for Radio Design, Ph.D. Thesis, University of South Australia, School of Electrical and Information Engineering, 2000. [9] A.J. Johansson, H. Floberg, Random number generation by chaotic double scroll oscillator on chip, IEEE International Symposium on Circuits and Systems 5 (1999) 407–409. [10] S. Ozoguz, S. Ergu¨n, A non-autonomous IC chaotic oscillator and its application for random bit generation, in: European Conference on Circuit Theory and Design, vol. 2, August–September 2005, pp. II/165–II/168.
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[11] A. Namajunas, A. Tamasevicius, Simple RC chaotic oscillator, Electronic Letters 32 (11) (1996) 945–946. [12] F. Han, X. Yu, Y. Wang, Y. Feng, G. Chen, N-scroll chaotic oscillators by secondorder systems and double-hysteresis blocks, Electronic Letters 39 (23) (2003) 1636–1638. [13] R.Z. Bhatti, M. Denneau, J. Draper, Duty cycle measurement and correction using a random sampling technique, in: 48th Midwest Symposium on Circuits and Systems, vol. 2, August 2005, pp. 1043–1046. [14] R.Z. Bhatti, M. Denneau, J. Draper, Phase measurement and adjustment of digital signals using random sampling technique, IEEE International Symposium on Circuits and Systems (2006) 3886–3889. [15] N. Michael, S. Shah, J. Das, M.M. Sandeep, C. Vijaykumar, Non uniform digitizer for alias-free sampling of wideband analog signals, in: IEEE Region 10 Conference, TENCON 2007, October–November 2007, pp. 1–4. [16] Y. Artyukh, I. Bilinskis, E. Boole, A. Rybakov, V. Vedin, Wideband RF signal digitizing for high purity spectral analysis, in: The 2005 International Workshop on Spectral Methods and Multirate Signal Processing, June 2005. [17] M. Ben-Romdhane, C. Rebai, A. Ghazel, P. Desgreys, P. Loumeau, Non-uniform sampling schemes for IF sampling radio receiver, in: IEEE International Conference on Design and Test of Integrated Systems in Nanoscale Technology, September 2006, pp. 15–20. [18] J. Costantine, K. Kabalan, A. El-Hajj, M. Rammal, New multi-band microstrip antenna design for wireless communications, IEEE Antenna and Propagation Magazine 49 (6) (2007) 181–186. [19] S. Yoshimoto, Y. Yamamoto, Y. Takahashi, E. Otsuka, Multi-band RF SAW filter for mobile phone using surface mount plastic package, IEEE Ultrasonics Symposium 1 (2002) 113–118. [20] V.K. Dao, Q.D. Bui, C.S. Park, A multi-band 900 MHz/1.8 GHz/5.2 GHz LNA for reconfigurable radio, IEEE Radio Frequency Integrated Circuits Symposium (2007) 69–72. [21] C. Rus, L. Festila, G. Csipkes, S. Hintea, D. Csipkes, A reconfigurable and programmable filter for Software Defined Radio based on a transconductorcapacitor analog array, in: IEEE Second International Design and Test Workshop, December 2007, pp. 27–32. [22] A. Koukab, Y. Lei, M.J. Declercq, A GSM-GPRS/UMTS FDD-TDD/WLAN 802.11a-b-g multi-standard carrier generation system, IEEE Journal of Solid-State Circuits 41 (7) (2006) 1513–1521. [23] M. Ben-Romdhane, C. Rebai, K. Grati, A. Ghazel, G. Hechmi, P. Desgreys, P. Loumeau, Non-uniform sampled signal reconstruction for multistandard WiMAX/Wi-Fi receiver, in: IEEE International Conference on Signal Processing and Communication, November 2007, pp. 181–184 [24] Analog Devices Data Sheet Number AD9626, 12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter, Analog Devices, Inc., November 2007. [25] Analog Devices Data Sheet Number AD9460, 16-Bit, 80 MSPS/105 MSPS, Analog-to-Digital Converter, Analog Devices, Inc., August 2006. [26] E. Boutillon, J.-L. Danger, A. Ghazel, Design of high speed AWGN communication channel emulator, Analog Integrated Circuits and Signal Processing 34 (2) (2003) 133–142 Kluwer Academic Publishers. [27] P.B. Kenington, L. Astier, Power consumption of A/D converters for software radio applications, IEEE Transactions on Vehicular Technology 49 (2) (2000).
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Pseudorandom signal sampler for relaxed design of multistandard radio receiver Chiheb Rebai a,, Manel Ben-Romdhane a,b, Patricia Desgreys b, Patrick Loumeau b, Adel Ghazel a a b
´rieure des Communications de Tunis (SUP’COM), Cite´ technologique des Communications, 2088 El Ghazala, Ariana, Tunisia CIRTA’COM Research Lab, Ecole Supe LTCI-CNRS UMR 5141, Ecole Nationale Supe´rieure des Te´le´communications de Paris (TELECOM ParisTech), 46, Rue Barrault, 75634 Paris Cedex 13, France
a r t i c l e in fo
abstract
Article history: Received 21 May 2008 Received in revised form 14 January 2009 Accepted 20 January 2009 Available online 18 March 2009
This paper proposes a novel software defined radio (SDR) receiver design using non-uniform sampling (NUS) technique implemented by original design of a pseudorandom signal sampler (PSS) circuit for controlling data conversion to relax multistandard receiver circuit constraints. The proposed and designed NUS-based SDR receiver allows spectral alias suppression at integer multiples of sampling frequency offering the advantages of relaxing anti-aliasing filter (AAF), reducing the analog-to-digital converter (ADC) dynamic power consumption and the automatic gain control (AGC) range as well. The PSS circuit, generating pseudorandom clock signal, with enough time-quantization accuracy, was designed. The PSS is implemented in 65-nm digital CMOS technology and occupies 470 (mm)2. It features up to 200 MHz ‘‘mean clock’’ for 3.2 GHz main clock while drawing 242 mA for 1.2 V supply. Mixed experimental/simulation tests, of designed NUS-based SDR receiver, revealed a confirmation of alias-free performances and the achievement of a 72 dB (12-bit ADC) dynamic range after signal reconstruction. & 2009 Elsevier Ltd. All rights reserved.
Keywords: Software defined radio Non-uniform sampling Multistandard radio receiver Pseudorandom signal sampler
1. Introduction Nowadays, different wireless communication networks are offering multiple services to end-users through a large choice of radio standards: Bluetooth, WiFi, WiMAX, GSM, UMTS, etc. [1,2]. Marketing success of multi-services wireless communications is depending on the feasibility of low-cost and low-power radio user terminals supporting multistandard processing with relaxed constraints on receiver circuits [3]. Software defined radio (SDR) concept is established to reach the objectives of the receiver reconfigurability, the receiver flexibility and the multi-services access, replacing stacked receivers in today used mobile handsets. SDR implementation requires a multistandard RF front-end and a software implementation of baseband processing. Most research activities regarding SDR focus on optimizing RF receiver topologies such as homodyne, low-IF and RF subsampling [4]. SDR receiver architectures are intended to tune from 200 kHz to 20 MHz wide channels that are received from 800 MHz to almost 6 GHz [1]. However, conventional used architectures suffer from introducing high design constraints on anti-aliasing filter
Corresponding author. Tel.: +216 71857 499; fax: +216 71856 829.
E-mail addresses: [email protected] (C. Rebai), [email protected] (M. Ben-Romdhane), [email protected] (P. Desgreys), [email protected] (P. Loumeau), [email protected] (A. Ghazel). 0026-2692/$ - see front matter & 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2009.01.010
(AAF) and analog-to-digital converter (ADC) in case of wideband standards [2]. In addition and due to large dynamic specification for narrow band standards and the ADC technology limits, these architectures need also to use automatic gain control (AGC) in front of the ADC [5]. In this paper, the authors propose a novel SDR receiver design using non-uniform sampling (NUS) technique implemented by original design of a pseudorandom signal sampler (PSS) circuit for controlling ADC to relax constraints of receiver circuits supporting GSM/UMTS/WiFi multistandard processing. This new idea of using NUS technique for radio signals sampling allows the main advantage of suppressing spectral aliases at integer multiples of sampling frequency produced by conventional uniform sampling technique. This reduces, for designed NUS-based SDR receiver, the constraints on the AAF, relaxes the AGC dynamic range, and decreases the ADC dynamic power consumption. Non-uniform sampling theory and techniques are presented in various publications and used for some applications such as duty cycle measurement and spectrum analysis [6–8]. For practical implementation of NUS, some non-uniform signal sampler solutions are proposed in literature [9–16]. In works [9,11–13], non-uniform sampler design is based on chaotic oscillators implemented with discrete components. This design solution is not appropriate for monolithic integrated SDR receiver baseband stage. The second limitation is due to the generation of random continuous-time signal that needs the use of an extra component time-to-digital converter (TDC) for digital signal reconstruction in digital signal processing (DSP).
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The authors in [16] proposed an architecture which generates a time quantized signal sampler convenient for time quantized random sampling (TQ-RS) scheme and reconstruction in DSP. But the use of discrete delay component based on variable inductance lets this architecture not suitable for monolithic integrated SDR receiver baseband stage. Solutions presented in [10,15], that generate a single continuous-time non-uniform signal (mean frequency), are not useful for multistandard that requires a variable non-uniform signal at different mean frequencies according to each standard design specifications. In addition, as solutions in [9,11–13], a TDC is required in front of digital signal reconstruction processing. Finally, non-uniform ring oscillator proposed in [14] seems to be an interesting solution for SDR receiver baseband stage. However, this type of oscillator has an important length of inverters and depends on the chosen technology since inverter W/L CMOS parameter should be reworked to get the same inverter delay. Inverter number selection is done by a pseudorandom number generator (uniform density function). Nevertheless, the sampling periods of successive samples could overlap. This will cause a wrong sampling instant modifying the sampling point density function behavior. Hence, uniform density function is not guaranteed. This analysis of previous work contributions permits to conclude that existing non-uniform sampler generators still present several limitations in terms of circuit integrability, variable sampling frequency, probability density function, accuracy and power consumption. To overcome these limitations, the authors propose in this paper an original circuit design of a pseudorandom signal sampler controlling the ADC to reach relaxed design for NUS-based multistandard radio receiver. Proposed PSS is designed to guarantee a better accuracy, a higher sampling frequency range, a lower power consumption and a smaller area. The paper is organized as follows. In Section 2, NUS processing formulation and system level design of the proposed NUS-based SDR receiver are presented. Section 3 details the proposed PSS circuit design and highlights authors’ contributions by comparison to previous works. In Section 4, PSS circuit digital implementation on 65 nm digital CMOS technology and mixed experimental and simulation results for the proposed NUS-based ADC control are carried out to demonstrate the advantages of the proposed NUS-based architecture and compare its performance to that achieved previously.
2. NUS-based SDR receiver design considerations Among analog down-conversion topologies, the most adapted one for SDR processing is homodyne architecture. To illustrate the proposed design methodology, we have chosen enhanced GSM (925–960 MHz), UMTS (2110–2170 MHz) and IEEE802.11a (UNII12: 5.15–5.35 GHz, UNII3: 5.725–5.825 GHz) standards. Table 1 summarizes GSM/UMTS/WiFi standard specifications. The proposed design is looking forward to sharing RF front-end hardware Table 1 GSM/UMTS/WiFi standard specifications. Parameters
GSM
UMTS
802.11a
Channel width (MHz) Channel spacing (MHz) Required signal-to-noise ratio (dB) Noise figure (dB) Required ADC dynamic range (dB) Required ADC resolution (bits)
0.2 0.2 9 9.8 99 17
3.84 5 6.7 9 88.4 15
16.6 20 26.8 10 61.8 10
as much as possible to reduce receiver cost, size and power consumption. 2.1. NUS processing analytical formulation NUS process converts a continuous analog bandpass signal x(t) into its discrete representation xs(t) as indicated in Eq. (1) with tkotk+1. xs ðtÞ ¼ xðtÞ
þ1 X
dðt tk Þ
(1)
k¼1
The sampling instant sequence {tk} is defined as {tk, kAZ}a{kTs, kAZ} with Ts the mean of the sampling period. This random sequence can be defined by either jittered random sampling (JRS) [6], or additive random sampling (ARS) [7]. To obtain tk in JRS scheme, we add a random time tk to deterministic instants kTs. However, to obtain tk in ARS scheme, we add tk to the previous sampling instant tk1. If irregularities are appropriately chosen, they could provide the aliasing suppression. Alias-free processing is met when the sampling point density function assumes a constant value equal to the mean sampling frequency fs given by Eq. (2). pðtÞ ¼
þ1 X k¼0
pk ðtÞ ¼
1 ¼ fs Ts
(2)
where pk(t) is the probability density function of the random sampling point tk. This stationary condition is accomplished in case of ARS scheme, and in case of JRS scheme only for uniform probability density over ½12T s ; 12T s . Nevertheless, random sampling is not convenient to generate and precisely recover uniform sampling instants [6]. In most non-uniform sampler implementations, the sampling instants are, either randomly or pseudorandomly, analogically generated. Then, these sampling generated instants are digitized before being used in digital recovering process [15]. In [8], Wojtiuk proposed the time quantized random sampling scheme. Each random time, tk, is quantized to tq,k and represented by Eq. (3) according to Eq. (4).
tq;k ¼ nD with D ¼
Ts qT
ðn 1=2ÞDotk pðn þ 1=2ÞD
(3) (4)
where qT is the quantization time factor and n a positive integer number. The TQ-RS in case of JRS scheme for qT ¼ 4 is illustrated in Fig. 1. Wojtiuk proves that qT should be higher than 10 to satisfy stationary condition given by Eq. (2). To analyze these schemes behavior, a statistical parameter s/Ts is defined to evaluate the time set randomness where s2 is the variance of the random time set {tk} or the quantized random time set {tq,k}. For alias-free sampling, we demonstrate that a suitable random scheme over ½12T s ; 12T s is characterized by s/ Ts ¼ 0.288 [17]. Besides, in case of TQ-RS, s/Ts depends on the quantization time factor choice. After presenting NUS technique and particularly TQ-RS scheme, we ought to accommodate NUS to SDR receiver according to GSM/UMTS/WiFi standard specifications. 2.2. System level design of the NUS-based SDR receiver Proposed homodyne topology for NUS-based SDR receiver is illustrated in Fig. 2. This figure shows the use of a common RF front-end for NUS- and US- based receiver. At this stage the signal is first received by a multiband antenna [18], processed by an adequate RF filter selected through an RF switch [19], and fed
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Fig. 1. TQ-RS description for JRS scheme and qT ¼ 4.
Fig. 2. SDR-based radio receiver topology (a) conventional baseband processing and (b) NUS-based baseband processing.
to a multiband LNA [20] then down converted to baseband by (I, Q) mixers. At baseband, the NUS-based processing path (b) is different from US-based one illustrated in path (a). Baseband circuits are digitally controlled to select one of the standards. The anti-aliasing filters are programmable [21] and the ADCs have to quantize signal in several bands and satisfy constraints in terms of sampling frequency and dynamic range. Moreover, frequency synthesizer should be N-fractional to satisfy GSM fine resolution. It must also be multiband and fit the phase noise requirements [22]. The NUS-based baseband processing path (b) need to be completed by a digital implementation of reconstruction algorithm (RA) to recover uniform sampling [23]. We propose to present and discuss system level design methodology and results for NUS-based multistandard receiver baseband processing circuits. Obtained design results will be compared with US-based case in order to evaluate authors’ contribution advantages in terms of relaxed specifications for AAF, ADC and AGC. For this study receiver design is considered for both Nyquist and over-sampling data converters. For AAF filter design, the only previous received signals processing considered is the reduction, by the RF filter, of out-of-band blockers to in-band noise level. We neglect, for AAF design, the effect of other previous stages such as LNA and mixers since their gain and noise are equally added to test signal, interferers, in-band blockers and out-of-band blockers.
So, we consider, at the AAF input, signals being processed by RF filter. RF filter is designed to attenuate out-of-band blockers and bring them to the same level as in-band blockers. Hence, a bandpass filter response is chosen with bandwidth equal to the reception band. The maximum bandpass insertion loss is fixed to 3 dB. Matlab-based CAD by considering defined filter specifications allows the choice of Butterworth bandpass filters that have 5th, 3rd and 3rd orders, respectively, for GSM, UMTS and 802.11a to respect specified RF filter masks. Results of blocker level after RF filter, for the different design cases, are presented in Tables 2 and 3. The AAF order is computed by considering following design methodology:
AAF attenuates signal over channel bandwidth Bc/2. The inband attenuation Amax is equal to 0.3 dB. The rejection frequency is equal to Bc/2 under sampling frequency. The minimum attenuation Amin beyond ft is given by Eq. (5). Amin ¼ Nbl St þ SNRout
(5)
where Nbl is the interferer or blocker level at the required rejection frequency ft, St is the test signal equal to 3 dB over sensibility and SNRout is required signal-to-noise ratio by the received signal given in Table 1.
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Table 2 GSM/UMTS/WiFi receiver design specifications—AAF order for Nyquist rate. GSM
Sampling frequency (MHz) Blocker level after RF filter (dBm) AAF minimum attenuation (dB) Butterworth AAF order Maximum blocker level after AAF (dBm)
UMTS
802.11a
US
NUS
US
NUS
US
NUS
0.2 90 18 432 107.9
0.2 33 75 5 71.4
3.84 66 44.4 24 109.57
3.84 44 51.8 4 73.5
16.6 63 25.8 23 88.78
16.6 30 58.8 3 63.25
Table 3 GSM/UMTS/WiFi receiver design specifications—AAF order for over-sampled rate. GSM
OSR Sampling frequency (MHz) Blocker level after RF filter (dBm) AAF minimum attenuation (dB) Butterworth AAF order Maximum blocker level after AAF (dBm)
UMTS
802.11a
US
US
NUS
US
US
NUS
US
US
NUS
13 2.6 33 75 4 58.24
208 41.6 23 85 2 84.68
13 2.6 23 85 2 58.24
3 11.52 66 29.8 5 63.74
48 184.32 44 51.8 2 84.77
3 11.52 44 51.8 2 63.74
1 16.6 69 19.8 23 63.25
16 265.6 30 58.8 3 88.78
1 16.6 30 58.8 3 63.25
Table 4 GSM/UMTS/WiFi receiver design specifications. GSM
OSR Sampling frequency (MHz) Butterworth AAF order : ordAAF Maximum blocker level after RF filter and AAF with max(ordAAF) order: (NbAtt)max (dBm)
AGC use
Max gain (dB) Min gain (dB)
ADC Dynamic Range (dB) Equivalent bit number
AAF order, under Butterworth approximation, is computed by considering the presented design methodology and input signals being processed by RF filter for blocker levels at the required rejection frequencies.
Design results, given in Table 2, of AAF for US-based receiver using Nyquist converter show that high order AAF, therefore unfeasible, is required for that case. By sampling at a frequency over-sampling ratio (OSR) times higher than Nyquist frequency, to have feasible AAF order (less than 3) for US-based receiver, design results given in Table 3 show that we need high OSR values equal to 208, 48 and 16, respectively for GSM, UMTS and WiFi. This leads to high power consumption of the ADC especially in the case of wideband standards such as IEEE802.11a [24]. In addition, US-based receiver requires an AGC to reduce large dynamic ranges of narrow band standards such as GSM and UMTS requiring a 16-bit ADC. Hence, the use of AGC reduces ADC resolution to 10 bits for uniform sampling as shown in Table 4.
UMTS
802.11a
US
US
NUS
US
US
NUS
US
NUS
208 41.6 2 71.4
208 41.6 2 71.4
13 2.6 2 71.4
48 184.32 2 73.49
48 184.32 2 73.49
3 11.52 2 73.49
16 265.6 3 63.25
1 16.6 3 63.25
No
No
No
No
No
No
69.4 13
39.59 7
96 16
96 16
71.49 23
25.3 4
73.8 12
73.8 12
61.8 10
61.8 10
For the NUS-based receiver design, we look for a trade-off between relaxing AAF selectivity and decreasing the mean sampling frequency fs when operating in over-sampling mode. In fact, thanks to alias-free processing, we notice that TQ-RS allows digitizing analog bandwidth equal to qTfs/2. This increase of the AAF transition band, by the quantization time factor qT, allows the decrease of AAF order as confirmed in design results of Tables 2 and 3. Hence, a feasible AAF order, as shown in results of Table 4, is obtained with lower sampling frequency. Compared to US-based receiver, the OSR of NUS-based receiver is qT times less and is equal to 13, 3 and 1, respectively for GSM, UMTS and WiFi. The second advantage of the implicit over-sampling by qT is to avoid the AGC or to use a relaxed circuit. Indeed, reducing mean sampling frequency reduces ADC dynamic power consumption, and a commercially available ADC is easily found, as presented in Fig. 3, satisfying NUS-based SDR multistandard receiver specifications presented in Table 4. According to this result, required ADC is a 16-bit resolution running at a 16.6 MHz sampling frequency and a 132.8 MHz effective resolution bandwidth (ERBW). These ADC
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Fig. 3. Specifications of commercially available ADCs.
specifications are respected by the component AD9460 from Analog Devices [25]. However, if power consumption reduction is preferred, we propose to use at most a 14-bit ADC to reduce by ten times the power consumption compared to the 16-bit ADC. In that case, a relaxed AGC is required with a maximum of gain 25 dB instead of 69.4 dB for the US-based receiver. As a conclusion, design results of this section show that proposed NUS-based SDR receiver has more relaxed AAF constraints, reduced ADC dynamic power consumption and decreased AGC range compared to US-based receiver.
3. Pseudorandom signal sampler circuit design We propose to complete this work by a circuit design for pseudorandom signal sampler to achieve experimental verification of radio system performances obtained with proposed original design for the NUS-based SDR receiver. The PSS will generate pseudorandom clock signal, with enough timequantization accuracy, to control ADC for NUS operation and to achieve correct digital reconstruction. For an efficient design of the PSS circuit, we target following design specifications:
Accurate generation of sampling instants thanks to the time quantized jittered and additive random sampling.
Integrated PSS circuit independently of the chosen CMOS process technology.
Circuit depending only on external main clock frequency fCLK defining the minimum step D equal to 1/fCLK.
PSS circuit power consumption very low compared with ADC dynamic power consumption.
PSS output mean frequency being at least fs equal to 16.6 MHz with an accuracy of 1/(qTfs) equal to 3.765 ns for IEEE802.11a standard. For GSM and UMTS, the PSS circuit needs to generate a non-uniform signal at mean frequency of, respectively, 3 and 7.68 MHz.
3.1. Survey of non-uniform clock generation circuits Before presenting our solution we start by analyzing signal sampler circuits presented in previous works [9–16]. The non-uniform
ring oscillator based solution, proposed in [14], presents limitations due to introduced phase noise, important length of inverters and its dependency on chosen technology since inverter W/L parameter should be reworked to get the same inverter delay. Only a well chosen inverter delay allows sampling instant generation that respects NUS-based receiver operating requirements. However, the sample periods of successive samples could be overlapped and errors could occur when we non-uniformly sample and hold the analog signal. Design presented in [16] proposes the use of delay block to introduce irregularity on the sampling signal. The non-uniform generator requires a frequency division then adds a time delay to generate the non-uniform signal. The obtained signal is convenient for TQ-RS scheme and reconstruction in DSP. NUS frequency value fits our specifications. However the use, by this generator, of discrete variable inductance-based delay component do not allow a monolithic integrated implementation of the SDR receiver baseband stage. Chaotic oscillators-based non-uniform samplers presented in [9,11–13] use also discrete components and therefore are not appropriate for monolithic integrated SDR receiver baseband stage. Implementation of these oscillators needs to add an extra time-to-digital converter component for digital signal reconstruction in DSP. Integrated chaotic oscillator design is proposed in [10] and delivers 43.7 MHz mean sampling frequency. To meet NUSbased multistandard receiver requirements, the oscillator needs to allow frequency changing of generated non-uniform signal and to amplify at a low noise the output signal. Minimum step D, achieved by this oscillator, do not allow required signal sampler accuracy for TQ-RS scheme. Signal samplers designs in [15] need high accuracy time-todigital converter before digital reconstruction. Signal sampler design built on thermal noise generates random signal with a Gaussian probability density corresponding to JRS scheme which never guarantees the stationary condition given by Eq. (2). We conclude that both designs of [15] are not adapted to TQ-RS scheme and the signal reconstruction depends on the TDC accuracy. Neither simulation results nor implementation have been presented in that work. By considering discussed drawbacks of previous works regarding non-uniform signal generators, we will propose a novel circuit respecting design specifications presented in the beginning of this section.
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Fig. 4. Required phases for TQ-RS scheme for qT ¼ 8.
The Gray counter is controlled by an external uniform main clock fCLK and based on N ¼ log2(qT) D-latches. The signals {G0, G1, y, GN1} delivered by this counter are combined to generate the qT sampling phases with different duty cycles. Gray counter enumeration reduces the number of jumps between delivered signals {Gi}, then glitches are reduced in all subsequent combinational logic. However, the linear feedback shift register (LFSR) generates a binary pseudorandom sequence {L0, L1, y, LN1}. When controlled by qT times slower clock, the LFSR presents N length minimal characteristic polynomial given by Eq. (6). pðxÞ ¼ xN þ xm þ 1
(6)
where m should be absolutely chosen between 0 and N [26]. The generated pseudorandom numbers perform a uniform probability density function in case of JRS scheme, and are taken in the set of {0, 1, y, qT1}. Therefore, statistical parameter s/Ts is given in Eq. (7). sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi s 1 ðqT 1Þ2 1 ¼ (7) T s qT 12
Fig. 5. PSS circuit digital design architecture (N ¼ log2(qT)).
3.2. Pseudorandom signal sampler defined circuit To sample non-uniformly, we define several sampling phases instead of conventional uniform sampling. The solutions based on phases, noted {F0, F1, y, FqT1} and presented in Fig. 4, suffer from overlapping phases. This creates the loss of information due to the time shift between ADC present outputs and receiving the next phase. The delay between the two successive clock phases is the minimum spacing D defined in Eq. (3), and the phases duty cycles are equal. The question is how to generate these phases without overlapping between {F0, F1, y, F(qT/2)1} and {F(qT/2), y, FqT1}. We propose a new design, called PSS to overcome the overlap problem. Fig. 5 illustrates the block diagram of the PSS. For the phase design process, we precisely produce phase segmentation thanks to Gray counter. Combining function is defined to take care of falling down current phase before next phase rising edge.
For qT ¼ 16, we achieve a pseudorandom sequence characterized by s/Ts ¼ 0.27 which is the nearest value to the theoretical one (0.288), given in Section 2, for a small number of latches. The last stage is the multiplexer MUX qT:1 which acts as a selective combiner. It selects the phase Fi addressed by the generated pseudorandom number i each period of fdiv. The main clock fCLK has a period equal to the minimum spacing D needed for the TQ-RS scheme. In NUS-based SDR receiver, the main clock could be taken from a multiband phase-locked loop (PLL). The mean sampling frequency is fs ¼ fdiv ¼ fCLK/qT where fCLK is the main clock frequency delivered by the PLL. Two modifications have been done to improve the accuracy. First, instead of generating a qT divided clock, we control the LFSR by the first generated phase F0. This modification is necessary to obtain synchronization between the multiplexer inputs and addresses. Second, the multiplexer introduces some delay between phases selection. Therefore, the pseudorandom clock PSSout presents glitches which are shorter than the specified minimum spacing D. If they are not suppressed, ADC will wrongly sample the input signal. For that reason, the multiplexer output was fed through a D-latch controlled by the main clock fCLK to deliver pseudorandom clock PSSout. Resulting modified PSS architecture is presented in Fig. 6.
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Table 5 Instantaneous sampling periods, sampling frequencies and duty cycles for qT ¼ 16.
Fig. 6. PSS circuit modified digital design architecture (N ¼ log2(qT)).
Instantaneous sampling frequency fi takes values between minimum and maximum frequencies defined in Eq. (8). f CLK pf i pf CLK ð2qT 1Þ
(8)
For LFSR polynomial given by Eq. (6), the obtained frequencies are different from those given by Eq. (8). Indeed, pseudorandom numbers in case of qT equal to 16 are presented in Table 5. For each LFSR generated number i, we compute the instantaneous duty cycle DCi and the mean sampling period Ti, which is the D step occurrences between two successive positive edges, given by Eq. (9). T i ¼ ½qT iðkÞ þ iðk þ 1ÞD;
1pkpqT 1
(9)
where Ti is equal to 1/fi, fi is the instantaneous sampling frequency. We can then extract the minimum and maximum sampling frequencies as given in Table 5. ADC must be able to convert at mean sampling frequency fs and computed maximum sampling frequency must be two times lower than the effective resolution bandwidth. Reducing sampling at mean sampling frequency fs instead of uniform sampling at qTfs decreases ADC dynamic power consumption near qT times [27].
LFSR output i
DCi (%)
Ti
fi
1 2 4 9 3 6 13 10 5 11 7 15 14 12 8 Mean sampling frequency
50.00 50.00 50.00 43.75 50.00 50.00 18.75 37.50 50.00 31.25 50.00 6.25 12.50 25.00 50.00
17D 18D 21D 10D 19D 23D 13D 11D 22D 12D 24D 15D 14D 12D 9D
fCLK/17 fCLK/18 fCLK/21 fCLK/10 fCLK/19 fCLK/23 fCLK/13 fCLK/11 fCLK/22 fCLK/12 fsmin ¼ fCLK/24 fCLK/15 fCLK/14 fCLK/12 fsmax ¼ fCLK/9 fCLK/16
fs
obtained when using a main clock frequency between 16 MHz and 3.2 GHz. Despite inconvenience of existing non-uniform sampler architectures for NUS-based SDR receiver, PSS offers a large sampling frequency range, a smaller die area and a less power consumption as recapitulated in Table 6. The obtained pseudorandom signal sampler power consumption is lower than the values mentioned in [10,16] for the same generated mean sampling frequencies. For example, for fs ¼ 53.546 MHz, the design in [16] consumes 8.25 W and our design consumes 77.64 mW. For fs ¼ 43.7 MHz, the design in [10] consumes 2.7 mW and our design consumes 63.36 mW. PSS adapted to NUS-based SDR receiver specifications consumes only 4.35 mW at 3 MHz, 11.13 mW at 7.68 MHz and 24 mW at 16.6 MHz. The designed PSS delivers up to 200 MHz and this could furthermore relax constraints on the baseband for future standards and services specifications. If we include AGC only for GSM received signals, the NUSbased SDR receiver presented in Section 2 needs a 12-bit ADC at fs ¼ 16.6 MHz. The alias-free phenomenon, for designed NUSbased SDR receiver, was tested in a mixed experimental/simulation environment. This mixed test environment is set up as follows: a Matlab/Simulink reference model is defined for the sample-and-hold (S/H) circuit followed by a quantization bloc. A sine wave is applied at the input of S/H circuit. Non-uniform sampling achieved by the S/H circuit model is controlled by a physical signal delivered by the pseudorandom signal sampler hardware circuit. Quantized S/H output was processed with the cubic spline reconstruction algorithm. Obtained spectrum after reconstruction shows a dynamic range 72 dB which is near to 12bit ADC dynamic range. Fig. 8 shows quantized S/H output spectrum after reconstruction algorithm compared to spectrum in conventional uniform sampling processing.
4. PSS circuit implementation and evaluation results Functional verification of the proposed PSS architecture is synthesized in VHDL to generate fs ¼ 16.6 MHz. For qT ¼ 8 and 16, the statistical parameter s/Ts is, respectively, 0.254 and 0.275. The phases and pseudorandom numbers used to generate the pseudorandom clock PSSout are given in Fig. 7. To validate the proposed idea for circuit design, the PSS architecture described in the previous section, was implemented in CADENCE for a 65 nm digital CMOS technology. The signal generation as described above has been verified through electrical post-layout simulation. PSS occupies a 470 (mm)2. It allows up to mean sampling frequency fs equal to 200 MHz. PSS circuit consumes between 1.21 and 242 mA from 1.2 V supply for obtained frequency test between 1 and 200 MHz. These frequencies are
5. Conclusion In this paper, a new NUS-based SDR receiver implemented by an original design of a PSS circuit has been proposed to enhance multistandard radio signals digitalization while maintaining relaxed design constraints for receiver circuit baseband stages such as AAF, ADC and AGC. NUS-based receiver design was tuned for the best trade-off between relaxing AAF selectivity and decreasing the mean sampling frequency when operating in implicit over-sampling mode to reduce ADC dynamic power consumption. To compensate limitations of existing non-uniform oscillators in [10,16], PSS circuit design is based on an accurate generation of sampling instants in the time quantized jittered and
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Fig. 7. PSS generated phases measurement for qT ¼ 8, phase[i] represents Fi for 0pip(qT1) and lfsr_out[j] represents Lj for 0pjp(log2(qT)1).
Table 6 Performances comparison of existing sampler designs with proposed PSS. Ref.
fs (MHz)
Area
Power consumption
Technology
[16] [13] [14] [10] Proposed PSS in this paper
53.546 N.C. N.C. 43.7 1–200
185 mm 162 mm 3264 (mm)2 3350 (mm)2 N.C. 470 (mm)2
8.25 W N.C. N.C. 2.7 mW 1.45 mW at 1 MHz to 290.4 mW at 200 MHz 24 mW at 16.6 MHz
Printed circuit board Target 130 nm IBM Cu-11 Target 130 nm IBM Cu-11 Spice AMS SiGe 0.35 mm BiCMOS Target 65 nm digital CMOS
0 y__US y__PSS
Normalized Power Spectrum Density (dBm)
-20 -40 -60 -80 -100 -120 -140 -160 -180
0
1
2
3
4 5 Frequency (MHz)
6
7
8
9
Fig. 8. PSS controlled S/H output spectrum after cubic spline reconstruction (y_PSS) versus uniform sampling S/H output spectrum (y_US).
additive random sampling, an integrated PSS circuit independently of the chosen CMOS process technology and a circuit depending only on external main clock frequency fCLK defining the
minimum step D equal to 1/fCLK. The 65 nm digital CMOS technology implementation of designed PSS leads to a circuit occupation area of 470 (mm)2.
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The proposed NUS receiver architecture and PSS circuit performances were validated for GSM/UMTS/WiFi multistandard radio processing. The PSS circuit consumes between 1.21 and 242 mA from 1.2 V supply for frequency test between 1 and 200 MHz. Proposed NUS design allows a 72 dB (12-bit) ADC dynamic range and leads to a 45 dB reduction in required AGC maximum of gain compared with conventional uniform design.
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