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Randomly prioritized buffer-less routing architecture for 3D Network on Chip
Computers and Electrical Engineering 59 (2017) 39–50
Contents lists available at ScienceDirect
Computers and Electrical Engineering journal homepage: www.elsevier.com/locate/compeleceng
Randomly prioritized buffer-less routing architecture for 3D Network on ChipR A. Karthikeyan a,∗, P. Senthil Kumar b a
Department of Electronics and Communication Engineering, Vel Tech Multi Tech Dr. Rangarajan Dr. Sakunthala Engineering College, Chennai, Tamil Nadu, 600062, India b Department of Information Technology, SKR Engineering College, Poonamalle, Chennai, Tamil Nadu, 600069, India
a r t i c l e
i n f o
Article history: Received 27 September 2016 Revised 9 March 2017 Accepted 9 March 2017
Keywords: SoC, Noc 3D-Noc Scheduling algorithm Round Robin algorithm Lottery algorithm etc
a b s t r a c t Recently, 3D NoC has become more important than 2D NoC due its new geometrical arrangement and also reduces the wire length from global interconnect to local interconnect. One of the main components to implement 3D NoC is the router. The components of the router are crossbar, FIFO, and arbiter. The scheduling algorithm is the main part of the arbiter which schedules and delivers all packets to the destination nodes without any loss of packets. Packets that have the highest priority are served first,the remaning highest priority packets ares queued in the priority register and non-priority packets are served after all priority packets are served. Round Robin routing algorithm is commonly used as the scheduling algorithm in most of the routers. This paper proposes a novel 3D lottery routing algorithm which is based on arbitral mechanism like randomly prioritized buffer. Communication among the IPs in NoC can be customized by users through the lottery router. The lottery routing algorithm distinguishes the different priorities of the input port and makes sure that it responses to the higher priority port. The efficient hardware implementation of 3D NoC is proposed using Xilinx Spartan 3E FPGA, the result shows that the proposed architecture consumes 1644 slices out of 4656 slices and operates at the maximum frequency of about 103.602 MHz. The 3D NoC is modeled and implemented with a Cadence Electronic Design Automation tool and the results show that the power consumption of 3D NoC is reduced by 9% compared to a single layer. © 2017 Elsevier Ltd. All rights reserved.
1. Introduction Recently, the complex System-on-chip (SoC) has been implemented using new design paradigm Network-on-Chip (NoC). The data packet is routed through a routing algorithm instead of dedicated wires [1–14]. The objective behind NoCs is to replace the design based system-on-chip global interconnection wires with the interconnection network. The generic processing elements (PE), namely the general processor, memories, FPGAs, ASICs etc are interconnected and communication between them is by specialized routers [18]. The NoC has concurrent communication to increase the bandwidth, scalability and predictability compared with the normal SoC.
R ∗
Reviews processed and recommended for publication to the Editor-in-Chief by Associate Editor Dr. R. Varatharajan. Corresponding author. E-mail addresses: [email protected] (A. Karthikeyan), [email protected] (P. Senthil Kumar).
http://dx.doi.org/10.1016/j.compeleceng.2017.03.006 0045-7906/© 2017 Elsevier Ltd. All rights reserved.
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A. Karthikeyan, P. Senthil Kumar / Computers and Electrical Engineering 59 (2017) 39–50
Due to lack of multiple efficiency, higher global interconnection, high power consumption and speed in 2D NoC, motivated researchers pay more attention to a new generation of NoC and this has lead to research of 3D NoC [19,21]. The 2D NoC has many problems such as electro migration and thermal issues that urge us to investigate 3D NoC. The problem in the increase of demand in global interconnections and the delay of integrated systems are solved by the emerging 3D technique. Advantages of 3D NoC over 2D NoC include: I The layers are interconnected by silicon vias (TSVs) and the average delay for the interconnection is reduced drastically. II The area required for manufacturing of the 3D chip is less compared to 2D-NoC. In order to meet the average communication delay for a specific application, the lottery arbiter is used in place of Round Robin arbiter. Each port has different priority values and communication demands are set in this arbiter. The lottery arbiter mechanism has the advantage of setting the priority for different requests and the need for an additional buffer in the case of heavy communication is not required. The starvation hitch in the predetermined precedence is not present in the lottery arbiter. The variable priority values in run time or in reconfiguration process can be implemented by using lottery arbiter [20]. The second part of this paper deals with different types routing algorithms and the third part proposes lottery microarchitecture for the 3D NoC router. The fourth part discusses the implementation and analyses of this architecture in terms of FPGA area and delay [17]. The last section deals with the conclusion and future direction. 2. Routing algorithm for 3D-NoC There are different routing algorithms present in 3D NoC. In this paper, we have analyzed different the routing algorithms and their power consumption. 2.1. Diagonal fault-tolerant routing algorithm When a Diagonal fault-tolerant routing algorithm encounters a faulty link or faulty node, it should identify the problem, escape this blocked situation and find another path to deliver the packets [4,16,24]. A 3D node is a temporary destination for each layer. There are three ways to tolerate faults in interconnection networks: Component redundancy is the easiest method that enables the system to continue its work in the presence of faults. In this method, once a failed component in the system is detected, it’s simply replaced by its redundant copy. This approach has a significant drawback which is the high extra cost of spare components that replace the faulty components. Fault-tolerant routing algorithm will usually tolerate problems in sending messages in presence of link or node failure and guarantees to deliver them to the destination. Faults are divided into two models, individual faults and faulty blocks in block model. Many of the healthy nodes and links assume faulty components to generate a suitable block to use in routing algorithm, but a negative aspect of this model is that the strong nodes become obsolete. We can specify n-D software based routing which is proposed for torus topology and it is the extension of Suh’s research from 2D to nD for faulty blocks in 3D NoC. Reconfiguration routing techniques [17,25] is reconfiguring the routing tables in presence of faulty links or nodes and in the case of failure, adopting them into new topology after failure. This routing algorithm can tolerate a high number of TSV’s failures. This uses a mixture of 3D and 2D routers which keep the power consumption less than the full 3D routers. 2.2. Dimension order XYZ routing algorithm In earlier researches, fully adaptive algorithm is presented in the Dimension Order XYZ routing [2,15,22 and 23]. Based on the traffic condition, dimension order XYZ routing algorithm can choose multiple paths in the network to avoid congestion. In this routing algorithm, the packets are routed to the next dimension after making offset zero in that dimension. The packets can travel three directions namely X, Y and Z until the distance along that direction never reaches zero. The network is divided into sub-networks of eight and has six directions namely East (E), West (W), North (N), South (S), Up (U) and Down (D). The algorithm guarantees that there is no deadlock and the packet can be delivered to three directions. Two types of virtual channels are used by the DyXYZ routing algorithm for all dimensions. The packets are routed along three dimensions without any cycles. In this algorithm, the congestion rate is calculated as the numeral of free buffer slots accessible in the resultant input buffer of the adjacent router. The input buffer is congested when the numeral of free buffer slots is larger than the threshold rate. The threshold rate is 70% of the total input buffer size. 2.3. Look ahead XYZ routing algorithm Look ahead XYZ routing algorithm [3,23] is the pipeline design of conventional XYZ routing algorithm. For performance enhancement of heavy traffic, the virtual channels are not considered in this algorithm. To improve the throughput, this algorithm uses four pipeline systems; Buffer writing (BW), Routing Calculation (RC), Switch Arbitration (SA) and the Crossbar Traversal stage (CT). The performance is degraded since each hop goes through the four stages and increases the flit latency. In the pipelining system, the information can be collected from the previous stage and the operations from each stage are
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Fig. 1. An assortment system of router pipeline: (a) conventional XYZ (b) LA-XYZ (c) LA-XYZ with no-load bypass.
dependent relative. This dependence is present in RC and SA stage and this dependence is eliminated in the Look ahead XYZ by having the parallelism of RC and SA stages. Fig. 1 represents the router pipelining systems of XYZ and LA-XYZ and LA-XYZ with no load bypass. 2.4. Lottery router The routing algorithms which are listed above have certain drawbacks such as suitability of NoC applications which have hotspots or the network has priority requirements [5,9]. In order to solve this problem, the previous algorithms have owed superfluous buffers into the weighty communication channels to discriminate the precedence of each channel. The extra buffers require additional resource area and hence consume extra power. In order to reduce the additional buffer size, we propose the 3D-NoC lottery arbiter. This algorithm will customize priorities [8,12, and 14] according to the variable demands of heavy communication and each channel can be configured for the specific application [6]. The advantages of the lottery arbiter over other arbiters are: I The proposed lottery arbiter is able to set up dynamically different priorities for different communication demands while maintaining the average communication for each specific NoC application. II The variable priority values can be implemented by fixed reconfiguration or at run-time dynamic configuration mechanism. III For heavy communication, the impact of using additional buffer is not required. IV In the fixed priority scheme, the ‘starvation’ problem is eliminated in this arbiter. 3. Proposed lottery based 3D-NoC The proposed 3D NoC lottery algorithm is based on arbitral mechanism. Depending upon the communication precedence each input port obtains certain statistics of ‘lottery’. Higher precedence port gains a huge number of lottery and vice versa. Due to conflicts occurring between the requests of the several input ports, each port will give in their hold lotteries to the arbiter. According to the lottery likelihood, the lottery arbiter will randomly select the requests and then respond to the selected port. There will be an average communication in each port compared to any other arbiter using this arbitration mechanism. Each port will be assigned with different priorities according to the communication demands of the port. The following Fig. 2 shows the 3D NoC lottery arbiter. The capacity of the lottery arbiter has to change the precedence of each
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Fig. 2. Lottery based 3D NoC.
port according to the request and demand. In order to customize and get used to the present state, the NoC is accepted whenever the communication traffic changes. The run-time configuration or priority reconfiguration function is to be built inside the NoC hardware. The different communication priorities are very difficult to implement to the hardware relocation like buffer size, bandwidth, interconnecting wires etc. The priority reconfiguration value of different requests is done by the use of software in the lottery arbiter. This approach will have a significant advantage in the future of dynamic reconfiguration of NoC [10,11]. This proposed arbiter does not have extra buffer for the heavy communication port and solves the starvation problem in fixed priority arbiter. In 3D lottery arbiter algorithm, each requested port gains the lottery number according to its current priority (based on current situation). If more than one port submit simultaneously requests to acess a particular port, the lottery arbiter uses priority probability i.e. the lottery value (threshold value of each port according to its priority) which was generated through the lottery generator. The random number generator will produce an arbitrary number which is accolade lottery. The arbitrary number compares the threshold value of each port and confirms the ports which win the accolade. The arbiter then sends the acknowledgment signal after verifying the grant signal of the input ports and the status of the output buffer. If the output buffer is full, the acknowledgment signal is deemed invalid and the data of the input port is not transmitted to the output buffer. The arbiter invalids the current accolade and generates another arbitrary number through random generator block. Let us assume r1 , r2 , r3 , ..........rn represents the request of each port. If ‘i’ port is requesting the arbitration then the corresponding ri = 1, otherwise ri is assigned as ‘0’. l1 , l2 , l3 , .......ln are the lottery number of the port according to the communication priorities. The response probability is calculated as per the Eq. (1)
ri li P (Ci ) = n j=1
(1)
r jl j
Let us assume L is the intact quantity of lottery and each port threshold significance is obtained using Eq. (2)
T hreshold = P (Ci ) ∗ L +
i−1 j=1
P (C j ) ∗ L
(2)
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Fig. 3. The micro-architecture of NoC router.
The proposed lottery algorithm operates in two modes; inconsistent and determined totality number. In the inconsistent approach, the totality number L is obtained by the following formula;
L=
ri ∗ li
(3)
In the predetermined, L which is the totality number lottery is constant, but the threshold significance is varied. The arbiter generates a threshold rate depending on the precedence rate of each port when there is a call from a port. The arbitrary number generator generates a random number [1, L] and it is compared with the threshold of each port to make sure which request is granted. For example, If the arbitrary number be on [threshold E, threshold W], the port W will gain the grand while the other ports request are discarded. Fig. 3 shows the micro-architecture of the NoC router: Lottery arbiter routing algorithm p: number of IPCs per router request(req): IPC requests of each grant (gnt): IPC grants for each t: index time begin lottery scheduler assign j = 1 // grant initialization for i=0 to p-1 do { gnt(i) = 0 // initially all grant is zero end } While j > t do loop { N = random generator(); for i=1 to p-1 do { if (req(i)=1) then if (N > threshold (i)) then gnt(i) = 1 exit end end } end // Increment time slot j=j+1 end } end loop end lottery scheduler
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Fig. 4. Architecture of lottery arbiter.
Fig. 4 shows architecture developed for lottery arbiter routing algorithm as explained above. 4. Performance simulation The micro-architecture of the 3D lottery router is implemented using VHDL and the proposed design is coded and simulated. Fig. 5 represents the simulation result of lottery router. The performance results of the proposed architecture which considers six input ports and one output port are shown in Fig. 6 through the RTL View. The six input port has the same data injection rate and sends the data to the one output port. The six input ports which are South, Local, East,West, Up and Down port and the North port, are assigned as output ports. Exploitation rate and arbitral recital of the anticipated route is usually compared with RR router. In the Round Robin arbitral mechanism, the exploitation pace is similar to all input ports. Advantages of the three dimensional integration are mainly due to vertical interconnects, i.e., TSV. They also incur overheads hence unlimited TSVs cannot be afforded. Optimization of TSV to save on area without sacrificing the performance is needed, thus the optimization of 3D NoC is carried out by optimizing the number of vertical links using the algorithms Genetic Algorithm (GA). Since GA has robust latency compared to other optimization, the latency decreases as the number of vertical links increase due to the fact that there are shorter paths for the packets to travel from the source to destination. In the RR arbiter, each input port inhabits the output port irrespective of data inoculation rate and the priorities of diverse packets are not renowned. The RR arbiter algorithm [9] treats low priority packets and high priority packets alike. The high priority packets enters in the North port and the utilization rate is similar to other ports. In the proposed 3D lottery intercession mechanism, high precedence packets will gain more tickets and will get high communication priorities. In this example, the north input port is assigned as the higher priority port. Fig. 7 shows the utilization rate of six input ports using the Round-Robin arbiter exigent for one output port. From this simulation, we can effortlessly recognize that all input ports averagely maintain in the output when the data inoculation rate is small (0.10, 0.15 and 0.16). In the lower data inoculation rate there is no conflict and there is still some inactive time left. In the above cases, all input ports transmit the data successfully to the output port regardless of the port priority. For higher data input rates, the lottery arbiter does not persuade all input ports data transmission. Fig. 8 shows that the utilization rate of six input ports using the Round-Robin arbiter competing for one output port. The proposed 3D lottery arbiter is able to discriminate the priority of the dissimilar packets and make sure that precedence packets are transmitted first towards the output port at a high communication rate. The proposed 3D lottery arbiter is compiled using VHDL hardware description language and is implemented using Xilinx FPGA. Table 1 shows the Device utilization summary of 3D lottery arbiter architecture. The area and power of a NoC router are evaluated based on the implementation results. Table 2 shows the total router area comprising of the including and excluding area taken by vertical links. The area of the router with inductive or ca-
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Fig. 5. Simulation result of lottery router.
Table 1 Device utilization (Selected device: 3s500eft256-5). Sl.No
Description
Used
Available
% of Utilization
1 2 3 4 5 6 7
Number of slices Number of slice flip flops Number of 4 input LUTs Number used as logic Number used as RAMs Number of bonded IOBs Maximum frequency of operation
1644 1017 2777 2369 408 92 103.602 MHz
4656 9312 9312
35% 10% 29%
190
48%
Table 2 Comparison of power and area of NoC and interconnect. No of layer
Area of NoC (um2 )
Area of interconnect (um2 )
Total area
The Power of NoC (mw)
Power of interconnect (mw)
Total power (mw)
1 2 4
52,324 53,231 55,045
8523 2457 923
60,847 55,688 55,968
0.5217 0.5255 0.5298
0.0712 0.0112 0.0092
0.5929 0.5367 0.539
pacitive links using serialization is only 1.1 times larger than the router with TSV for pitches not larger than 100 um. In this section, inductive/capacitive coupling vertical links are evaluated using the simulator in the context of a 3D NoC. In the simulator, we model a 2-Tier, 8-Core 3D CMP with a shared L2 cache distributed into 8 banks. These 16 nodes are interconnected by a 3D NoC configured as a 3D MESH (2 × 2 by 2 layers). The area and power of proposed NoC are stated in Table 2, for ST Micro 180 nm technology and 5 GHz frequency. The whole CMP (processor, cache, NoC) is clocked at 1.5 GHz.
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Fig. 6. RTL view of lottery algorithm.
Fig. 7. Port utilization of Round-Robin arbiters for various injection rates.
Fig. 9 shows a comparison of the area occupied by the NoC and interconnects for various number of layers. From the comparison chart, the area occupation of 3D Noc decreases to a maximum of 80% when there are four layers while the total area slightly increases (around 10% of 1D NoC) due to additional unit of 3D Noc Control unit. The result shows that the area of the interconnects drastically reduces with gradual increment of the NoC area due to data transfer transceivers. Fig. 10 shows the comparison of the power consumed by the NoC and interconnect for various number of layers. In 3D, the congestion of interconnect is reduced by increasing the number of layers thus reduces the power consumtion of interconnect layers by 70% comparing to 1D interconnect layer. The result shows that the power consumption of the interconnect drastically reduces with the slight increment of NoC power due to data transfer transceivers block. Power consumption reduces by 9% when the NoC has four layers. The area and power consumption of the other routing algothims are shown in Table 3. The table shows that the results obtained for lottery based NoC gives better area utilization and power consumption.
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Fig. 8. Port utilization of lottery arbiter for various injection rates.
Fig. 9. Comparison charts for area utilization of loterry router in different layers.
Fig. 10. Comparison charts for power consumption of loterry router in different layers.
Table 3 Area and power comparison of various routing algorithm. Algorithm used in 3D NoC (2 layer)
Area of NoC (um2)
Area of interconnect (um2)
Total area (um2)
Power of NoC (mw)
Power of interconnect (mw)
Total power (mw)
Dimension order XYZ routing algorithm Diagonal fault-tolerant routing algorithm Look ahead XYZ routing algorithm Lottery based routing algorithm
55,492 56,413 54,456 53,231
2784 2684 2638 2457
58,276 59,097 57,094 55,688
0.5841 0.5958 0.6258 0.5255
0.0196 0.0185 0.0238 0.0112
0.6037 0.6143 0.6496 0.5367
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Fig. 11. Comparison charts for power consumption of various routing algorithm.
Fig. 12. Comparison charts for power consumption of various routing algorithm.
Figs. 11 and 12 shows the comparison chart for area and power consumption for various routing algorithms. The chart clearly shows that the loterry based routing algorithm consumes less area and power consumption compared with other routing algorithms. 5. Conclusion Lottery arbitral mechanism for the 3D NoC router architecture is proposed and implemented. Different communications has different priorities and is based on the applications, the projected algorithm to constitute the priority of dissimilar port is implemented. Further, we proposed micro-architecture for the 3D lottery router and we introduced the function of lottery arbiter. The output port exploitation space of dissimilar input port in the proposed 3D lottery mechanism is estimated with Round-Robin mechanism. The compared results reveal that the Lottery router can discriminate different communication priorities and promise the high priority packets to achieve supplementary network resources. In conclusion, 3D lottery NoC has better performance compared with other 3D-NoC. The 3D-NoC is modeled and implemented with Cadence EDA tools and the result shows that power consumption is reduced to 9% compared with a single layer. In future, lottery based routing algorithm can be implemented and analyzed in GALS lottery based routing algorithm by comparing the area, power and delay and design bundled-data asynchronous Network-on-Chip router. References [1] Benini L, De Micheli G. Networks on Chips: a new SoC paradigm. IEEE Comput 2002:70–8 Jan. [2] Ebrahimi Masoumeh, Chang Xin, Daneshtalab Masoud, Plosila Juha, Liljeberg Pasi, Tenhunen Hannu. In: Dy-xyz fully adaptive routing algorithm for 3D NoCs IEEE conference publications; 2013. p. 499–503. [3] Akrambenahmed Abderazekbenabdullah. Low latency high through put look-ahead routing algorithm for 3D Network-on-Chip (3D-NoC) architecture. In: IEEE conference publications; 2012. p. 167–74. [4] Akbari Sarah, Isvandi Maryam, Fathi Mahmod, Barangi Reza. Diagonal fault-tolerant routing algorithm for 3D multi-layer Networks-on-Chip IASBS, Zanjan, Iran; 2011 May 31-June 2. [5] Eung S. Shin, Vincent J. Mooney III, George F. Riley. Round-Robin arbiter design and generation. In: ISSS’02 october 2–4; 2002. [6] Jer-min jou, Yun-lung lee. An optimal Round-Robin arbiter design for NoC. J Inf Sci Eng 2010;26:2047–58. [7] Xiaopeng Gao, Zhe Zhang, Xiang Long. Round Robin arbiters for virtual channel router. In: IMACS multiconference on computational engineering in systems applications (CESA), October 4-6; 2006. [8] Chang Wu, Yubai Li, Song Chai, Zhongming Yang, Lottery router: a customized arbitral priority NoC router International conference on computer science and software engineering 978-0-7695-3336-0/08
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[9] Suyog KDahule, Gaikwad MA. Design & simulation of Round Robin Arbiter for NoC Architecture. Int J Eng Adv Technol 2012;1(6) (IJEAT+) ISSN:2249–8958 August. [10] Jian Wang, Yubai Li, Qicong Peng, Taiqiu Tan, A dynamic priority arbiter for Network-an-Chip IEEE transactions 978-1-4244-4110-5/09. [11] Neeta Doifode, Dinesh Padole, Dr. Preeti Bajaj, Dynamic lottery bus arbiter for shared bus system on chip: a design approach with VHDL, International conference on emerging trends in engineering and technology IEEE computer society 978-0-7695-3267-7/08. [12] Lahiri Kanishka, Raghunathan Anand, Lakshminarayana Ganesh. The LOTTERY BUS on-chip communication architecture. IEEE Trans Very Large Scale Integr (vlsi) Syst 2006;14(6) june. [13] Yan Ghidini, Thais Webber, Edson Moreno, Fernando Grando, Rubem Fagundes, César Marcon, Buffer depth and traffic influence on 3D NoCs performance IEEE Trans Very Large Scale Integr 978-1-4673-2789-3/12 [14] Chang Wu. Lottery router: a customized arbitral priority NoC router. In: International conference on computer science and soft ware engineering; 20 08 12/20 08. [15] Ebrahimi M, Chang Xin, Daneshtalab M, Plosila J, Liljeberg P, Tenhunen H. DyXYZ: fully adaptive routing algorithm for 3D NoCs. In: 2013 21st Euromicro international conference on parallel distributed and network- based processing; 2013. [16] Ben Ahmed Akram, Abderazek Ben Abdallah. Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC). J Supercomput 2013;66(3):1507–32. [17] de Paulo Vitor, Ababei Cristinel. 3D Network-on-Chip architectures using homogeneous meshes and heterogeneous floorplans. Int J Reconfigurable Comput 2010;2010 Article ID 603059, 12 pages. [18] Zhizhou Fu. The design and implementation of arbiters for Network- on- Chips. In: 2nd International conference on industrial and information systems, 07/2010; 2010. [19] Ahmed AkramBen, Abderazek Ben Abdallah. Low- overhead routing algorithm for 3D Network- on-Chip. In: Third international conference on networking and computing; 2012. p. 2012. [20] Warathe Kanchan. A design approach to AMBA (Advanced Microcontroller Bus Architecture) bus architecture with dynamic lottery arbiter. In: Annual IEEE India conference; 2009 12/2009. [21] Sweety A, Karthikeyan A, Jebasingh Kirubakaran SJ. Analysis and performance comparison of 3-D NoC routing algorithms. Int J Appl Eng Res 2015;10(5):13415–29. [22] Khan MA, Ansari AQ. Quadrant-based XYZ dimension order routing algorithm for 3-D Asymmetric Torus Routing Chip (ATRC). In: 2011 International conference on emerging trends in networks and computer communications (ETNCC), Udaipur; 2011. p. 121–4. [23] Ahmed AB, Abdallah AB. LA-XYZ: low latency, high throughput look-ahead routing algorithm for 3D Network-on-Chip (3D-NoC) architecture. In: 2012 IEEE 6th International symposium on embedded multicore SoCs, Aizu-Wakamatsu; 2012. p. 167–74. [24] Zhang Zhen, Serwe Wendelin, Wu Jian, Yoneda Tomohiro, Zheng Hao. Formal analysis of a fault-tolerant routing algorithm for a Network-on-Chip. In: 19th International conference on formal methods for industrial critical systems, FMICS2014, Sep, Florence, Italy. Springer; 2014 8718, pp.48-62, 20. [25] Valinataj Mojtaba, Mohammadi Siamak, Plosila Juha, Liljeberg Pasi, Tenhunen Hannu. A reconfigurable and adaptive routing method for fault-tolerant mesh-based networks-on-chip. Int J Electron Commun 2011;65:630–40.
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Karthikeyan Appathurai received the B.E., degree in Electronics and Communication from Manonmaniam Sundaranar University, Tirunelveli in 2004 and M.E., degree in Embedded System Technologies from Anna University, Chennai in 2007 and is currently working toward the Ph.D degree at Anna University, Chennai. His research interest includes Network on Chip. SenthilKumar Ponnusamy is currently working as Professor and Head of the Department of Information Technology, SKR Engineering College, Chennai. He received his ME in 2002 from Arulmigu Kalasalingam college of engineering, Krishnankovil and Ph.D in 2010 from Bharathiyar University, India. He has 18 years of experience in various engineering college. He has published more than 30 papers in various national and International journal and conferences. His area of research is network.
Contents lists available at ScienceDirect
Computers and Electrical Engineering journal homepage: www.elsevier.com/locate/compeleceng
Randomly prioritized buffer-less routing architecture for 3D Network on ChipR A. Karthikeyan a,∗, P. Senthil Kumar b a
Department of Electronics and Communication Engineering, Vel Tech Multi Tech Dr. Rangarajan Dr. Sakunthala Engineering College, Chennai, Tamil Nadu, 600062, India b Department of Information Technology, SKR Engineering College, Poonamalle, Chennai, Tamil Nadu, 600069, India
a r t i c l e
i n f o
Article history: Received 27 September 2016 Revised 9 March 2017 Accepted 9 March 2017
Keywords: SoC, Noc 3D-Noc Scheduling algorithm Round Robin algorithm Lottery algorithm etc
a b s t r a c t Recently, 3D NoC has become more important than 2D NoC due its new geometrical arrangement and also reduces the wire length from global interconnect to local interconnect. One of the main components to implement 3D NoC is the router. The components of the router are crossbar, FIFO, and arbiter. The scheduling algorithm is the main part of the arbiter which schedules and delivers all packets to the destination nodes without any loss of packets. Packets that have the highest priority are served first,the remaning highest priority packets ares queued in the priority register and non-priority packets are served after all priority packets are served. Round Robin routing algorithm is commonly used as the scheduling algorithm in most of the routers. This paper proposes a novel 3D lottery routing algorithm which is based on arbitral mechanism like randomly prioritized buffer. Communication among the IPs in NoC can be customized by users through the lottery router. The lottery routing algorithm distinguishes the different priorities of the input port and makes sure that it responses to the higher priority port. The efficient hardware implementation of 3D NoC is proposed using Xilinx Spartan 3E FPGA, the result shows that the proposed architecture consumes 1644 slices out of 4656 slices and operates at the maximum frequency of about 103.602 MHz. The 3D NoC is modeled and implemented with a Cadence Electronic Design Automation tool and the results show that the power consumption of 3D NoC is reduced by 9% compared to a single layer. © 2017 Elsevier Ltd. All rights reserved.
1. Introduction Recently, the complex System-on-chip (SoC) has been implemented using new design paradigm Network-on-Chip (NoC). The data packet is routed through a routing algorithm instead of dedicated wires [1–14]. The objective behind NoCs is to replace the design based system-on-chip global interconnection wires with the interconnection network. The generic processing elements (PE), namely the general processor, memories, FPGAs, ASICs etc are interconnected and communication between them is by specialized routers [18]. The NoC has concurrent communication to increase the bandwidth, scalability and predictability compared with the normal SoC.
R ∗
Reviews processed and recommended for publication to the Editor-in-Chief by Associate Editor Dr. R. Varatharajan. Corresponding author. E-mail addresses: [email protected] (A. Karthikeyan), [email protected] (P. Senthil Kumar).
http://dx.doi.org/10.1016/j.compeleceng.2017.03.006 0045-7906/© 2017 Elsevier Ltd. All rights reserved.
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Due to lack of multiple efficiency, higher global interconnection, high power consumption and speed in 2D NoC, motivated researchers pay more attention to a new generation of NoC and this has lead to research of 3D NoC [19,21]. The 2D NoC has many problems such as electro migration and thermal issues that urge us to investigate 3D NoC. The problem in the increase of demand in global interconnections and the delay of integrated systems are solved by the emerging 3D technique. Advantages of 3D NoC over 2D NoC include: I The layers are interconnected by silicon vias (TSVs) and the average delay for the interconnection is reduced drastically. II The area required for manufacturing of the 3D chip is less compared to 2D-NoC. In order to meet the average communication delay for a specific application, the lottery arbiter is used in place of Round Robin arbiter. Each port has different priority values and communication demands are set in this arbiter. The lottery arbiter mechanism has the advantage of setting the priority for different requests and the need for an additional buffer in the case of heavy communication is not required. The starvation hitch in the predetermined precedence is not present in the lottery arbiter. The variable priority values in run time or in reconfiguration process can be implemented by using lottery arbiter [20]. The second part of this paper deals with different types routing algorithms and the third part proposes lottery microarchitecture for the 3D NoC router. The fourth part discusses the implementation and analyses of this architecture in terms of FPGA area and delay [17]. The last section deals with the conclusion and future direction. 2. Routing algorithm for 3D-NoC There are different routing algorithms present in 3D NoC. In this paper, we have analyzed different the routing algorithms and their power consumption. 2.1. Diagonal fault-tolerant routing algorithm When a Diagonal fault-tolerant routing algorithm encounters a faulty link or faulty node, it should identify the problem, escape this blocked situation and find another path to deliver the packets [4,16,24]. A 3D node is a temporary destination for each layer. There are three ways to tolerate faults in interconnection networks: Component redundancy is the easiest method that enables the system to continue its work in the presence of faults. In this method, once a failed component in the system is detected, it’s simply replaced by its redundant copy. This approach has a significant drawback which is the high extra cost of spare components that replace the faulty components. Fault-tolerant routing algorithm will usually tolerate problems in sending messages in presence of link or node failure and guarantees to deliver them to the destination. Faults are divided into two models, individual faults and faulty blocks in block model. Many of the healthy nodes and links assume faulty components to generate a suitable block to use in routing algorithm, but a negative aspect of this model is that the strong nodes become obsolete. We can specify n-D software based routing which is proposed for torus topology and it is the extension of Suh’s research from 2D to nD for faulty blocks in 3D NoC. Reconfiguration routing techniques [17,25] is reconfiguring the routing tables in presence of faulty links or nodes and in the case of failure, adopting them into new topology after failure. This routing algorithm can tolerate a high number of TSV’s failures. This uses a mixture of 3D and 2D routers which keep the power consumption less than the full 3D routers. 2.2. Dimension order XYZ routing algorithm In earlier researches, fully adaptive algorithm is presented in the Dimension Order XYZ routing [2,15,22 and 23]. Based on the traffic condition, dimension order XYZ routing algorithm can choose multiple paths in the network to avoid congestion. In this routing algorithm, the packets are routed to the next dimension after making offset zero in that dimension. The packets can travel three directions namely X, Y and Z until the distance along that direction never reaches zero. The network is divided into sub-networks of eight and has six directions namely East (E), West (W), North (N), South (S), Up (U) and Down (D). The algorithm guarantees that there is no deadlock and the packet can be delivered to three directions. Two types of virtual channels are used by the DyXYZ routing algorithm for all dimensions. The packets are routed along three dimensions without any cycles. In this algorithm, the congestion rate is calculated as the numeral of free buffer slots accessible in the resultant input buffer of the adjacent router. The input buffer is congested when the numeral of free buffer slots is larger than the threshold rate. The threshold rate is 70% of the total input buffer size. 2.3. Look ahead XYZ routing algorithm Look ahead XYZ routing algorithm [3,23] is the pipeline design of conventional XYZ routing algorithm. For performance enhancement of heavy traffic, the virtual channels are not considered in this algorithm. To improve the throughput, this algorithm uses four pipeline systems; Buffer writing (BW), Routing Calculation (RC), Switch Arbitration (SA) and the Crossbar Traversal stage (CT). The performance is degraded since each hop goes through the four stages and increases the flit latency. In the pipelining system, the information can be collected from the previous stage and the operations from each stage are
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Fig. 1. An assortment system of router pipeline: (a) conventional XYZ (b) LA-XYZ (c) LA-XYZ with no-load bypass.
dependent relative. This dependence is present in RC and SA stage and this dependence is eliminated in the Look ahead XYZ by having the parallelism of RC and SA stages. Fig. 1 represents the router pipelining systems of XYZ and LA-XYZ and LA-XYZ with no load bypass. 2.4. Lottery router The routing algorithms which are listed above have certain drawbacks such as suitability of NoC applications which have hotspots or the network has priority requirements [5,9]. In order to solve this problem, the previous algorithms have owed superfluous buffers into the weighty communication channels to discriminate the precedence of each channel. The extra buffers require additional resource area and hence consume extra power. In order to reduce the additional buffer size, we propose the 3D-NoC lottery arbiter. This algorithm will customize priorities [8,12, and 14] according to the variable demands of heavy communication and each channel can be configured for the specific application [6]. The advantages of the lottery arbiter over other arbiters are: I The proposed lottery arbiter is able to set up dynamically different priorities for different communication demands while maintaining the average communication for each specific NoC application. II The variable priority values can be implemented by fixed reconfiguration or at run-time dynamic configuration mechanism. III For heavy communication, the impact of using additional buffer is not required. IV In the fixed priority scheme, the ‘starvation’ problem is eliminated in this arbiter. 3. Proposed lottery based 3D-NoC The proposed 3D NoC lottery algorithm is based on arbitral mechanism. Depending upon the communication precedence each input port obtains certain statistics of ‘lottery’. Higher precedence port gains a huge number of lottery and vice versa. Due to conflicts occurring between the requests of the several input ports, each port will give in their hold lotteries to the arbiter. According to the lottery likelihood, the lottery arbiter will randomly select the requests and then respond to the selected port. There will be an average communication in each port compared to any other arbiter using this arbitration mechanism. Each port will be assigned with different priorities according to the communication demands of the port. The following Fig. 2 shows the 3D NoC lottery arbiter. The capacity of the lottery arbiter has to change the precedence of each
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Fig. 2. Lottery based 3D NoC.
port according to the request and demand. In order to customize and get used to the present state, the NoC is accepted whenever the communication traffic changes. The run-time configuration or priority reconfiguration function is to be built inside the NoC hardware. The different communication priorities are very difficult to implement to the hardware relocation like buffer size, bandwidth, interconnecting wires etc. The priority reconfiguration value of different requests is done by the use of software in the lottery arbiter. This approach will have a significant advantage in the future of dynamic reconfiguration of NoC [10,11]. This proposed arbiter does not have extra buffer for the heavy communication port and solves the starvation problem in fixed priority arbiter. In 3D lottery arbiter algorithm, each requested port gains the lottery number according to its current priority (based on current situation). If more than one port submit simultaneously requests to acess a particular port, the lottery arbiter uses priority probability i.e. the lottery value (threshold value of each port according to its priority) which was generated through the lottery generator. The random number generator will produce an arbitrary number which is accolade lottery. The arbitrary number compares the threshold value of each port and confirms the ports which win the accolade. The arbiter then sends the acknowledgment signal after verifying the grant signal of the input ports and the status of the output buffer. If the output buffer is full, the acknowledgment signal is deemed invalid and the data of the input port is not transmitted to the output buffer. The arbiter invalids the current accolade and generates another arbitrary number through random generator block. Let us assume r1 , r2 , r3 , ..........rn represents the request of each port. If ‘i’ port is requesting the arbitration then the corresponding ri = 1, otherwise ri is assigned as ‘0’. l1 , l2 , l3 , .......ln are the lottery number of the port according to the communication priorities. The response probability is calculated as per the Eq. (1)
ri li P (Ci ) = n j=1
(1)
r jl j
Let us assume L is the intact quantity of lottery and each port threshold significance is obtained using Eq. (2)
T hreshold = P (Ci ) ∗ L +
i−1 j=1
P (C j ) ∗ L
(2)
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Fig. 3. The micro-architecture of NoC router.
The proposed lottery algorithm operates in two modes; inconsistent and determined totality number. In the inconsistent approach, the totality number L is obtained by the following formula;
L=
ri ∗ li
(3)
In the predetermined, L which is the totality number lottery is constant, but the threshold significance is varied. The arbiter generates a threshold rate depending on the precedence rate of each port when there is a call from a port. The arbitrary number generator generates a random number [1, L] and it is compared with the threshold of each port to make sure which request is granted. For example, If the arbitrary number be on [threshold E, threshold W], the port W will gain the grand while the other ports request are discarded. Fig. 3 shows the micro-architecture of the NoC router: Lottery arbiter routing algorithm p: number of IPCs per router request(req): IPC requests of each grant (gnt): IPC grants for each t: index time begin lottery scheduler assign j = 1 // grant initialization for i=0 to p-1 do { gnt(i) = 0 // initially all grant is zero end } While j > t do loop { N = random generator(); for i=1 to p-1 do { if (req(i)=1) then if (N > threshold (i)) then gnt(i) = 1 exit end end } end // Increment time slot j=j+1 end } end loop end lottery scheduler
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Fig. 4. Architecture of lottery arbiter.
Fig. 4 shows architecture developed for lottery arbiter routing algorithm as explained above. 4. Performance simulation The micro-architecture of the 3D lottery router is implemented using VHDL and the proposed design is coded and simulated. Fig. 5 represents the simulation result of lottery router. The performance results of the proposed architecture which considers six input ports and one output port are shown in Fig. 6 through the RTL View. The six input port has the same data injection rate and sends the data to the one output port. The six input ports which are South, Local, East,West, Up and Down port and the North port, are assigned as output ports. Exploitation rate and arbitral recital of the anticipated route is usually compared with RR router. In the Round Robin arbitral mechanism, the exploitation pace is similar to all input ports. Advantages of the three dimensional integration are mainly due to vertical interconnects, i.e., TSV. They also incur overheads hence unlimited TSVs cannot be afforded. Optimization of TSV to save on area without sacrificing the performance is needed, thus the optimization of 3D NoC is carried out by optimizing the number of vertical links using the algorithms Genetic Algorithm (GA). Since GA has robust latency compared to other optimization, the latency decreases as the number of vertical links increase due to the fact that there are shorter paths for the packets to travel from the source to destination. In the RR arbiter, each input port inhabits the output port irrespective of data inoculation rate and the priorities of diverse packets are not renowned. The RR arbiter algorithm [9] treats low priority packets and high priority packets alike. The high priority packets enters in the North port and the utilization rate is similar to other ports. In the proposed 3D lottery intercession mechanism, high precedence packets will gain more tickets and will get high communication priorities. In this example, the north input port is assigned as the higher priority port. Fig. 7 shows the utilization rate of six input ports using the Round-Robin arbiter exigent for one output port. From this simulation, we can effortlessly recognize that all input ports averagely maintain in the output when the data inoculation rate is small (0.10, 0.15 and 0.16). In the lower data inoculation rate there is no conflict and there is still some inactive time left. In the above cases, all input ports transmit the data successfully to the output port regardless of the port priority. For higher data input rates, the lottery arbiter does not persuade all input ports data transmission. Fig. 8 shows that the utilization rate of six input ports using the Round-Robin arbiter competing for one output port. The proposed 3D lottery arbiter is able to discriminate the priority of the dissimilar packets and make sure that precedence packets are transmitted first towards the output port at a high communication rate. The proposed 3D lottery arbiter is compiled using VHDL hardware description language and is implemented using Xilinx FPGA. Table 1 shows the Device utilization summary of 3D lottery arbiter architecture. The area and power of a NoC router are evaluated based on the implementation results. Table 2 shows the total router area comprising of the including and excluding area taken by vertical links. The area of the router with inductive or ca-
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Fig. 5. Simulation result of lottery router.
Table 1 Device utilization (Selected device: 3s500eft256-5). Sl.No
Description
Used
Available
% of Utilization
1 2 3 4 5 6 7
Number of slices Number of slice flip flops Number of 4 input LUTs Number used as logic Number used as RAMs Number of bonded IOBs Maximum frequency of operation
1644 1017 2777 2369 408 92 103.602 MHz
4656 9312 9312
35% 10% 29%
190
48%
Table 2 Comparison of power and area of NoC and interconnect. No of layer
Area of NoC (um2 )
Area of interconnect (um2 )
Total area
The Power of NoC (mw)
Power of interconnect (mw)
Total power (mw)
1 2 4
52,324 53,231 55,045
8523 2457 923
60,847 55,688 55,968
0.5217 0.5255 0.5298
0.0712 0.0112 0.0092
0.5929 0.5367 0.539
pacitive links using serialization is only 1.1 times larger than the router with TSV for pitches not larger than 100 um. In this section, inductive/capacitive coupling vertical links are evaluated using the simulator in the context of a 3D NoC. In the simulator, we model a 2-Tier, 8-Core 3D CMP with a shared L2 cache distributed into 8 banks. These 16 nodes are interconnected by a 3D NoC configured as a 3D MESH (2 × 2 by 2 layers). The area and power of proposed NoC are stated in Table 2, for ST Micro 180 nm technology and 5 GHz frequency. The whole CMP (processor, cache, NoC) is clocked at 1.5 GHz.
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Fig. 6. RTL view of lottery algorithm.
Fig. 7. Port utilization of Round-Robin arbiters for various injection rates.
Fig. 9 shows a comparison of the area occupied by the NoC and interconnects for various number of layers. From the comparison chart, the area occupation of 3D Noc decreases to a maximum of 80% when there are four layers while the total area slightly increases (around 10% of 1D NoC) due to additional unit of 3D Noc Control unit. The result shows that the area of the interconnects drastically reduces with gradual increment of the NoC area due to data transfer transceivers. Fig. 10 shows the comparison of the power consumed by the NoC and interconnect for various number of layers. In 3D, the congestion of interconnect is reduced by increasing the number of layers thus reduces the power consumtion of interconnect layers by 70% comparing to 1D interconnect layer. The result shows that the power consumption of the interconnect drastically reduces with the slight increment of NoC power due to data transfer transceivers block. Power consumption reduces by 9% when the NoC has four layers. The area and power consumption of the other routing algothims are shown in Table 3. The table shows that the results obtained for lottery based NoC gives better area utilization and power consumption.
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Fig. 8. Port utilization of lottery arbiter for various injection rates.
Fig. 9. Comparison charts for area utilization of loterry router in different layers.
Fig. 10. Comparison charts for power consumption of loterry router in different layers.
Table 3 Area and power comparison of various routing algorithm. Algorithm used in 3D NoC (2 layer)
Area of NoC (um2)
Area of interconnect (um2)
Total area (um2)
Power of NoC (mw)
Power of interconnect (mw)
Total power (mw)
Dimension order XYZ routing algorithm Diagonal fault-tolerant routing algorithm Look ahead XYZ routing algorithm Lottery based routing algorithm
55,492 56,413 54,456 53,231
2784 2684 2638 2457
58,276 59,097 57,094 55,688
0.5841 0.5958 0.6258 0.5255
0.0196 0.0185 0.0238 0.0112
0.6037 0.6143 0.6496 0.5367
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Fig. 11. Comparison charts for power consumption of various routing algorithm.
Fig. 12. Comparison charts for power consumption of various routing algorithm.
Figs. 11 and 12 shows the comparison chart for area and power consumption for various routing algorithms. The chart clearly shows that the loterry based routing algorithm consumes less area and power consumption compared with other routing algorithms. 5. Conclusion Lottery arbitral mechanism for the 3D NoC router architecture is proposed and implemented. Different communications has different priorities and is based on the applications, the projected algorithm to constitute the priority of dissimilar port is implemented. Further, we proposed micro-architecture for the 3D lottery router and we introduced the function of lottery arbiter. The output port exploitation space of dissimilar input port in the proposed 3D lottery mechanism is estimated with Round-Robin mechanism. The compared results reveal that the Lottery router can discriminate different communication priorities and promise the high priority packets to achieve supplementary network resources. In conclusion, 3D lottery NoC has better performance compared with other 3D-NoC. The 3D-NoC is modeled and implemented with Cadence EDA tools and the result shows that power consumption is reduced to 9% compared with a single layer. In future, lottery based routing algorithm can be implemented and analyzed in GALS lottery based routing algorithm by comparing the area, power and delay and design bundled-data asynchronous Network-on-Chip router. References [1] Benini L, De Micheli G. Networks on Chips: a new SoC paradigm. IEEE Comput 2002:70–8 Jan. [2] Ebrahimi Masoumeh, Chang Xin, Daneshtalab Masoud, Plosila Juha, Liljeberg Pasi, Tenhunen Hannu. In: Dy-xyz fully adaptive routing algorithm for 3D NoCs IEEE conference publications; 2013. p. 499–503. [3] Akrambenahmed Abderazekbenabdullah. Low latency high through put look-ahead routing algorithm for 3D Network-on-Chip (3D-NoC) architecture. In: IEEE conference publications; 2012. p. 167–74. [4] Akbari Sarah, Isvandi Maryam, Fathi Mahmod, Barangi Reza. Diagonal fault-tolerant routing algorithm for 3D multi-layer Networks-on-Chip IASBS, Zanjan, Iran; 2011 May 31-June 2. [5] Eung S. Shin, Vincent J. Mooney III, George F. Riley. Round-Robin arbiter design and generation. In: ISSS’02 october 2–4; 2002. [6] Jer-min jou, Yun-lung lee. An optimal Round-Robin arbiter design for NoC. J Inf Sci Eng 2010;26:2047–58. [7] Xiaopeng Gao, Zhe Zhang, Xiang Long. Round Robin arbiters for virtual channel router. In: IMACS multiconference on computational engineering in systems applications (CESA), October 4-6; 2006. [8] Chang Wu, Yubai Li, Song Chai, Zhongming Yang, Lottery router: a customized arbitral priority NoC router International conference on computer science and software engineering 978-0-7695-3336-0/08
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[9] Suyog KDahule, Gaikwad MA. Design & simulation of Round Robin Arbiter for NoC Architecture. Int J Eng Adv Technol 2012;1(6) (IJEAT+) ISSN:2249–8958 August. [10] Jian Wang, Yubai Li, Qicong Peng, Taiqiu Tan, A dynamic priority arbiter for Network-an-Chip IEEE transactions 978-1-4244-4110-5/09. [11] Neeta Doifode, Dinesh Padole, Dr. Preeti Bajaj, Dynamic lottery bus arbiter for shared bus system on chip: a design approach with VHDL, International conference on emerging trends in engineering and technology IEEE computer society 978-0-7695-3267-7/08. [12] Lahiri Kanishka, Raghunathan Anand, Lakshminarayana Ganesh. The LOTTERY BUS on-chip communication architecture. IEEE Trans Very Large Scale Integr (vlsi) Syst 2006;14(6) june. [13] Yan Ghidini, Thais Webber, Edson Moreno, Fernando Grando, Rubem Fagundes, César Marcon, Buffer depth and traffic influence on 3D NoCs performance IEEE Trans Very Large Scale Integr 978-1-4673-2789-3/12 [14] Chang Wu. Lottery router: a customized arbitral priority NoC router. In: International conference on computer science and soft ware engineering; 20 08 12/20 08. [15] Ebrahimi M, Chang Xin, Daneshtalab M, Plosila J, Liljeberg P, Tenhunen H. DyXYZ: fully adaptive routing algorithm for 3D NoCs. In: 2013 21st Euromicro international conference on parallel distributed and network- based processing; 2013. [16] Ben Ahmed Akram, Abderazek Ben Abdallah. Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC). J Supercomput 2013;66(3):1507–32. [17] de Paulo Vitor, Ababei Cristinel. 3D Network-on-Chip architectures using homogeneous meshes and heterogeneous floorplans. Int J Reconfigurable Comput 2010;2010 Article ID 603059, 12 pages. [18] Zhizhou Fu. The design and implementation of arbiters for Network- on- Chips. In: 2nd International conference on industrial and information systems, 07/2010; 2010. [19] Ahmed AkramBen, Abderazek Ben Abdallah. Low- overhead routing algorithm for 3D Network- on-Chip. In: Third international conference on networking and computing; 2012. p. 2012. [20] Warathe Kanchan. A design approach to AMBA (Advanced Microcontroller Bus Architecture) bus architecture with dynamic lottery arbiter. In: Annual IEEE India conference; 2009 12/2009. [21] Sweety A, Karthikeyan A, Jebasingh Kirubakaran SJ. Analysis and performance comparison of 3-D NoC routing algorithms. Int J Appl Eng Res 2015;10(5):13415–29. [22] Khan MA, Ansari AQ. Quadrant-based XYZ dimension order routing algorithm for 3-D Asymmetric Torus Routing Chip (ATRC). In: 2011 International conference on emerging trends in networks and computer communications (ETNCC), Udaipur; 2011. p. 121–4. [23] Ahmed AB, Abdallah AB. LA-XYZ: low latency, high throughput look-ahead routing algorithm for 3D Network-on-Chip (3D-NoC) architecture. In: 2012 IEEE 6th International symposium on embedded multicore SoCs, Aizu-Wakamatsu; 2012. p. 167–74. [24] Zhang Zhen, Serwe Wendelin, Wu Jian, Yoneda Tomohiro, Zheng Hao. Formal analysis of a fault-tolerant routing algorithm for a Network-on-Chip. In: 19th International conference on formal methods for industrial critical systems, FMICS2014, Sep, Florence, Italy. Springer; 2014 8718, pp.48-62, 20. [25] Valinataj Mojtaba, Mohammadi Siamak, Plosila Juha, Liljeberg Pasi, Tenhunen Hannu. A reconfigurable and adaptive routing method for fault-tolerant mesh-based networks-on-chip. Int J Electron Commun 2011;65:630–40.
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Karthikeyan Appathurai received the B.E., degree in Electronics and Communication from Manonmaniam Sundaranar University, Tirunelveli in 2004 and M.E., degree in Embedded System Technologies from Anna University, Chennai in 2007 and is currently working toward the Ph.D degree at Anna University, Chennai. His research interest includes Network on Chip. SenthilKumar Ponnusamy is currently working as Professor and Head of the Department of Information Technology, SKR Engineering College, Chennai. He received his ME in 2002 from Arulmigu Kalasalingam college of engineering, Krishnankovil and Ph.D in 2010 from Bharathiyar University, India. He has 18 years of experience in various engineering college. He has published more than 30 papers in various national and International journal and conferences. His area of research is network.