- Email: [email protected]
Reliability of a signal processing system
172
World Abstracts on Microelectronics and Reliability
Time-To-Repair (MTTR). A major defect in the prediction methodology currently in use (MIL-HDBK-472) is its failure to address and quantify maintenance task time increases attributable to unfavourable elements in the real-world environment. This paper discusses how environmental factors affect work efficiency and presents several empirical relationships which can be used to predict a fielded MTTR. An illustrative example is provided.
Performance and reliability analysis of a microcomputer pool. VON SIEGBERT HENTSCHKE and REIMUND MEIERL. Frequenz 37 (5), 123 (1983) (in German). Performance capacity and reliability are main objectives if microcomputers are applied for digital communication and switching systems. This article presents dimensioning rules for a microcomputer pool with redundancy which supports the optimal design of microcomputer systems requiring extreme reliability. Higher maintenance expense increases the reliability, but also the costs. With the aid of curves describing the system performance, basic structures are derived which fulfil the desired reliability and maintenance specifications. A software evaluation: results and recommendations. JAN M. HOWELL. Proc. A. Reliab. Maintainab. Syrup. 113 (1983). This paper discusses a software quality evaluation conducted on a major U.S. Air Force avionics system. The originally planned effort was limited to a hardware evaluation but was expanded to include software when the impact of software became apparent. The paper presents some results obtained, discusses pattern software problems encountered and suggests ways to avoid those repetitive difficulties. Significant subtleties of stress screening. HENRY CARUSO. Proc. A. Reliab. Maintainab. Syrup. 154 (1983). This paper examines three relatively unexplored areas of environmental stress screening of electronic hardware that will have a major effect on its effectiveness as a quality improvement process. (a) The environment that causes a failure and that which makes a flaw detectable are often different. Failure analyses have shown that many apparent temperature failures were in reality precipitated by vibration-induced stresses. (b) A significant number of failures are not "hard" failures that remain detectable after the environmental stress has been removed. Unless the performance of the hardware being screened is monitored continually while under stress, a large proportion of the detectable faults will escape the screening process. (c) To date, there has been an unwarranted emphasis on precisely specified input environmental stress conditions and relatively little emphasis upon hardware response to the environment. For screening to be predictably effective, the stress response of the hardware being screened must first be adequately characterized and understood. BIT analysis and design reliability. FLOYD J. KREUZE. Proc. A. Reliab. Maintainab. Syrup. 328 (1983). This paper begins with a brief description of what BIT is and what it is supposed to do. How BIT design requirements are stated is then explored. This sets the stage for a description of BIT design analysis and why it is needed. Proceeding logically to the FMEA-derived BIT analysis, a general description of the overall process is given along with a specific example--a typical digital AFCS servo loop. Attention is directed to assessing the impact of BIT failure on the parent AFCS equipment. This is done primarily to see how well the BIT design addresses the need to reduce this impact to a minimum. A general description of the overall process is followed by a specific example taken from experience in the design of digital AFCS equipment. These AFCS data are combined into a fault tree to produce a single figure of merit for the system. The problem of a newly-designed AFCS BIT required to interface with aircraft
equipment of an older design is explored briefly. Of particular interest to the reliability engineer, is the way BIT analysis activity makes effective use of F M E A and fault tree analysis techniques. The analysis depends heavily upon inputs from the reliability prediction for failure rates.
Development of a multiple intermittent fault testing strategy. RICHARD JAY SPILLMAN. Comput. Electl Engng 10 (1), 19 (1983). This paper examines the effects of multiple intermittent faults on an overall circuit testing procedure. Different testing strategies are developed which depend on ,~., the rate of intermittent fault activity. In addition, the effects of masking intermittent faults in redundant circuits are explored. A fault-tolerant system architecture for Navy applications. WESB T. COMFORT.IBM Jl Res. Det,. 27 (3), 219 (1983). This paper describes the architecture of a computer system, being designed and built for the U.S. Navy, that is expected to be the standard Navy shipboard computer for the next twenty years or so. It has a requirement for very high system reliability, which is addressed by a multiprocessor system configuration that can recover dynamically from hardware faults and support on-line repair of failed hardware elements. Successfully accomplishing this requires various types of redundant hardware elements and special system architecture features, as well as intelligent fault-recovery software. This also requires that the application programs be designed to participate fully in the recovery and reconfiguration process. This paper presents the overall system architecture and discusses a number of significant new features designed to support fault-tolerant operation, including a duplex control bus, a computer interconnection system, a technique for remote diagnostics, a single-button maintenance procedure, and speciat fault-handling software. Minimizing the average cost of testing coherent systems: complexity and approximate algorithms. PIOTR JI~DRZEJOWICZ IEEE Trans. Reliab. R-32 (1), 66 (1983). The paper deals with the problem of finding optimal testing policy to minimize the average cost of determining the state of a s-coherent system. Computational complexity of this problem is analysed and strong evidence presented that an exact, polynomial-time, algorithm is very unlikely to exist. Instead, three approximate algorithms having polynomial running times are suggested and evaluated. Two of them guarantee reasonably good solutions and might be practical. Reliability of a signal processing system. STEVENS. TUNG. Proc. A. Reliab. Maintainab. Syrup. 95 (1983). This paper presents a mathematical model to evaluate the reliability of a complex infrared (IR) signal processing system. Furthermore, this paper demonstrates the importance of using heuristic methods and algorithms in conjunction with classical reliability theory and combinatorial analysis techniques to solve a complex reliability mathematical modelling problem. To facilitate building of the model, an algorithm for combinatorial analysis has been devised and a computer program written. Copies of the computer program can be obtained upon request. These mathematical models and the approaches used should he useful to reliability engineers and statisticians. The application of a life cycle cost model to modular electronic systems. A. DAVIES and K. J. SKINNER. J. Br. lnstn Radio Engrs 53 (5), 209 (1983). The widespread use of modular construction in the electronic equipment industry has resulted in the development of standard electronic modules (SEMs). These units are an extension of the original modular partitioning concept, and are designed for universal use, being interchangeable between different items of SEM equipment. They are highly reliable functional modules which may be discarded on failure, and are designed to be independent of
World Abstracts on Microelectronics and Reliability
Time-To-Repair (MTTR). A major defect in the prediction methodology currently in use (MIL-HDBK-472) is its failure to address and quantify maintenance task time increases attributable to unfavourable elements in the real-world environment. This paper discusses how environmental factors affect work efficiency and presents several empirical relationships which can be used to predict a fielded MTTR. An illustrative example is provided.
Performance and reliability analysis of a microcomputer pool. VON SIEGBERT HENTSCHKE and REIMUND MEIERL. Frequenz 37 (5), 123 (1983) (in German). Performance capacity and reliability are main objectives if microcomputers are applied for digital communication and switching systems. This article presents dimensioning rules for a microcomputer pool with redundancy which supports the optimal design of microcomputer systems requiring extreme reliability. Higher maintenance expense increases the reliability, but also the costs. With the aid of curves describing the system performance, basic structures are derived which fulfil the desired reliability and maintenance specifications. A software evaluation: results and recommendations. JAN M. HOWELL. Proc. A. Reliab. Maintainab. Syrup. 113 (1983). This paper discusses a software quality evaluation conducted on a major U.S. Air Force avionics system. The originally planned effort was limited to a hardware evaluation but was expanded to include software when the impact of software became apparent. The paper presents some results obtained, discusses pattern software problems encountered and suggests ways to avoid those repetitive difficulties. Significant subtleties of stress screening. HENRY CARUSO. Proc. A. Reliab. Maintainab. Syrup. 154 (1983). This paper examines three relatively unexplored areas of environmental stress screening of electronic hardware that will have a major effect on its effectiveness as a quality improvement process. (a) The environment that causes a failure and that which makes a flaw detectable are often different. Failure analyses have shown that many apparent temperature failures were in reality precipitated by vibration-induced stresses. (b) A significant number of failures are not "hard" failures that remain detectable after the environmental stress has been removed. Unless the performance of the hardware being screened is monitored continually while under stress, a large proportion of the detectable faults will escape the screening process. (c) To date, there has been an unwarranted emphasis on precisely specified input environmental stress conditions and relatively little emphasis upon hardware response to the environment. For screening to be predictably effective, the stress response of the hardware being screened must first be adequately characterized and understood. BIT analysis and design reliability. FLOYD J. KREUZE. Proc. A. Reliab. Maintainab. Syrup. 328 (1983). This paper begins with a brief description of what BIT is and what it is supposed to do. How BIT design requirements are stated is then explored. This sets the stage for a description of BIT design analysis and why it is needed. Proceeding logically to the FMEA-derived BIT analysis, a general description of the overall process is given along with a specific example--a typical digital AFCS servo loop. Attention is directed to assessing the impact of BIT failure on the parent AFCS equipment. This is done primarily to see how well the BIT design addresses the need to reduce this impact to a minimum. A general description of the overall process is followed by a specific example taken from experience in the design of digital AFCS equipment. These AFCS data are combined into a fault tree to produce a single figure of merit for the system. The problem of a newly-designed AFCS BIT required to interface with aircraft
equipment of an older design is explored briefly. Of particular interest to the reliability engineer, is the way BIT analysis activity makes effective use of F M E A and fault tree analysis techniques. The analysis depends heavily upon inputs from the reliability prediction for failure rates.
Development of a multiple intermittent fault testing strategy. RICHARD JAY SPILLMAN. Comput. Electl Engng 10 (1), 19 (1983). This paper examines the effects of multiple intermittent faults on an overall circuit testing procedure. Different testing strategies are developed which depend on ,~., the rate of intermittent fault activity. In addition, the effects of masking intermittent faults in redundant circuits are explored. A fault-tolerant system architecture for Navy applications. WESB T. COMFORT.IBM Jl Res. Det,. 27 (3), 219 (1983). This paper describes the architecture of a computer system, being designed and built for the U.S. Navy, that is expected to be the standard Navy shipboard computer for the next twenty years or so. It has a requirement for very high system reliability, which is addressed by a multiprocessor system configuration that can recover dynamically from hardware faults and support on-line repair of failed hardware elements. Successfully accomplishing this requires various types of redundant hardware elements and special system architecture features, as well as intelligent fault-recovery software. This also requires that the application programs be designed to participate fully in the recovery and reconfiguration process. This paper presents the overall system architecture and discusses a number of significant new features designed to support fault-tolerant operation, including a duplex control bus, a computer interconnection system, a technique for remote diagnostics, a single-button maintenance procedure, and speciat fault-handling software. Minimizing the average cost of testing coherent systems: complexity and approximate algorithms. PIOTR JI~DRZEJOWICZ IEEE Trans. Reliab. R-32 (1), 66 (1983). The paper deals with the problem of finding optimal testing policy to minimize the average cost of determining the state of a s-coherent system. Computational complexity of this problem is analysed and strong evidence presented that an exact, polynomial-time, algorithm is very unlikely to exist. Instead, three approximate algorithms having polynomial running times are suggested and evaluated. Two of them guarantee reasonably good solutions and might be practical. Reliability of a signal processing system. STEVENS. TUNG. Proc. A. Reliab. Maintainab. Syrup. 95 (1983). This paper presents a mathematical model to evaluate the reliability of a complex infrared (IR) signal processing system. Furthermore, this paper demonstrates the importance of using heuristic methods and algorithms in conjunction with classical reliability theory and combinatorial analysis techniques to solve a complex reliability mathematical modelling problem. To facilitate building of the model, an algorithm for combinatorial analysis has been devised and a computer program written. Copies of the computer program can be obtained upon request. These mathematical models and the approaches used should he useful to reliability engineers and statisticians. The application of a life cycle cost model to modular electronic systems. A. DAVIES and K. J. SKINNER. J. Br. lnstn Radio Engrs 53 (5), 209 (1983). The widespread use of modular construction in the electronic equipment industry has resulted in the development of standard electronic modules (SEMs). These units are an extension of the original modular partitioning concept, and are designed for universal use, being interchangeable between different items of SEM equipment. They are highly reliable functional modules which may be discarded on failure, and are designed to be independent of