- Email: [email protected]
s digital coherent systems
Optical Fiber Technology 17 (2011) 452–455
Contents lists available at SciVerse ScienceDirect
Optical Fiber Technology www.elsevier.com/locate/yofte
Invited Papers
Soft-decision forward error correction for 100 Gb/s digital coherent systems Kiyoshi Onohara ⇑, Takashi Sugihara, Yoshikuni Miyata, Kenya Sugihara, Kazuo Kubo, Hideo Yoshida, Kazuumi Koguchi, Takashi Mizuochi Mitsubishi Electric Corporation, 5-1-1 Ofuna, Kamakura, Kanagawa 247-8501, Japan
a r t i c l e
i n f o
Article history: Available online 19 October 2011 Keywords: Error correction coding Field programmable gate arrays Forward error correction Optical communication Parallel processing
a b s t r a c t Soft-decision forward error correction (SD-FEC) and its practical implementation for 100 Gb/s digital coherent systems are discussed. In applying SD-FEC to a digital coherent transponder, the configuration of the frame structure of the FEC becomes a key issue. We present a triple-concatenated FEC, with a pair of concatenated hard-decision FEC (HD-FEC) further concatenated with an SD-based low-density paritycheck (LDPC) code for 20.5% redundancy. In order to evaluate error correcting performance of SD-based LDPC code. We implement the entire 100 Gb/s throughput of LDPC code on field programmable gate arrays (FPGAs) based hardware emulator. The proposed triple-concatenated FEC can achieve a Q-limit of 6.4 dB and a net coding gain (NCG) of 10.8 dB at a post-FEC bit error ratio (BER) of 1015 is expected. In addition, we raise an important question for the definition of NCG in digital coherent systems with and without differential quadrature phase-shift keying (QPSK) coding, which is generally used to avoid phase slip caused by the practical limitations in processing the phase recovery algorithms. Ó 2011 Elsevier Inc. All rights reserved.
1. Introduction The transmission distance and speed in optical communications are primarily limited by optical signal-to-noise ratio (OSNR) and waveform distortion. The well established adaptive equalization algorithms being deployed with recent digital coherent technologies make possible a drastic improvement in the waveform distortion. However, no matter how good the equalization performance may be, it is never possible to restore the received OSNR once it has been degraded. Moreover, as the level of an M-ary modulation scheme increases, greater OSNR is required because the decreased Euclidean distance between each signal point in the constellation makes it more difficult to distinguish between the states. Only FEC can compensate significantly for low OSNR. Addressing this issue is prompting an increasing demand for powerful FEC to reduce the required OSNR. Recently, several trials aimed at exceeding an NCG of 10 dB have been initiated. Chan et al. proposed a continuously interleaved BCH code having an NCG of 9.35 dB with 7% redundancy [1]. This is considered to be one of the best performing hard decision FECs for optical communications. On the other hand, soft-decision is a promising way to improve the error correction capability effectively. SD-FEC uses not just the conventional ‘1’ vs. ‘0’ decision but also an indication of how certain we are that the decision is correct. Although it needs to calculate the maximum ⇑ Corresponding author. Fax: +81 467 41 2519. E-mail address: [email protected] (K. Onohara). 1068-5200/$ - see front matter Ó 2011 Elsevier Inc. All rights reserved. doi:10.1016/j.yofte.2011.09.005
a posteriori probability (MAP) for the additive white Gaussian noise (AWGN) channel, we can get more 2 dB coding gain in theory compared to HD-FECs. Thanks to the advent of digital signal processing (DSP) LSIs and high performance analog-to-digital converters (ADC) such as sampling rate of 56 Gs/s, signal bandwidth of 15 GHz, and resolution of 6 bits or more for digital coherent systems [2], SD-FEC becomes much easier to incorporate into the receiver hardware. In response to this trend, Miyata et al. proposed SD-based triple-concatenated FEC using LDPC codes with an NCG of 10.8 dB at 20.5% redundancy [3]. Yu et al. presented an SD-based LDPC(18353, 15296) code with an NCG of 11.28 dB at 20% redundancy [4]. A longer codeword brings with it increased NCG and also prevents any undesired error flaring floor. In this paper, we discuss how SD-FEC is becoming practical in digital coherent receivers using high speed ADCs. LDPC codes are introduced as good candidates for strong SD-FEC. Several implementations of SD-based LDPC codes are considered for 100 Gb/s transmission, where error floor is a critical issue needing to be addressed. To overcome this, the concatenation of HD-FEC and SD-based LDPC codes is proposed to achieve more than 10 dB NCG compliant with Optical Internetworking Forum (OIF) standards. In addition, we evaluate error correcting performance by implementing the entire 100 Gb/s throughput of LDPC code on FPGA-based hardware emulator. In the last part, we raise an important question for the definition of NCG in digital coherent systems with and without differential QPSK coding, which is generally used to avoid phase slip caused by the practical limitations in processing the phase recovery algorithms.
K. Onohara et al. / Optical Fiber Technology 17 (2011) 452–455
Note that the NCGs presented in this paper are defined at a post-FEC bit error ratio (BER) of 1015. 2. Soft-decision FEC Soft-decision decoding uses not just the conventional ‘1’ vs. ‘0’ decision but also an indication of how certain we are that the decision is correct. Fig. 1 illustrates a typical soft-decision structure for a QPSK constellation. The 2N 1 decision thresholds sandwiched between the two signal states of the in-phase and quadrature phase components are used for soft-decision decoding. In the case of N = 3, the two possible received signals, ‘1’ and ‘0’, lie in regions represented by a binary vector ranging from [0 1 1] to [1 1 1]. The left-most bit is the hard-decision digit, and the other two digits are information bits indicating the probability of ‘1’ or ‘0’. Conveniently, a recent digital coherent receiver has an ADC at its front end for demodulating the multi-level coded signals. This suddenly makes it much easier to realize soft-decision decoding, even though the bit rate is much higher than previously. The coding gain can in principle be improved by p/2 by using soft-decision decoding with infinite quantization bits N and redundancy, an approximately 2 dB difference. In a practical implementation of QPSK, an N of 3 or 4 is sufficient to obtain near ideal error correction performance. 3. LDPC codes For 100 Gb/s optical communications, one potential candidate for strong SD-FEC is an LDPC code, a linear code defined by the sparse parity-check matrix invented by Gallager, which is expected to exhibit superior error correcting performance. Studies into applying LDPC codes to optical communications were instituted as early as 1999 by Djordjevic et al. [5]. The expected merits of LDPC codes are not confined to high error correction capability, but also fit them for parallelization to reduce circuit complexity. In an LSI for high speed optical communications, ease of parallelized signal processing is essential for practical implementation. Fig. 2 illustrates four types of FEC frame structure and associated transponder configuration for a 100 Gb/s digital coherent system, which each consist of an OTU4 framer LSI, a coherent ASIC and an optical front-end. The FEC redundancy is assumed to be 20% as recommended by the OIF. The OTU4 framer LSI transforms the 100GbE signal to and from the OTU4 framed format, and usually incorporates a hard-decision FEC, e.g. RS(255, 239) or concatenated codes compliant with ITU-T G.975.1. The coherent ASIC includes an ADC and DSP
In-phase p.d.f.
Soft decision threshold
Quadrature-phase p.d.f.
Soft decision threshold Fig. 1. Typical 3-bit soft decision for QPSK signal.
453
for received signal quantization, dispersion compensation, phase estimation, clock recovery, polarization de-multiplexing, and adaptive equalization of waveform distortion due to polarization mode dispersion. In Fig. 2a and b a single 20% LDPC code is implemented in respectively the OTU4 framer or the coherent ASIC. It is expected that the 20% redundancy of the LDPC code will provide superior error correction performance. However, in order to suppress the undesired error floor which is inherent to LDPC codes, a very long codeword is required. This results in a large circuit and high latency. Fig. 2a has the drawback that a huge interconnection speed at N + 1 times the transmission rate is needed between the OTU4 framer LSI and the coherent ASIC, e.g. for N = 3, a 125 Gb/s 4 = 500 Gb/s interconnection is required. Fig. 2c shows another way to easily eliminate the LDPC code error floor. The error floor of the inner SD-FEC in the coherent ASIC is suppressed by concatenating it with a weak 3% outer HD-FEC code. Under this concept, the concatenation of LDPC(9216, 7936) and RS(992, 956) codes has been experimentally demonstrated to show an NCG of 9.7 dB (=9.0 dB at 1013) with only 2-bit soft-decision and four iterations [6]. Fig. 2d is thought to be the most practical implementation. An SD-FEC with a relatively short codeword and small circuit is implemented in the coherent ASIC as the inner code, concentrating on the higher BER (>103) region. The inevitable increase in the residual BER floor is cleaned up by the concatenated HD-FEC compliant with ITU-T G.975.1 in the OTU4 framer LSI. This concept was given the name ‘‘triple-concatenated FEC’’ [2]. 4. Evaluation of SD-FEC performance by FPGA based hardware emulation We evaluated the error correcting performance by implementing the entire 100 Gb/s throughput of LDPC(4608, 4080) code (13% redundancy) on an FPGA based hardware emulator (Mentor Graphics, Veloce). Hardware emulations enable us to save time drastically due to higher speed processing than software simulations and evaluate the error floor at the low BER region. The clock frequency was 556 kHz. We evaluated 204.8 million codewords in 7.4 h. Fig. 3 shows the FEC performance where the vertical axis is post-FEC BER and the horizontal axis is pre-FEC Q represented in dB. A blue solid line shows the results of an LDPC code, and a red solid line shows those of triple-concatenated FEC by software simulation we have reported [3]. Red circles show the results of an LDPC code by hardware emulation. It is clearly shown that the results of LDPC code by hardware emulation are consistent with those by software simulation. From these results, we can expect that an NCG of the LDPC code concatenated with EFEC compliant with ITU-T G.975.1 was 10.8 dB at a BER of 1015. If we implement the proposed FEC in a 40–45 nm class CMOS technology LSI with 512-parallel processing and a 250 MHz clock, the frame cycle is estimated to be 1.2 ls. The latency for decoding LDPC codes with EFEC is estimated to be less than 10 ls even for 16 iterations. 5. SD-FEC in differential QPSK and other modulation formats In digital coherent transmissions, realistic linewidth, additive noise, and undesired nonlinearity interaction cause catastrophic failure due to cycle slips more often than expected [7]. The phase estimate becomes incorrect over a quarter cycle, and stays wrong indefinitely. When a cycle slip occurs, at least one OTU frame (4080 8 4 bits) is lost. In order for the burst error correction capability of the FEC to be able to recover this, an impossible interleaving depth of at least 100 OTU frames would be necessary. Instead, differential QPSK is usually employed, in which a cycle slip causes 2 consecutive errored bits. The BER of differentially encoded
K. Onohara et al. / Optical Fiber Technology 17 (2011) 452–455
3% HD-FEC
(d) 13% SD-FEC concatenated with 7% HD-FEC (Triple concatenated codes) 13% LDPC 7% concatenated HD-FEC
Payload
E/O O/E E/O
ADC/DSP ADC/DSP
20% SD-FEC
O/E E/O O/E
Payload
13% SD-FEC
17% LDPC
3% HD-FEC
(c) SD-FEC concatenated with 3% HD-FEC
E/O
Not Used Not Used 7% HD-FEC
20% LDPC
Payload
Optics
O/E
100GbE/OTU4 100GbE/OTU4 100GbE/OTU4 100GbE/OTU4
(b) Single SD-FEC in coherent ASIC
20% SD-FEC
100GbE 100GbE 100GbE 100GbE
20% LDPC
Payload
Coherent ASIC
ADC/DSP
OTU4 framer
ADC/DSP
OTU4V frame structure
(a) Single SD-FEC in OTU4 framer
17% SD-FEC
454
Fig. 2. Four types of FEC frame structure and optical transponder for a 100 Gb/s digital coherent system.
Uncoded (Theoretical)
10-1
Post-FEC BER
10-3
Channel FEC ENC
LDPC H/W Emulation
10-5 10-7
(a) QPSK Channel
LDPC Simulation
10-9
FEC Diff ENC ENC
10-11 Triple-concatenated FEC
10-13 10-15
FEC DEC
5
5.5
6
6.5
7
7.5
8
8.5
Diff FEC DEC DEC
(b) Differential QPSK 9
Qin’=Qin
Qin’ Qin
Fig. 4. Simplified block diagrams of (a) QPSK and (b) differential QPSK.
Pre-FEC Q (dB) Fig. 3. FEC performance by implementing the entire 100 Gb/s throughput of LDPC(4608, 4080).
QPSK is 2p(1 p), where p is the error probability of synchronous detection QPSK, which is equivalent to an OSNR penalty of 1.1 dB at around 102. Fig. 4 shows simplified block diagrams for (a) QPSK and (b) differential QPSK. The received Q can be defined at two points. Qin is the FEC decoder input Q. Most systems are defined in terms of this. The input Q of a differential decoder is Qin0 . Most optical engineers consider this point to be the receiver input. Note that the definition of Q here is a simple conversion from BER using complementary error function (erfc). Fig. 5 illustrates the difference in FEC performance of QPSK and differential QPSK. The SD-FEC is assumed to be the
triple-concatenated FEC using LDPC codes type [2]. The Q difference between uncoded QPSK and uncoded differential QPSK is just 0.09 dB at 1015. With decreasing Qin0 , the difference widens, e.g. to 1.07 dB at 2 102. The NCG for QPSK is calculated to be 18 dB 6.4 dB + 10log(1/1.2) = 10.8 dB. In contrast, the NCG of differential QPSK appears to be 18 dB 6.4 dB 1.07 dB + 0.09 dB + 10log(1/1.2) = 9.8 dB. Is the NCG really degraded? The answer is no. The reason why the NCG looks degraded is that the Qin0 difference between QPSK and differential QPSK is different at different corrected BERs, e.g. 0.09 dB at 1015 and 1.07 dB at 2 102. The inherent performance of the FEC will not be degraded as long as the FEC can correct up to 4-bit short bursts. When trying to design a system power budget to ITU-T G.977, the 1.07 dB degradation due to differential coding should be
K. Onohara et al. / Optical Fiber Technology 17 (2011) 452–455
1.07dB
10-1
2x10-2
Uncoded Differential QPSK
10-3 Corrected BER
10-5
Uncoded QPSK
10-7
QPSK with SD-FEC
10-9
Differential QPSK with SD-FEC
10-11
NCG =10.8dB
10-13 10-15 10-17
0.09dB =9.8dB? 10-15
5
6
7
8
6.4dB 7.5dB
9
10 11 12 13 14 15 16 17 18 19 Qin’(dB)
Fig. 5. Soft decision FEC performance of QPSK and differential QPSK.
included in the mean Q value (in Fig. 4, use Qin not Qin0 ). A Q limit of 6.4 dB should always be used. SD-FEC is applicable other modulation formats such as m-QAM, and optical frequency division multiplexing (OFDM). However as the level of an M-ary modulation increases, the higher resolution of ADC is needed. For example, OSNR penalty of 16-QAM is ignorable when ADC resolution is higher than 6 bits [8]. Therefore, we need more than 9 bits of ADC resolution is needed for 3-bit SD-FEC into 16-QAM format. 6. Conclusions We reviewed recent progress in SD-FEC for optical communications. LDPC codes are expected to be strong candidates for SD-FECs.
455
We showed and compared four ways of implementing LDPC codes in OTU4 framer LSIs and coherent ASICs. A triple-concatenated FEC is introduced as one of the strongest SD-FECs for 100 Gb/s transmission. We have verified error correcting performance by implementing the entire 100 Gb/s throughput of LDPC(4608, 4080) code on an FPGA based hardware emulator. It has been clearly shown that the results by hardware emulation were consistent with those by software simulation. We expect that an NCG of the LDPC code concatenated with EFEC was 10.8 dB at a BER of 1015. In addition, we discussed the definition of NCG in digital coherent systems with and without differential coding, which latter is generally used to avoid phase slip caused by the practical limitations in processing the phase recovery algorithms. References [1] F. Chang, K. Onohara, T. Mizuochi, IEEE Commun. Mag. 48 (3) (2010) 48–55. [2] B. Germann, I. Dedic, in: OSA SPPCom2010, SPTuC2, Karlsruhe, Germany, 2010. [3] Y. Miyata, K. Sugihara, W. Matsumoto, K. Onohara, T. Sugihara, K. Kubo, H. Yoshida, T. Mizuochi, in: OFC/NFOEC2010, OThL3, San Diego, CA, 2010. [4] F. Yu, C. Xie, L. Zeng, F. Chang, T. Coe, J. Dillard, Presented at ECOC2010, WS11 Workshop, Torino, Italy, 2010. [5] I.B. Djordjevic, M. Arabaci, L.L. Minkov, Next generation FEC for high-capacity communication in optical transport networks, IEEE J. Lightw. Technol 27 (16) (2009) 3518–3530. [6] T. Mizuochi, Y. Konishi, Y. Miyata, T. Inoue, K. Onohara, S. Kametani, T. Sugihara, K. Kubo, H. Yoshida, T. Kobayashi, T. Ichikawa, Experimental demonstration of concatenated LDPC and RS codes by FPGAs emulation, IEEE Photon. Technol. Lett. 21 (18) (2009) 1302–1304. [7] E. Ibragimov, B. Zhang, T.J. Schmidt, C. Malouin, N. Fediakine, H. Jiang, Cycle slip probability in 100G PM-QPSK systems, in: OFC/NFOEC2010, OWE2, San Diego, CA, 2010. [8] P.J. Winzer, A.H. Gnauck, C.R. Doerr, M. Magarini, L.L. Buhl, Spectrally efficient long-haul optical networking using 112-Gb/s polarization-multiplexed 16QAM, IEEE J. Lightw. Technol 28 (4) (2010) 547–556.
Contents lists available at SciVerse ScienceDirect
Optical Fiber Technology www.elsevier.com/locate/yofte
Invited Papers
Soft-decision forward error correction for 100 Gb/s digital coherent systems Kiyoshi Onohara ⇑, Takashi Sugihara, Yoshikuni Miyata, Kenya Sugihara, Kazuo Kubo, Hideo Yoshida, Kazuumi Koguchi, Takashi Mizuochi Mitsubishi Electric Corporation, 5-1-1 Ofuna, Kamakura, Kanagawa 247-8501, Japan
a r t i c l e
i n f o
Article history: Available online 19 October 2011 Keywords: Error correction coding Field programmable gate arrays Forward error correction Optical communication Parallel processing
a b s t r a c t Soft-decision forward error correction (SD-FEC) and its practical implementation for 100 Gb/s digital coherent systems are discussed. In applying SD-FEC to a digital coherent transponder, the configuration of the frame structure of the FEC becomes a key issue. We present a triple-concatenated FEC, with a pair of concatenated hard-decision FEC (HD-FEC) further concatenated with an SD-based low-density paritycheck (LDPC) code for 20.5% redundancy. In order to evaluate error correcting performance of SD-based LDPC code. We implement the entire 100 Gb/s throughput of LDPC code on field programmable gate arrays (FPGAs) based hardware emulator. The proposed triple-concatenated FEC can achieve a Q-limit of 6.4 dB and a net coding gain (NCG) of 10.8 dB at a post-FEC bit error ratio (BER) of 1015 is expected. In addition, we raise an important question for the definition of NCG in digital coherent systems with and without differential quadrature phase-shift keying (QPSK) coding, which is generally used to avoid phase slip caused by the practical limitations in processing the phase recovery algorithms. Ó 2011 Elsevier Inc. All rights reserved.
1. Introduction The transmission distance and speed in optical communications are primarily limited by optical signal-to-noise ratio (OSNR) and waveform distortion. The well established adaptive equalization algorithms being deployed with recent digital coherent technologies make possible a drastic improvement in the waveform distortion. However, no matter how good the equalization performance may be, it is never possible to restore the received OSNR once it has been degraded. Moreover, as the level of an M-ary modulation scheme increases, greater OSNR is required because the decreased Euclidean distance between each signal point in the constellation makes it more difficult to distinguish between the states. Only FEC can compensate significantly for low OSNR. Addressing this issue is prompting an increasing demand for powerful FEC to reduce the required OSNR. Recently, several trials aimed at exceeding an NCG of 10 dB have been initiated. Chan et al. proposed a continuously interleaved BCH code having an NCG of 9.35 dB with 7% redundancy [1]. This is considered to be one of the best performing hard decision FECs for optical communications. On the other hand, soft-decision is a promising way to improve the error correction capability effectively. SD-FEC uses not just the conventional ‘1’ vs. ‘0’ decision but also an indication of how certain we are that the decision is correct. Although it needs to calculate the maximum ⇑ Corresponding author. Fax: +81 467 41 2519. E-mail address: [email protected] (K. Onohara). 1068-5200/$ - see front matter Ó 2011 Elsevier Inc. All rights reserved. doi:10.1016/j.yofte.2011.09.005
a posteriori probability (MAP) for the additive white Gaussian noise (AWGN) channel, we can get more 2 dB coding gain in theory compared to HD-FECs. Thanks to the advent of digital signal processing (DSP) LSIs and high performance analog-to-digital converters (ADC) such as sampling rate of 56 Gs/s, signal bandwidth of 15 GHz, and resolution of 6 bits or more for digital coherent systems [2], SD-FEC becomes much easier to incorporate into the receiver hardware. In response to this trend, Miyata et al. proposed SD-based triple-concatenated FEC using LDPC codes with an NCG of 10.8 dB at 20.5% redundancy [3]. Yu et al. presented an SD-based LDPC(18353, 15296) code with an NCG of 11.28 dB at 20% redundancy [4]. A longer codeword brings with it increased NCG and also prevents any undesired error flaring floor. In this paper, we discuss how SD-FEC is becoming practical in digital coherent receivers using high speed ADCs. LDPC codes are introduced as good candidates for strong SD-FEC. Several implementations of SD-based LDPC codes are considered for 100 Gb/s transmission, where error floor is a critical issue needing to be addressed. To overcome this, the concatenation of HD-FEC and SD-based LDPC codes is proposed to achieve more than 10 dB NCG compliant with Optical Internetworking Forum (OIF) standards. In addition, we evaluate error correcting performance by implementing the entire 100 Gb/s throughput of LDPC code on FPGA-based hardware emulator. In the last part, we raise an important question for the definition of NCG in digital coherent systems with and without differential QPSK coding, which is generally used to avoid phase slip caused by the practical limitations in processing the phase recovery algorithms.
K. Onohara et al. / Optical Fiber Technology 17 (2011) 452–455
Note that the NCGs presented in this paper are defined at a post-FEC bit error ratio (BER) of 1015. 2. Soft-decision FEC Soft-decision decoding uses not just the conventional ‘1’ vs. ‘0’ decision but also an indication of how certain we are that the decision is correct. Fig. 1 illustrates a typical soft-decision structure for a QPSK constellation. The 2N 1 decision thresholds sandwiched between the two signal states of the in-phase and quadrature phase components are used for soft-decision decoding. In the case of N = 3, the two possible received signals, ‘1’ and ‘0’, lie in regions represented by a binary vector ranging from [0 1 1] to [1 1 1]. The left-most bit is the hard-decision digit, and the other two digits are information bits indicating the probability of ‘1’ or ‘0’. Conveniently, a recent digital coherent receiver has an ADC at its front end for demodulating the multi-level coded signals. This suddenly makes it much easier to realize soft-decision decoding, even though the bit rate is much higher than previously. The coding gain can in principle be improved by p/2 by using soft-decision decoding with infinite quantization bits N and redundancy, an approximately 2 dB difference. In a practical implementation of QPSK, an N of 3 or 4 is sufficient to obtain near ideal error correction performance. 3. LDPC codes For 100 Gb/s optical communications, one potential candidate for strong SD-FEC is an LDPC code, a linear code defined by the sparse parity-check matrix invented by Gallager, which is expected to exhibit superior error correcting performance. Studies into applying LDPC codes to optical communications were instituted as early as 1999 by Djordjevic et al. [5]. The expected merits of LDPC codes are not confined to high error correction capability, but also fit them for parallelization to reduce circuit complexity. In an LSI for high speed optical communications, ease of parallelized signal processing is essential for practical implementation. Fig. 2 illustrates four types of FEC frame structure and associated transponder configuration for a 100 Gb/s digital coherent system, which each consist of an OTU4 framer LSI, a coherent ASIC and an optical front-end. The FEC redundancy is assumed to be 20% as recommended by the OIF. The OTU4 framer LSI transforms the 100GbE signal to and from the OTU4 framed format, and usually incorporates a hard-decision FEC, e.g. RS(255, 239) or concatenated codes compliant with ITU-T G.975.1. The coherent ASIC includes an ADC and DSP
In-phase p.d.f.
Soft decision threshold
Quadrature-phase p.d.f.
Soft decision threshold Fig. 1. Typical 3-bit soft decision for QPSK signal.
453
for received signal quantization, dispersion compensation, phase estimation, clock recovery, polarization de-multiplexing, and adaptive equalization of waveform distortion due to polarization mode dispersion. In Fig. 2a and b a single 20% LDPC code is implemented in respectively the OTU4 framer or the coherent ASIC. It is expected that the 20% redundancy of the LDPC code will provide superior error correction performance. However, in order to suppress the undesired error floor which is inherent to LDPC codes, a very long codeword is required. This results in a large circuit and high latency. Fig. 2a has the drawback that a huge interconnection speed at N + 1 times the transmission rate is needed between the OTU4 framer LSI and the coherent ASIC, e.g. for N = 3, a 125 Gb/s 4 = 500 Gb/s interconnection is required. Fig. 2c shows another way to easily eliminate the LDPC code error floor. The error floor of the inner SD-FEC in the coherent ASIC is suppressed by concatenating it with a weak 3% outer HD-FEC code. Under this concept, the concatenation of LDPC(9216, 7936) and RS(992, 956) codes has been experimentally demonstrated to show an NCG of 9.7 dB (=9.0 dB at 1013) with only 2-bit soft-decision and four iterations [6]. Fig. 2d is thought to be the most practical implementation. An SD-FEC with a relatively short codeword and small circuit is implemented in the coherent ASIC as the inner code, concentrating on the higher BER (>103) region. The inevitable increase in the residual BER floor is cleaned up by the concatenated HD-FEC compliant with ITU-T G.975.1 in the OTU4 framer LSI. This concept was given the name ‘‘triple-concatenated FEC’’ [2]. 4. Evaluation of SD-FEC performance by FPGA based hardware emulation We evaluated the error correcting performance by implementing the entire 100 Gb/s throughput of LDPC(4608, 4080) code (13% redundancy) on an FPGA based hardware emulator (Mentor Graphics, Veloce). Hardware emulations enable us to save time drastically due to higher speed processing than software simulations and evaluate the error floor at the low BER region. The clock frequency was 556 kHz. We evaluated 204.8 million codewords in 7.4 h. Fig. 3 shows the FEC performance where the vertical axis is post-FEC BER and the horizontal axis is pre-FEC Q represented in dB. A blue solid line shows the results of an LDPC code, and a red solid line shows those of triple-concatenated FEC by software simulation we have reported [3]. Red circles show the results of an LDPC code by hardware emulation. It is clearly shown that the results of LDPC code by hardware emulation are consistent with those by software simulation. From these results, we can expect that an NCG of the LDPC code concatenated with EFEC compliant with ITU-T G.975.1 was 10.8 dB at a BER of 1015. If we implement the proposed FEC in a 40–45 nm class CMOS technology LSI with 512-parallel processing and a 250 MHz clock, the frame cycle is estimated to be 1.2 ls. The latency for decoding LDPC codes with EFEC is estimated to be less than 10 ls even for 16 iterations. 5. SD-FEC in differential QPSK and other modulation formats In digital coherent transmissions, realistic linewidth, additive noise, and undesired nonlinearity interaction cause catastrophic failure due to cycle slips more often than expected [7]. The phase estimate becomes incorrect over a quarter cycle, and stays wrong indefinitely. When a cycle slip occurs, at least one OTU frame (4080 8 4 bits) is lost. In order for the burst error correction capability of the FEC to be able to recover this, an impossible interleaving depth of at least 100 OTU frames would be necessary. Instead, differential QPSK is usually employed, in which a cycle slip causes 2 consecutive errored bits. The BER of differentially encoded
K. Onohara et al. / Optical Fiber Technology 17 (2011) 452–455
3% HD-FEC
(d) 13% SD-FEC concatenated with 7% HD-FEC (Triple concatenated codes) 13% LDPC 7% concatenated HD-FEC
Payload
E/O O/E E/O
ADC/DSP ADC/DSP
20% SD-FEC
O/E E/O O/E
Payload
13% SD-FEC
17% LDPC
3% HD-FEC
(c) SD-FEC concatenated with 3% HD-FEC
E/O
Not Used Not Used 7% HD-FEC
20% LDPC
Payload
Optics
O/E
100GbE/OTU4 100GbE/OTU4 100GbE/OTU4 100GbE/OTU4
(b) Single SD-FEC in coherent ASIC
20% SD-FEC
100GbE 100GbE 100GbE 100GbE
20% LDPC
Payload
Coherent ASIC
ADC/DSP
OTU4 framer
ADC/DSP
OTU4V frame structure
(a) Single SD-FEC in OTU4 framer
17% SD-FEC
454
Fig. 2. Four types of FEC frame structure and optical transponder for a 100 Gb/s digital coherent system.
Uncoded (Theoretical)
10-1
Post-FEC BER
10-3
Channel FEC ENC
LDPC H/W Emulation
10-5 10-7
(a) QPSK Channel
LDPC Simulation
10-9
FEC Diff ENC ENC
10-11 Triple-concatenated FEC
10-13 10-15
FEC DEC
5
5.5
6
6.5
7
7.5
8
8.5
Diff FEC DEC DEC
(b) Differential QPSK 9
Qin’=Qin
Qin’ Qin
Fig. 4. Simplified block diagrams of (a) QPSK and (b) differential QPSK.
Pre-FEC Q (dB) Fig. 3. FEC performance by implementing the entire 100 Gb/s throughput of LDPC(4608, 4080).
QPSK is 2p(1 p), where p is the error probability of synchronous detection QPSK, which is equivalent to an OSNR penalty of 1.1 dB at around 102. Fig. 4 shows simplified block diagrams for (a) QPSK and (b) differential QPSK. The received Q can be defined at two points. Qin is the FEC decoder input Q. Most systems are defined in terms of this. The input Q of a differential decoder is Qin0 . Most optical engineers consider this point to be the receiver input. Note that the definition of Q here is a simple conversion from BER using complementary error function (erfc). Fig. 5 illustrates the difference in FEC performance of QPSK and differential QPSK. The SD-FEC is assumed to be the
triple-concatenated FEC using LDPC codes type [2]. The Q difference between uncoded QPSK and uncoded differential QPSK is just 0.09 dB at 1015. With decreasing Qin0 , the difference widens, e.g. to 1.07 dB at 2 102. The NCG for QPSK is calculated to be 18 dB 6.4 dB + 10log(1/1.2) = 10.8 dB. In contrast, the NCG of differential QPSK appears to be 18 dB 6.4 dB 1.07 dB + 0.09 dB + 10log(1/1.2) = 9.8 dB. Is the NCG really degraded? The answer is no. The reason why the NCG looks degraded is that the Qin0 difference between QPSK and differential QPSK is different at different corrected BERs, e.g. 0.09 dB at 1015 and 1.07 dB at 2 102. The inherent performance of the FEC will not be degraded as long as the FEC can correct up to 4-bit short bursts. When trying to design a system power budget to ITU-T G.977, the 1.07 dB degradation due to differential coding should be
K. Onohara et al. / Optical Fiber Technology 17 (2011) 452–455
1.07dB
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0.09dB =9.8dB? 10-15
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Fig. 5. Soft decision FEC performance of QPSK and differential QPSK.
included in the mean Q value (in Fig. 4, use Qin not Qin0 ). A Q limit of 6.4 dB should always be used. SD-FEC is applicable other modulation formats such as m-QAM, and optical frequency division multiplexing (OFDM). However as the level of an M-ary modulation increases, the higher resolution of ADC is needed. For example, OSNR penalty of 16-QAM is ignorable when ADC resolution is higher than 6 bits [8]. Therefore, we need more than 9 bits of ADC resolution is needed for 3-bit SD-FEC into 16-QAM format. 6. Conclusions We reviewed recent progress in SD-FEC for optical communications. LDPC codes are expected to be strong candidates for SD-FECs.
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We showed and compared four ways of implementing LDPC codes in OTU4 framer LSIs and coherent ASICs. A triple-concatenated FEC is introduced as one of the strongest SD-FECs for 100 Gb/s transmission. We have verified error correcting performance by implementing the entire 100 Gb/s throughput of LDPC(4608, 4080) code on an FPGA based hardware emulator. It has been clearly shown that the results by hardware emulation were consistent with those by software simulation. We expect that an NCG of the LDPC code concatenated with EFEC was 10.8 dB at a BER of 1015. In addition, we discussed the definition of NCG in digital coherent systems with and without differential coding, which latter is generally used to avoid phase slip caused by the practical limitations in processing the phase recovery algorithms. References [1] F. Chang, K. Onohara, T. Mizuochi, IEEE Commun. Mag. 48 (3) (2010) 48–55. [2] B. Germann, I. Dedic, in: OSA SPPCom2010, SPTuC2, Karlsruhe, Germany, 2010. [3] Y. Miyata, K. Sugihara, W. Matsumoto, K. Onohara, T. Sugihara, K. Kubo, H. Yoshida, T. Mizuochi, in: OFC/NFOEC2010, OThL3, San Diego, CA, 2010. [4] F. Yu, C. Xie, L. Zeng, F. Chang, T. Coe, J. Dillard, Presented at ECOC2010, WS11 Workshop, Torino, Italy, 2010. [5] I.B. Djordjevic, M. Arabaci, L.L. Minkov, Next generation FEC for high-capacity communication in optical transport networks, IEEE J. Lightw. Technol 27 (16) (2009) 3518–3530. [6] T. Mizuochi, Y. Konishi, Y. Miyata, T. Inoue, K. Onohara, S. Kametani, T. Sugihara, K. Kubo, H. Yoshida, T. Kobayashi, T. Ichikawa, Experimental demonstration of concatenated LDPC and RS codes by FPGAs emulation, IEEE Photon. Technol. Lett. 21 (18) (2009) 1302–1304. [7] E. Ibragimov, B. Zhang, T.J. Schmidt, C. Malouin, N. Fediakine, H. Jiang, Cycle slip probability in 100G PM-QPSK systems, in: OFC/NFOEC2010, OWE2, San Diego, CA, 2010. [8] P.J. Winzer, A.H. Gnauck, C.R. Doerr, M. Magarini, L.L. Buhl, Spectrally efficient long-haul optical networking using 112-Gb/s polarization-multiplexed 16QAM, IEEE J. Lightw. Technol 28 (4) (2010) 547–556.