- Email: [email protected]
semiconductor field effect transistor gate contacts by high resolution transmission electron microscopy analysis
Materials Science and Engineering, B20 ( 1993) 33- 36
33
Investigation of stability of GaAs metal/electron/semiconductor field effect transistor gate contacts by high resolution transmission electron microscopy analysis N. Labat, Y. Danto and B. Plano UniversitO de Bordeaux I, IXL (URA CNRS 846), 351 cours de la LibOration, F-33405 Talence Cedex (France)
M. Chambon UniversitO de Bordeaux I, Laboratoire de Microscopie Electronique, 351 cours de la LibOration, F-33405 Talence Cedex (France) J.-M. D u m a s CNET, BP 40, F-22301 Lannion Cedex (France)
Abstract The structure of GaAs metal/electron/semiconductor field effect transistor (MESFET) gate contacts has been investigated by high resolution transmission electron microscopy (TEM). A specific technique has been used successfully to prepare thin and proper cross-sections of specific regions within GaAs devices. A significant defect has been observed at the periphery of the recessed gate, which indicates the presence of a non-passivated region of the active layer surface. The presence of an amorphous layer at the gate metallization-GaAs interface has been revealed by a high resolution observation. These structural anomalies have been correlated with parasitic effects of the I - V Schottky gate contact characteristics.
1. Introduction Accurate cross-sectional views of GaAs devices are particularly useful for failure analysis and process evaluation. Because of the reduced dimensions of defects and structures, it has become difficult to identify the physical origins of failures by scanning electron microscopy (SEM) examination. Transmission electron microscopy (TEM) is a technique which offers sufficient resolution for semiconductor material and interface studies [1, 2]. A few papers have been related to the correlation between observations on GaAs devices with their electrical parasitic effects [3, 4]. In the present work, a technique is proposed to produce thin cross-sections of desired regions within GaAs devices for TEM studies. This sample preparaTABLE 1. Device geometry Source-drain distance Source-gate distance Gate-drain distance Gate length
0921-5107/93/$6.00
3.5/am 1.1/~m 1.7 ~m 0.7/~m
tion procedure has been used to investigate the structure of MESFET Schottky gate contacts. The origins of the observed morphological aspects are assessed and the correlations with the gate metallization-GaAs interface properties are discussed.
2. Device description The devices studied are issued from a standard GaAs I.C. process. The main technological features are as follows: n and n + local implantations through the r.f.-sputtered Si3N 4 pre-encapsulated substrate; a recessed gate FET structure obtained by local etching of the channel; a TiPtAu gate metal 200 nm thick; a TiPtAu dual-metal-layer interconnect separated by a plasma-enhanced, chemical-vapour-deposited Si3N4 layer; 250 nm-thick AuGeNi ohmic contacts 250 nm thick. The device geometry (Table 1) has been determined from a SEM cross-sectional examination. © 1993 - Elsevier Sequoia. All rights reserved
34
N. Labat et aL
/
3mbili/v o / ( ; a A ~ AII;SkE7 gate contact,s
3. Electrical anomalies Electrical defects have been detected from the static electrical characterization of the devices. The current-voltage characteristics of the gate contact measured with respect to the drain or source present anomalies which cannot be described by the thermoionic model of the Schottky diode. The first anomaly is an abnormal N-shape noticed on the In 1G vs. V6 plot of the forward bias gate-source diode. As was suggested by Schneider [5], this behaviour can be attributed to a non-uniform barrier height voltage, resulting from chemical reactions at the gate metallization-GaAs interface. Hence, the Schottky diode current results from the superposition of several parallel diodes D,:
where S~, ~B~, ns and r~ are the specific parameters of the ith diode. The forward bias IG(V~) characteristic of the MESFETs has been successfully modelled by a set of two elementary diodes D 1 and D 2. The fitting parameters are given for one typical device in Fig. 1. It is obvious that the diode D 1, which presents a low barrier height voltage and a small effective area, is predominant under a low gate voltage (VG<0.35 V), whereas the diode D 2 corresponds to a more ideal Schottky contact. The devices studied also present higher values of the gate leakage current than those predicted by the thermoionic model. In Fig. 2, the reverse bias gate-source current I G is compared with the theoretical values (plots a and b). An excess experimental value of more than one order of magnitude is observed, even
when taking into account a reduced barricl heiglu resulting from the Schottky effect (plot a) and from the effect of the electric field (plot b) As was previously assumed by Dumas et aL j61, this excess leakage current should result from conductive "paths" in the access regions, between gate and source or gate and drain. Moreover, this intrinsic leakage current is strongly dependent on the curvature radius of the gate edge and the gate recess and on the electric field in this region.
4. TEM sample preparation Specific difficulties are encountered when preparing GaAs devices for T E M studies. The most important one is related to the localization of the desired area to be examined during the mechanical grinding and the ion milling processes. Compared with silicon devices, GaAs devices have the disadvantage of a lack of transparency of metallizations and GaAs materials until the specimen is less than 1 # m thick. Other problems arise from the metallographic properties of the materials involved (metal-GaAs interface) and the very fine patterns with the narrow gate, high walls of the ohmic contacts and thick interconnect metallizations. The sample preparation procedure is based on a "glass slide" method [7]. A thin glass slide is stuck on the top surface of the GaAs device to prevent damage in the polished section as a result of metal particle scratches. This will allow the observation of the structure of interest from the top surface under an optical light microscope. This stack is then cut in cross-section in the desired area so that the structure can be recognized in the section plane under an optical light microscope. A slice 200 # m thick is cut off from the device. It is attached to a T E M grid 3 nm in size, so that the
I mA IGS
f
10"e
~
Iosi;9
1BA
I0"
lO Io
1nA /
o
lO-i~ i
oo
0,2
0,4
i
0,6
0,8
Fig. 1. Forward bias I - V gate-source characteristic: m, experimental plot; - - , results of modelling with ~B1 =0.236 V, n 1 = 1.5, r 1 = 8 0 0 k ~ , ~B2=0-663 V, n 2= 1.17, r 2 =15 f~ and 10 -7 < S 1/S 2 < 10 -6.
10.u 0 '
o o°
°
°
J b
o
a vcs (',9
oL~'
o:,
'
o:0 '
Fig. 2. Reverse bias I - V measured; A, <>,computed.
o)'
;'
,L,
~ i.,
'
,.0
gate-source characteristic: ~,
N. Labat et al.
/
Stability of GaAs MESFET gate contacts
structure of interest is visible and is centred through the grid hole. The second face of the specimen is then precisely parallel ground down to less than 15 ,urn thick. This polished surface is smoothed down to allow the identification of the device patterns. Then, ion milling is performed for several hours as appropriate {under reduced ion milling rate conditions). The structure of interest is then thin enough to allow high resolution TEM examination.
35
dispersive, X-ray analysis combined with the scanning TEM mode. A two-layer structure is identified: the bottom TiPt layer presents a typical contrast of a polycrystalline material which is 50 nm thick; the darker TiPtAu layer, which is 120 nm thick.
Fig. 3. Bright-field TEM view of M E S F E T gate contact: a, n-GaAs active layer; b, TiPtAu layer; c, r.f.-sputtered Si3N 4 layer.
The micrograph of the gate metallization side region (Fig. 4) clearly shows that a crack in the metal is overhanging the flanks of the gate recess and that the GaAs surface is left unprotecte d at the periphery of the gate recess. This observation confirms the presence of structural defects, which are inherent to the fabrication process and particularly related to a narrow and abrupt gate recess etched in the Si3N4 pre-encapsulated substrate. Conductive "paths" developed in the access regions at the GaAs surface should result in an excess gate leakage current previously measured on the MESFET device. High resolution investigations have been carried out at the gate metallization-GaAs active layer interface. The orientation of the electron incident beam is parallel to the GaAs[110] direction, as is usual for such observations. An interface zone typical of the whole structure is shown in Fig. 5. Some Moir6 effect contrast (d) is observed in the polycrystalline TiPt layer. This results from double diffraction occurring at grain boundaries which are not perpendicular to the surface of the sample. The roughness of the GaAs surface, which is about 4 nm in amplitude, is assumed to be related to the recess etching process. An intermediate amorphous layer 5 nm thick is detected between the GaAs surface and the polycrystalline TiPt layer. It is composed of non-removed GaAs native oxide and non-stoichiometric titanium oxide compounds. This observation confirms the proposed model of a multiphase Schottky contact
Fig. 4. TEM view of the gate contact periphery: a, TiPT polycrystalline layer; b, TiPtAu (gold-rich) metallization layer; c, chemical-vapour-deposited SigN4 passivation layer.
Fig. 5. High resolution TEM view of the gate metallization-GaAs interface: a, n-GaAs active layer; b, interface amorphous layer; c, TiPt grains; d, Moird effect contrast.
5. Results and discussion
The morphological aspect of the gate contact structure is shown in the cross-sectional bright-field TEM views in Figs. 3 and 4. The composition of the gate metallization has been examined using in situ energy-
36
N. Labat et al.
/
Stability o[GaAs MESFE Tgate contact,s
resulting from the superposition of at least two phases (corresponding to different barrier height voltages) to explain the N-shape of the forward bias In IG vs. plot.
6. Conclusions The TEM technique has been used successfully to locate the physical origins of the electrical parasitic effects of MESFET devices. Moreover, correlations between structural defects of the MESFET gate contact inherent to the fabrication process with the electrical characteristics of the device have been assessed. Technological improvements, such as a suitable passivation of the whole access regions of the MESFET, have been implemented [6].
Acknowledgment This work has been partially supported by the CNET (Lannion, France).
References 1 R.B. Marcus and T. T. Sheng, Transmission Electron Microscopy of VLSI Circuits and Structures, Wiley, New York, 1983, pp. 15-29. 2 P. Ruterana, P. Friedel and J. Schneider, High resolution electron microscopy of the GaAs/Si3N 4 interface produced by multipolar plasma deposition, Appl. Phys. Lett., 49 (l l) (1986) 672-673. 3 A. Ezis and A.-K. Rai, Lateral protrusions of ohmic contacts to AIGaAs/GaAs MODFET material, Electron. Lett., Z~ (3) (1987) 113-114. 4 E Magistrali, D. Sala, M. Vanzi, P. Valli and .I. Turner, An investigation of high temperature degradation of Ti/Pt/Au Schottky contacts to GaAs FETs using TEM technique, Proc. 5th Conf. on Quality in Electronic Components, ESREF 91, Bordeaux, 1991, pp. 385-395. 5 M. V. Schneider, Characteristics of Schottky diodes with microcluster interface, Appl. Phvs. Lett., 43 (6)(1983) 558-560. 6 J.-M. Dumas, G. Kervarec, J.-Y. Bresse, J.-Y. Boulaire, M. Gauneau and D. Lecrosnier, Investigation on interelectrode metallic "paths" affecting the operation of IC MESFETs, Proc. IEEE GaAs-IC Gallium Arsenide, Integrated Circuit Syrup., Portland, OR, 1987, pp. 15-18. 7 W. G. Cowden and A. K. Datye, The use of glass slides for preparing cross-section TEM samples of discrete transistors, Mater. Res. Soc. Syrup. Proc., 115 (1988) 109-114.
33
Investigation of stability of GaAs metal/electron/semiconductor field effect transistor gate contacts by high resolution transmission electron microscopy analysis N. Labat, Y. Danto and B. Plano UniversitO de Bordeaux I, IXL (URA CNRS 846), 351 cours de la LibOration, F-33405 Talence Cedex (France)
M. Chambon UniversitO de Bordeaux I, Laboratoire de Microscopie Electronique, 351 cours de la LibOration, F-33405 Talence Cedex (France) J.-M. D u m a s CNET, BP 40, F-22301 Lannion Cedex (France)
Abstract The structure of GaAs metal/electron/semiconductor field effect transistor (MESFET) gate contacts has been investigated by high resolution transmission electron microscopy (TEM). A specific technique has been used successfully to prepare thin and proper cross-sections of specific regions within GaAs devices. A significant defect has been observed at the periphery of the recessed gate, which indicates the presence of a non-passivated region of the active layer surface. The presence of an amorphous layer at the gate metallization-GaAs interface has been revealed by a high resolution observation. These structural anomalies have been correlated with parasitic effects of the I - V Schottky gate contact characteristics.
1. Introduction Accurate cross-sectional views of GaAs devices are particularly useful for failure analysis and process evaluation. Because of the reduced dimensions of defects and structures, it has become difficult to identify the physical origins of failures by scanning electron microscopy (SEM) examination. Transmission electron microscopy (TEM) is a technique which offers sufficient resolution for semiconductor material and interface studies [1, 2]. A few papers have been related to the correlation between observations on GaAs devices with their electrical parasitic effects [3, 4]. In the present work, a technique is proposed to produce thin cross-sections of desired regions within GaAs devices for TEM studies. This sample preparaTABLE 1. Device geometry Source-drain distance Source-gate distance Gate-drain distance Gate length
0921-5107/93/$6.00
3.5/am 1.1/~m 1.7 ~m 0.7/~m
tion procedure has been used to investigate the structure of MESFET Schottky gate contacts. The origins of the observed morphological aspects are assessed and the correlations with the gate metallization-GaAs interface properties are discussed.
2. Device description The devices studied are issued from a standard GaAs I.C. process. The main technological features are as follows: n and n + local implantations through the r.f.-sputtered Si3N 4 pre-encapsulated substrate; a recessed gate FET structure obtained by local etching of the channel; a TiPtAu gate metal 200 nm thick; a TiPtAu dual-metal-layer interconnect separated by a plasma-enhanced, chemical-vapour-deposited Si3N4 layer; 250 nm-thick AuGeNi ohmic contacts 250 nm thick. The device geometry (Table 1) has been determined from a SEM cross-sectional examination. © 1993 - Elsevier Sequoia. All rights reserved
34
N. Labat et aL
/
3mbili/v o / ( ; a A ~ AII;SkE7 gate contact,s
3. Electrical anomalies Electrical defects have been detected from the static electrical characterization of the devices. The current-voltage characteristics of the gate contact measured with respect to the drain or source present anomalies which cannot be described by the thermoionic model of the Schottky diode. The first anomaly is an abnormal N-shape noticed on the In 1G vs. V6 plot of the forward bias gate-source diode. As was suggested by Schneider [5], this behaviour can be attributed to a non-uniform barrier height voltage, resulting from chemical reactions at the gate metallization-GaAs interface. Hence, the Schottky diode current results from the superposition of several parallel diodes D,:
where S~, ~B~, ns and r~ are the specific parameters of the ith diode. The forward bias IG(V~) characteristic of the MESFETs has been successfully modelled by a set of two elementary diodes D 1 and D 2. The fitting parameters are given for one typical device in Fig. 1. It is obvious that the diode D 1, which presents a low barrier height voltage and a small effective area, is predominant under a low gate voltage (VG<0.35 V), whereas the diode D 2 corresponds to a more ideal Schottky contact. The devices studied also present higher values of the gate leakage current than those predicted by the thermoionic model. In Fig. 2, the reverse bias gate-source current I G is compared with the theoretical values (plots a and b). An excess experimental value of more than one order of magnitude is observed, even
when taking into account a reduced barricl heiglu resulting from the Schottky effect (plot a) and from the effect of the electric field (plot b) As was previously assumed by Dumas et aL j61, this excess leakage current should result from conductive "paths" in the access regions, between gate and source or gate and drain. Moreover, this intrinsic leakage current is strongly dependent on the curvature radius of the gate edge and the gate recess and on the electric field in this region.
4. TEM sample preparation Specific difficulties are encountered when preparing GaAs devices for T E M studies. The most important one is related to the localization of the desired area to be examined during the mechanical grinding and the ion milling processes. Compared with silicon devices, GaAs devices have the disadvantage of a lack of transparency of metallizations and GaAs materials until the specimen is less than 1 # m thick. Other problems arise from the metallographic properties of the materials involved (metal-GaAs interface) and the very fine patterns with the narrow gate, high walls of the ohmic contacts and thick interconnect metallizations. The sample preparation procedure is based on a "glass slide" method [7]. A thin glass slide is stuck on the top surface of the GaAs device to prevent damage in the polished section as a result of metal particle scratches. This will allow the observation of the structure of interest from the top surface under an optical light microscope. This stack is then cut in cross-section in the desired area so that the structure can be recognized in the section plane under an optical light microscope. A slice 200 # m thick is cut off from the device. It is attached to a T E M grid 3 nm in size, so that the
I mA IGS
f
10"e
~
Iosi;9
1BA
I0"
lO Io
1nA /
o
lO-i~ i
oo
0,2
0,4
i
0,6
0,8
Fig. 1. Forward bias I - V gate-source characteristic: m, experimental plot; - - , results of modelling with ~B1 =0.236 V, n 1 = 1.5, r 1 = 8 0 0 k ~ , ~B2=0-663 V, n 2= 1.17, r 2 =15 f~ and 10 -7 < S 1/S 2 < 10 -6.
10.u 0 '
o o°
°
°
J b
o
a vcs (',9
oL~'
o:,
'
o:0 '
Fig. 2. Reverse bias I - V measured; A, <>,computed.
o)'
;'
,L,
~ i.,
'
,.0
gate-source characteristic: ~,
N. Labat et al.
/
Stability of GaAs MESFET gate contacts
structure of interest is visible and is centred through the grid hole. The second face of the specimen is then precisely parallel ground down to less than 15 ,urn thick. This polished surface is smoothed down to allow the identification of the device patterns. Then, ion milling is performed for several hours as appropriate {under reduced ion milling rate conditions). The structure of interest is then thin enough to allow high resolution TEM examination.
35
dispersive, X-ray analysis combined with the scanning TEM mode. A two-layer structure is identified: the bottom TiPt layer presents a typical contrast of a polycrystalline material which is 50 nm thick; the darker TiPtAu layer, which is 120 nm thick.
Fig. 3. Bright-field TEM view of M E S F E T gate contact: a, n-GaAs active layer; b, TiPtAu layer; c, r.f.-sputtered Si3N 4 layer.
The micrograph of the gate metallization side region (Fig. 4) clearly shows that a crack in the metal is overhanging the flanks of the gate recess and that the GaAs surface is left unprotecte d at the periphery of the gate recess. This observation confirms the presence of structural defects, which are inherent to the fabrication process and particularly related to a narrow and abrupt gate recess etched in the Si3N4 pre-encapsulated substrate. Conductive "paths" developed in the access regions at the GaAs surface should result in an excess gate leakage current previously measured on the MESFET device. High resolution investigations have been carried out at the gate metallization-GaAs active layer interface. The orientation of the electron incident beam is parallel to the GaAs[110] direction, as is usual for such observations. An interface zone typical of the whole structure is shown in Fig. 5. Some Moir6 effect contrast (d) is observed in the polycrystalline TiPt layer. This results from double diffraction occurring at grain boundaries which are not perpendicular to the surface of the sample. The roughness of the GaAs surface, which is about 4 nm in amplitude, is assumed to be related to the recess etching process. An intermediate amorphous layer 5 nm thick is detected between the GaAs surface and the polycrystalline TiPt layer. It is composed of non-removed GaAs native oxide and non-stoichiometric titanium oxide compounds. This observation confirms the proposed model of a multiphase Schottky contact
Fig. 4. TEM view of the gate contact periphery: a, TiPT polycrystalline layer; b, TiPtAu (gold-rich) metallization layer; c, chemical-vapour-deposited SigN4 passivation layer.
Fig. 5. High resolution TEM view of the gate metallization-GaAs interface: a, n-GaAs active layer; b, interface amorphous layer; c, TiPt grains; d, Moird effect contrast.
5. Results and discussion
The morphological aspect of the gate contact structure is shown in the cross-sectional bright-field TEM views in Figs. 3 and 4. The composition of the gate metallization has been examined using in situ energy-
36
N. Labat et al.
/
Stability o[GaAs MESFE Tgate contact,s
resulting from the superposition of at least two phases (corresponding to different barrier height voltages) to explain the N-shape of the forward bias In IG vs. plot.
6. Conclusions The TEM technique has been used successfully to locate the physical origins of the electrical parasitic effects of MESFET devices. Moreover, correlations between structural defects of the MESFET gate contact inherent to the fabrication process with the electrical characteristics of the device have been assessed. Technological improvements, such as a suitable passivation of the whole access regions of the MESFET, have been implemented [6].
Acknowledgment This work has been partially supported by the CNET (Lannion, France).
References 1 R.B. Marcus and T. T. Sheng, Transmission Electron Microscopy of VLSI Circuits and Structures, Wiley, New York, 1983, pp. 15-29. 2 P. Ruterana, P. Friedel and J. Schneider, High resolution electron microscopy of the GaAs/Si3N 4 interface produced by multipolar plasma deposition, Appl. Phys. Lett., 49 (l l) (1986) 672-673. 3 A. Ezis and A.-K. Rai, Lateral protrusions of ohmic contacts to AIGaAs/GaAs MODFET material, Electron. Lett., Z~ (3) (1987) 113-114. 4 E Magistrali, D. Sala, M. Vanzi, P. Valli and .I. Turner, An investigation of high temperature degradation of Ti/Pt/Au Schottky contacts to GaAs FETs using TEM technique, Proc. 5th Conf. on Quality in Electronic Components, ESREF 91, Bordeaux, 1991, pp. 385-395. 5 M. V. Schneider, Characteristics of Schottky diodes with microcluster interface, Appl. Phvs. Lett., 43 (6)(1983) 558-560. 6 J.-M. Dumas, G. Kervarec, J.-Y. Bresse, J.-Y. Boulaire, M. Gauneau and D. Lecrosnier, Investigation on interelectrode metallic "paths" affecting the operation of IC MESFETs, Proc. IEEE GaAs-IC Gallium Arsenide, Integrated Circuit Syrup., Portland, OR, 1987, pp. 15-18. 7 W. G. Cowden and A. K. Datye, The use of glass slides for preparing cross-section TEM samples of discrete transistors, Mater. Res. Soc. Syrup. Proc., 115 (1988) 109-114.