Seven-bit analog-to-digital converter for nanosecond pulses

NUCLEAR

INSTRUMENTS

AND

METHODS

67

(1969)229-239;

~C) N O R T H - H O L L A N D

PUBLISHING

CO.

SEVEN-BIT ANALOG-TO-DIGITAL CONVERTER FOR N A N O S E C O N D PULSES* D. P O R A T a n d K. H E N S E

StanJbrd Linear Accelerator Center, SmnJbrd UniversiO,, StanJbrd, CaliJbrnia, U.S.A. Received 26 July 1968 The time integral o f n a n o s e c o n d pulses is digitized with a linearity, resolution and stability -~1~o. T h e sensitivity of the circuit is 1.2 p C / c o u n t . T h e circuit can also be utilized for

m e a s u r e m e n t of short time intervals. In this m o d e its sensitivity, for s t a n d a r d logic pulses ( - 0 . 7 V), is ~-~ 80 ps/count.

1. I n t r o d u c t i o n

proportional to the time integral of the input signal. Output is - 0 . 2 V into 50 ohm, nominal; (b) D e l i v e r s + 4 V (logic "1") into 100 ohm. Outputs can be " O R " - e d on 8 data bus lines for manual or computer sequential readout of several ADC's; Overflow: Eighths bit available when data exceed 127 counts. Circuit limits around 160 counts. + 4 V into 2.7 k~, pulse or level. Output strobe: Enables data to be presented on the data bus lines as long as STROBE is ON; Visual indicators: (a) DATA pilot light shows when data are present on weights 22 through 26; (b) OVERFLOW pilot light indicates that counts exceed 127. Reset and timing functions are provided by one control circuit capable of serving 11 ADC's (section 2).

The availability of digital computers for high-energy physics experiments generates the demand for interface circuitry between the experimental apparatus and the computer. Digital data are commonly pre-processed in fast logic blocks, and their rate is reduced considerably before being sent to the computer. The problem in such a case reduces to matching pulse shapes at the interface. However, analog signals of nanosecond duration require either linear time scaling (stretching) or a fast A-D converter, since computers cannot as yet accept such signals directly. A K ° experiment J) is being built up in which two analog-type data of nanosecond and sub-nanosecond duration have to be measured: (a) pulse height information from 66 shower counters to measure y-ray energies; (b) Time-of-flight analysis for particle identification. The circuit described below is capable of performing either function. Its specifications are: - 150 pC, max. (e.g., - 15 mA, 10 nsec pulse) ; input impedance 50 ohm ; - 0 . 7 V into 50 ohm, i.e. stanGate input: dard NIM logic ONE. Minimum duration 4 nsec; Better than 1%, integral Linearity: > 7 binary bits; Resolution: Analog output (PHA): Delivers a negative pulse proportional to the time integral of the input signal and matching input characteristics of pulseheight analyzers. Rise time (10 to 9 0 % ) = 0.6ps. Decay time constant (to l/e) = 3.2/~s; Digital outputs: (a) "~S C A L E R ' . Delivers number of pulses (at 10 MHz rate)

Data input:

* W o r k s u p p o r t e d by the U. S. A t o m i c Energy C o m m i s s i o n and the Airforce Office o f Scientific Research C o n t r a c t n u m b e r F 44620-67-e-0070.

229

2. C i r c u i t d e s c r i p t i o n

Fig. 1 shows a block diagram of the analog-todigital converter (ADC). Transistor numbers in the blocks identify the relevant components also shown in greater detail in the circuit diagrams, figs. 2-5. The operation of the instrument will be described with help of fig. I and the timing diagram of fig. 6. An input pulse, such as from a fast photomultiplier, applied to the grounded-base stage, QI, will pass to the amplifier-integrator, provided it is coincident in time with a gate signal. The linear gate is of the matched-quad type and is driven from the gate amplifier Q2 through Q5. The subsequent stages, Q6 through QI 1 are used for quasi-integration and amplification of the signal. AC coupling has been used throughout since the instrument was designed to serve in experiments at the Stanford Linear Accelerator

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S E V E N - B I T A N A L O G - T O - D I G I T A L CONVERTER

(a)

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(e) Fig. 6. Waveforms and timing signals. Hor.: 3/~sec/cm. Vert. (a), (b) and (c): 0.5 V/cm; (d) and (e): 2 V/cm. a. Output at PHA; b. Input to peak detector; c. Waveform at C45. The flat portion represents the peak detector output. The trailing edge is due to the discharge current source. Note the negative step at 0 volt caused by

the clamp; d. Comparator output; e. Clamp signal,

Center (SLAC), whose short beam pulse of 1.6/~s together with a 360 pps repetition rate exclude any possibilities of pile-up. The amplifier-integrator could thus be designed for good noise rejection at low frequencies in addition to the usual high-frequency noise rejection due to integration. Q12 and Q13 are

235

a feedback pair delivering a negative pulse, fig. 6a, whose characteristics match the input requirements of several commercially available pulse-height analyzers (PHA). This output facilitates monitoring selected channels during an experiment that involves a number of ADC's and aids in adjusting to zero the gate pedestal. The peak detector utilizes a differential amplifier Q 14, Q 15 which controls a current source Q 17, Q 18 to charge a capacitor (C45) to the peak value of the integrated pulse. The signal appearing at the input of the peak detector (Q14A) has a rise time of 2.0 iLsec (10 to 90%), and a decay time constant of 6.0/~sec, fig. 6b. The finite response time of the peak detector would result in a non-linear relationship of input charge vs number of counts, had the pulse not been slowed down prior to peak detection. Q41 exhibits sharp cut-off characteristics to limit the signal amplitude to 4.6 V, and protects the gate-source junctions of Q14 and the base-emitter junctions of QI 5. Q14 is a matched pair of FET's; the gate of Ql4B presents a high impedance across C45 permitting the peak value of the integrated pulse to be kept for relatively long time intervals with little loss of amplitude. The present circuit has a time constant of 5 ms. (Time constants of the order of I sec are possible with minor modifications and may be of use where a considerable number of analog data is multiplexed into one A to D converter). Current source Ql8 charges C45 as long as the output of the peak detector is lower than the input signal to the differential amplifier Q14, Q15. Otherwise it is turned off, and between incoming data it is also clamped to prevent its accidental actuation by noise. C45 is kept fully charged for a duration of approximately 15 #sec determined by the monostable Z51 and the SAMPLE flip-flop F1. This allows for the signal at the gate of Q14A to decay completely before analogto-digital conversion is initiated. The analog-to-digital conversion is of the capacitordischarge type. Briefly, the comparator, A 1, senses the voltage across C45 and assumes a logic ONE state when Vc~s > VREv. After some delay of 15 psec, this state actuates the current discharge source QI9 through Q23 which discharges linearly C45 resulting in the waveform as in fig. 6c. A more detailed description follows: the output from the comparator (Q26, Q27, A1) is as shown in fig. 6d. For Vc45 _< VREF, the output is - 0 . 7 V . When Vc45 > VREV, it rises to about 0 V and cannot rise further due to the action of the SAMPLE flip-flop, F1, which inhibits the comparator output for 15/~sec. A logic ONE from FI permits the output to rise to

236

D. P O R A T A N D K. H E N S E

Fig. 7a. Analog-to-digital converter.

+ 6 V, enabling G4 and thus allowing the l0 MHz clock signal to be applied to the 8-bit binary counter composed of two integrated circuits A5 and A6. When Vc45 < V~EV, the comparator returns to its Z E R O state, inhibiting further clock pulses from arriving at the 8-bit counter, and turning off the discharge current source. The trailing edge of the comparator output resets the S A M P L E flip-flop which in turn disables the comparator. It also actuates the C L A M P flip-flop which clamps C45 via Q25 to a slightly negative

potential, fig. 6c, and relaxes tolerances on leakage currents which may build up a charge on C45 between signals. The clamp on C45 is released approximately 1 #sec after receipt of new data. C45 is thus protected from noise in the time interval when the environmental noise is highest, e.g., due to spark chambers or other pulsed apparatus. The digital information, stored in the binary counter, is strobed out via N A N D gates G 9 - G I 6 . The output

SEVEN-BIT ANALOG-TO-DIGITAL

CONVERTER

237

Fig. 7b. Control module.

amplifiers Q33-Q40 can deliver 40 mA into 100 ohm transmission lines. The SCALER output delivers a number of pulses proportional to the time integral of the input signal and can be used for monitoring selected channels or for calibration of the instruments when a computer is not available. One pilot light provides visual indication of overflow conditions, (27-th bit), the other is actuated by an OR circuit of weights 22-26 to indicate that DATA are available.

RESET can be accomplished in three ways: a. Push-button reset required when the equipment is energized, b. External reset, requiring a positive pulse of 70 nsec and 3.5 V, minimum; c. Internal reset. In this mode one preserves the digital information in the binary counter until arrival of a new event. The gate signal, allowing this event to be measured, is utilized to produce a reset pulse. Thus the digital part of the circuit is

238

D.

PORAT

AND

reset whilst the analog signal is being processed. In the experiment under consideration (section 1) a spark chamber is actuated whenever an event is recognized by fast logic circuitry. It is important, therefore, to protect against noise those circuits that are located in the proximity of spark chambers. Such problems are typical in an experimental situation. Q 6 9 - Q 7 1 generate a 1 #sec reset signal which keeps all bistable circuit elements in the O F F state well after the spark chamber noise has decayed. The 1 #sec monostable also releases the clamping action on C45 and on the peak detector via the C L A M P flip-flop, F2, and via switches Q16 and Q25. Thus the clamp is released 1 #sec after receipt of new data and actuated immediately after completion of the analog-to-digital conversion, fig. 6e. It was stated earlier that the SAMPLE and C L A M P flip-flops are reset by the trailing edge of the comparator Output. However, an experimental situation is likely where some A D C channels did not receive data, though an event has been recorded which initiates the unclamping of C45, etc. In such a case no trailing edge is available from the comparator for resetting the S A M P L E and C L A M P flip-flops. Gates G 5 - G 7 sense such situations and generate the requisite reset signal typically within 90 nsec. The circuit shown above the dashed line of fig. 1 (details in figs. 2 and 3) was packaged in a standard AEC no. 1 module. The circuit containing some 330 components, including transistors and integrated circuits, was constructed using printed-board techniques. The part of the circuit shown below the dashed line of fig. 1 (details in figs. 4 and 5) provides control functions and was constructed similarly. A standard AEC nuclear instrumentation chassis can thus hold one control module providing the functions of gating, clock and timing for eleven measuring modules. Power is obtained from a supply, model AEC-320-3 and an auxiliary source of + 5.5 V for the integrated circuits. In larger systems it is convenient to supply the pilot lamps from an unregulated source. A study was made of two different ways to multiplex the analog information for conversion into digital form. The time constant at the peak detector can be lengthened by increase of R90, C45 and the charging current in Q 17, Q 18. A fast analog-to-digital converter can then be used for 100 channels or more in a multiplexing scheme. One multiplexing arrangement studied involves the use of analog switches. The other solution utilizes the binary states at the output of a comparator to monitor whether C45 has been fully discharged,

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of counts vs input amplitude.

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Input pulse:

10 nsec, rise and fall time = 1 nsec. indicating that the analog-to-digital conversion has been completed. 3.

Results

Fig. 8 shows the number of counts vs input amplitude for pulses of 10 nsec duration. The maximum input amplitude for 1% linearity is - 0 . 7 V, however the !

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SEVEN-BIT

ANALOG-TO-DIGITAL

useful range is up to - 1.1 V at which point the sharp cut-off characteristics of the limiter (Q41) take over. The circuit can be utilized for measurements of subnanosecond time intervals such as in time-of-flight analysis. In this mode one applies a signal of standard amplitude and duration to the D A T A terminal of the instrument. This input stage together with its linear gate form an "overlap-coincidence" circuit, the output of which is then integrated and digitized. Fig. 9 shows results obtained by moving the G A T E signal in time with respect to the D A T A input signal. The observed slope of 12.6 counts/nsec can be changed by altering the input amplitude of the D A T A signal or the gain of the amplifier. A small system of 10 measuring modules and one control module was built and operated reliably. The system under construction utilizes sixty-six instruments which are multiplexed, together with other data, into a PDP-9 computer.

CONVERTER

239

Note added in proof: A system consisting of 28 instruments used in the time measuring mode and 33 in the amplitude measuring mode has been used in the meantime and performed to specifications. We are indebted to Prof. M. Schwartz and Dr. D. Dorfan for illuminating discussions and to Prof. S. Wojcicki for reading the manuscript. Thanks are due to Mr. F. Generali and the Electronics Fabrication Group for their fine printed-circuit work.

Reference 1) D. Dorfan, M. Schwartz and S. Wojcicki, Measurements of the magnitude of r/00 and its phase relative to ~+-, SLAC proposal no. 3 I, Stanford Linear Accelerator Center, Stanford University, Stanford, California (October, 1967) unpublished.