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Si by selective aspect ratio trapping
ARTICLE IN PRESS Journal of Crystal Growth 311 (2009) 3133–3137
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Journal of Crystal Growth journal homepage: www.elsevier.com/locate/jcrysgro
Growth and characterization of GaAs layers on polished Ge/Si by selective aspect ratio trapping J.Z. Li , J. Bai, J.M. Hydrick, J.S. Park, C. Major, M. Carroll, J.G. Fiorenza, A. Lochtefeld AmberWave Systems Corporation, 13 Garabedian Drive, Salem, NH 03079, USA
a r t i c l e in fo
abstract
Article history: Received 3 October 2008 Received in revised form 5 March 2009 Accepted 11 March 2009 Communicated by D.W. Shaw Available online 24 March 2009
Epitaxial GaAs layers have been deposited on polished Ge film grown on exactly (0 0 1) oriented Si substrate by metal-organic chemical vapor deposition (MOCVD) via aspect ratio trapping (ART) method. Double-crystal X-ray diffraction shows that the full-width at half-maximum (FWHM) of the (4 0 0) reflection obtained from 1 mm GaAs is 140 arcsec. Scanning electron microscopy (SEM) of the GaAs layer surface shows that the amount of antiphase domain defects (APD) raised from GaAs/Ge interface using Ge ART on Si is dramatically reduced compared to GaAs layers grown on exact (0 0 1) Ge substrate. Defect reduction and Ge diffusion at vicinal GaAs/Ge interface were investigated via cross-section transmission electron microscopy (X-TEM) and secondary ion mass spectrometry (SIMS). Film morphology and optical properties were evaluated via SEM and room temperature photoluminescence (PL). & 2009 Elsevier B.V. All rights reserved.
PACS: 81.05.Ea 81.15.Gh 78.55.Cr 71.55.Eq 73.40.Kp Keywords: A1. Defects A2. III–V on Si A3. Aspect ratio trapping A3. Metal-organic chemical vapor deposition B1. Gallium compounds
1. Introduction Monolithic integration of III–V optoelectronic materials onto elemental semiconductors such as Si and Ge has attracted a great deal of interest for decades in the hope of taking advantages of each material’s superiorities. Among those approaches, epitaxial growth of GaAs on Si has been the most extensively investigated subject. Although some progress has been reported [1–3], device quality of GaAs on Si has not materialized at the commercial level due to large mismatch in lattice constants and thermal expansion coefficients between GaAs and Si. Considering the actual material growth cost and the processing limit in practically realizing optoelectronic integrated circuits (OEIC) on Si substrates, growth of high-quality GaAs with minimal transitional buffer layer thickness on exact oriented (0 0 1) Si substrate platform is desired. Since Ge has a lattice constant very close to that of GaAs, with a mismatch of only 0.07%, much lower than the 4.1% mismatch between GaAs and Si, growth of virtual Ge/Si substrate followed
Corresponding author. Tel.: +1 603 870 8675.
E-mail address: [email protected] (J.Z. Li). 0022-0248/$ - see front matter & 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.jcrysgro.2009.03.018
by GaAs growth is a promising growth option. To date, several groups have reported on the growth of GaAs layers on Ge/Si substrates [4–6]. However, these GaAs layers have had rather higher dislocation density or involve a very thick Ge-containing buffer layer. The inferiority of these GaAs layers grown on Ge/Si is mainly due to the poor crystalline quality of the Ge buffer layers. Thus, the Ge crystalline quality must be improved in order to grow high-quality GaAs layers on Ge/Si. On the other hand, the common and principal difficulty in growing polar GaAs on nonpolar Ge is the creation of antiphase domain (APD) defects in GaAs layers. It has been reported that an effective way to obtain single domain GaAs is growing GaAs on off-cut Ge (0 0 1) substrates [7,8]. Thus, when using Ge/Si as a virtual substrate, the starting substrate would need to be an off-cut Si (0 0 1). However, this may not be an ideal solution for OEIC processes, for which exact (0 0 1) Si substrates have been the platform of choice. Previously, the authors have demonstrated an effective approach to GaAs heterointegration by using MOCVD via the aspect ratio trapping method to reduce threading dislocations during Ge and GaAs growth on exact (0 0 1) Si substrates [9,10]. Here, we demonstrate the growth and characterization of GaAs layers on such a Ge/Si template, where the Ge layer is coalesced and polished
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by chemical mechanical polishing (CMP), to serve as a buffer layer between GaAs and Si. The film quality of overgrown GaAs was inspected with SEM, SIMS, room temperature PL and X-TEM.
2. Experimental procedure Two-step low-pressure MOCVD processes were performed for GaAs/Ge/Si growth. A cross-sectional SEM image in Fig. 1 shows the layer structure. First, 2–3 mm coalesced Ge layer was grown by using MOCVD on exact (0 0 1) Si substrates with trench-patterned thermal SiO2 on the Si surface. Details of the Ge growth procedure and material characterization are described in Ref. [9]. After Ge growth, Ge layer was polished via chemical mechanical polishing to a thickness of about 1–1.5 mm. The CMP process is described in Ref. [11]. A mirror-like Ge surface was obtained with an etch pit density (EPD) level in the mid-106/cm2 range. Before GaAs overgrowth, the polished Ge/Si substrate was cleaned with successive dips in H2O2 solution and 1:50 diluted hydrofluoric acid (HF), with deionized water rinses between steps. A final dip in the HF solution left the Ge surface hydrophobic prior to loading in the MOCVD reactor. In the second step, GaAs layers were grown in a separate MOCVD reactor at a constant low pressure (70 Torr) by using triethylgallium (TEG) and arsine (AsH3) for buffer layer growth and trimethylgallium (TMG) and AsH3 for upper GaAs layer growth. Prior to buffer layer growth, the wafer was baked at 680 1C for 10 min under H2 overpressure followed by 2 min Ascoating by introducing AsH3 overpressure. An optimized threeperiod GaAs (10 nm)/Al0.40Ga0.6As (15 nm) superlattice buffer layer structure was grown at temperature of 600 1C. Finally, 1 mm GaAs layer was grown at temperature of 600 1C with an optimized annealing process. In addition, p- and n-type doping were investigated by using carbon tetrabromide and SiH3 during GaAs layer growth, respectively. The growth rates were kept at 7 nm/min for the buffer layer and at 50 nm/min for the top layer. In order to monitor any growth condition variation, a blanket GaAs (0 0 1) substrate and a blanket Ge (0 0 1) substrate were used in each growth run, in addition to the Ge virtual substrate.
substrate via ART are shown in Fig. 2(a) and (b), respectively. Clearly, a commonly seen high-density antiphase disordered network appeared in GaAs grown on exact (0 0 1) Ge substrate, while very few APD defects were observed for GaAs on Ge/Si in Fig. 2(b). A possible explanation for the APD reduction is related to the crystallographic growth behavior of the Ge buffer layer. It has been demonstrated that (11 3) facets are primarily formed during initial Ge growth inside the trenched area [12]. As the Ge film grows above the SiO2 mask, a coalesced wavy Ge growth front is formed, and faceting orientation gradually change from (11 3) to (0 0 1). Therefore, in the vicinity of coalesced Ge region, the aspolished Ge surface may have miss-oriented facets in a periodically modulated fashion, which would provide equivalent off-cut surface feature and lead to suppressed APD formation in the overgrown GaAs layers. In fact, further investigations indicated that the density of APD in overgrown GaAs layers decreases with increasing CMP depth. In other words, after CMP, a thinner Ge layer above the SiO2 patterning leads to higher GaAs overgrowth quality, which supports the above explanation.
3. Results and discussion 3.1. Surface morphology and room temperature PL Under the same growth conditions, mirror-like surfaces were observed from samples grown on the GaAs substrate and polished Ge/Si substrate while hazy GaAs surface was observed on the sample grown on the Ge substrate. SEM surface images of GaAs grown on exact (0 0 1) Ge substrate and on polished Ge/Si
Fig. 1. Cross-section SEM image of GaAs overgrown on polished Ge film grown on SiO2 trench patterned Si (0 0 1) substrate.
Fig. 2. Surface SEM images of GaAs samples grown in the same run: (a) grown on exact oriented (0 0 1) Ge substrate and (b) grown on polished Ge/Si substrate via ART.
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Shown in Fig. 3 are the room temperature PL results for the samples of Fig. 2. Both PL spectrums show a clean band gap emission at 867 nm, indicating no Ge-based complexes were formed inside the GaAs layer. This is confirmed by the SIMS profile in Fig. 5. However, the PL intensity for the GaAs layer grown on Ge/Si substrate is about 5 times higher than that of GaAs grown on exact (0 0 1) Ge substrate, which is attributed to the APD reduction in the GaAs/Ge/Si ART structure.
during GaAs overgrowth. As shown in growth chart (b), after growing 100 nm GaAs on top of the low-temperature buffer layer, the growth temperature was elevated up to 720 1C and annealed for 10 min under AsH3 overpressure with small TMG flow rate. After 10 min, the growth temperature was cooled to 300 1C, and then immediately ramped back up to 600 1C for the remaining upper GaAs layer growth. It is found that introducing such an insitu thermal annealing step during GaAs growth improves both GaAs layer and Ge layer crystalline quality. As seen from Fig. 4, the full-width at half-maximum (FWHM) of the XRD o angle for GaAs decreased from 248 to 145 arcsec and the FWHM for the Ge layer also decreased, from 198 to 137 arcsec.
3.2. Double-crystal X-ray diffraction In order to optimize growth conditions, a double-crystal XRD rocking curve was compared for GaAs/Ge/Si samples grown under different conditions. GaAs layers of 1 mm were grown on two samples cleaved from the same polished Ge/Si substrate. The upper curve in Fig. 4 was measured from a sample using a ‘‘standard’’ two-step growth recipe as illustrated in growth chart (a), where a low-temperature buffer layer is grown at 400 1C and a high-temperature upper layer is grown at 600 1C. The lower curve was measured from a sample with interrupted annealing process
3.3. SIMS analysis To determine the level of Ge diffusion and the as-grown doping profiles in GaAs, a doping-probe structure was grown for SIMS analysis. Fig. 5 shows SIMS profiles of a GaAs layer
Fig. 3. Room temperature PL comparison of 1 mm un-doped GaAs layer grown on exact (0 0 1) Ge substrate and on polished Ge/Si substrate via ART.
ω
0.1
3135
Fig. 5. SIMS profiles for GaAs grown on polished Ge/Si substrate. Ge layer was grown on exact (0 0 1) Si substrate via ART.
Ge: (ω) FWHM=198″
Si
0.0 GaAs: (ω) FWHM=248″
−0.1 −0.5
0.5 ω/2θ
0.0
a
1.0
1.5
b
Growth time Growth time 0.1 Si
ω
Ge: (ω) FWHM=137″ 0.0
−0.1
GaAs: (ω) FWHM=145″ −0.2
0.2
0.6
ω/2θ
1.0
1.4
Fig. 4. Double-crystal XRD rocking curve mapping of 1 mm GaAs samples grown on polished Ge/Si substrates. Upper results were measured from a sample grown using ‘‘standard’’ recipe as illustrated in chart (a). The lower results were measured from a sample with additional annealing steps during GaAs overgrowth as illustrated in chart (b).
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be observed after thermal annealing vs. samples grown without thermal annealing (not shown). As seen from Fig. 6(b), some of the defects originating from the Ge layer were terminated at the GaAs/Ge interface by annihilation or were inclined to the heterointerface. In addition, we have observed that the density of coalescence defects originating at the Ge/SiO2 interface was also reduced vs. non-thermally treated samples. It has been reported that deliberate post-growth thermal annealing of GaAs/Si materials enables misfit dislocation coalescence and annihilation due to GaAs dislocation movement under high temperature and thermal stress relaxation [13]. In addition, the level of defect reduction depends on the lattice-mismatched heterointerface orientation [14]. In this study, although no complicated annealing processes were conducted, we believe similar thermal annealing mechanisms found in GaAs/Si materials also apply to the GaAs/Ge/Si double heterostructure system. It should be noticed that the growth optimization of Ge on Si is the key to prevent Ge and overgrown GaAs layer from cracking. In this work, up to 5 mm crack-free Ge epilayers were achieved on 8 in Si (0 0 1) substrates via ART growth. After 2 mm GaAs overgrowth and thermal annealing, as shown in Fig. 4(b), no cracking has been observed on GaAs surface. These results suggest that further reduction of dislocation density in GaAs films on this virtual Ge/Si substrate could be realized with optimized post-growth or in-situ thermal treatment. In fact, high performance Esaki diodes [15] and MOSFET [16] devices based on this approach have been successfully demonstrated recently.
4. Conclusions
Fig. 6. Cross-section TEM images of GaAs/Ge/Si with SiO2-patterned trench/space ratio ¼ 1:2 (a) 1 mm GaAs grown on 1.7 mm polished Ge/Si substrate with annealing process and (b) close-up image of GaAs/Ge interface from the sample in (a).
grown under the same conditions as those described in Fig. 4(b) except with thicker GaAs layer, 2 mm. As shown in Fig. 5, the background Ge doping level dropped below 1 1017 cm3 during the first 200 nm of GaAs growth and was below the detection limit of 1 1016 cm3 after 450 nm of GaAs growth. Carbon contamination was also below detectable limits. Both n/p doping and oxygen contamination behaved very similar to those layers grown on GaAs substrates. The abrupt increases of Ge, Si, O and C at the sample surface, showed in Fig. 5, are SIMS process artifacts.
3.4. Cross-section TEM analysis Fig. 6 shows cross-section TEM images of a sample grown under the same conditions as described in Fig. 4(b). Ge layer of 3 mm was first grown on SiO2-patterned Si (0 0 1) substrate with trench/space ratio ¼ 1:2. After CMP, 0.8 mm GaAs was grown on 1.7 mm Ge layer. From Fig. 6(a), a clear GaAs/Ge interface line can
We have demonstrated the feasibility of growing high-quality GaAs on polished Ge/Si (0 0 1) substrate using aspect ratio trapping method. The results indicate that polished ART Ge grown on exact (0 0 1) Si substrate can be used as a thin template layer for GaAs growth, a promising approach to developing OEIC-compatible, high-quality GaAs on Si substrate. We found that an optimized AlGaAs/GaAs buffer layer could effectively suppress Ge diffusion and reduce dislocation propagation. We attribute the significant APD reduction in GaAs layer to the nature of ART-based Ge growth, which results in a virtual off-cut Ge surface after CMP. Improved GaAs layer quality has been illustrated by introducing an interrupted thermal annealing step during GaAs growth. According to our investigation, it is concluded that the use of a combination of an optimal GaAs buffer layer and in-situ thermal annealing treatment lead to further improvement of GaAs or other III–V material quality grown on Si (0 0 1) substrates.
Acknowledgment The authors are grateful to the Sarnoff optoelectronic group for providing technical assistance in epitaxial growth. References [1] W.Y. Uen, Z.Y. Li, Y.C. Huang, M.C. Chen, T.N. Yang, S.M. Lan, C.H. Wu, H.F. Hong, G.C. Chi, J. Crystal Growth 295 (2006) 103. [2] Alex Chediak, Karen Scott, Peng Zhang, TICS 4, MSE 225, April 12, 2002. [3] S. Saravanan, K. Jeganathan, K. Baskar, T. Jimbo, T. Soga, M. Umeno, J. Crystal Growth 195 (1998) 23. [4] Y. Fukuda, Y. Kadota, Y. Ohmachi, Jpn. J. Appl. Phys. 27 (1988) 485. [5] K. Mizuguchi, N. Hayafuji, S. Ochi, T. Murotani, K. Fujikawa, J. Crystal Growth 77 (1986) 509. [6] M.E. Groenert, Arthur J. Pitera, R.J. Ram, E.A. Fitzgerald, J. Vac. Sci. Technol. B 21 (3) (2003) 1064.
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[7] A. Wan, V. Menon, S.R. Forrest, D. Wasserman, S.A. Lyon, A. Kahn, J. Vac. Sci. Technol. B 22 (4) (2004) 1893. [8] C.K. Chia, J.R. Dong, D.Z. Chi, A. Sridhara, A.S.W. Wong, M. Suryana, G.K. Dalapati, S.J. Chua, S.J. Lee, Appl. Phys. Lett. 92 (2008) 141905. [9] J.-S. Park, J. Bai, M. Curtin, B. Adekore, M. Carroll, A. Lochtefeld, Appl. Phys. Lett. 90 (2007) 05213. [10] J.Z. Li, J. Bai, J.-S. Park, B. Adekore, K. Fox, M. Carroll, A. Lochtefeld, Z. Shallenbarger, Appl. Phys. Lett. 91 (2007) 021114. [11] J.M. Hydrick, J.S. Park, J. Bai, C. Major, M. Curtin, J.G. Fiorenza, M. Carroll, A. Lochtefeld, ECS Trans. 16 (10) (2008) 237.
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[12] J. Bai, J.-S. Park, Z. Cheng, M. Curtin, B. Adekore, M. Carroll, A. Lochtefeld, Appl. Phys. Lett. 90 (2007) 101902. [13] M. Yamaguchi, A. Yamamoto, M. Tachikawa, Y. Itoh, M. Sugo, Appl. Phys. Lett. 53 (1988) 2295. [14] M. Tamura, T. Yodo, T. Saitoh, J. Palmer, J. Crystal Growth 150 (1995) 654–660. [15] S.L. Rommel, D. Pawlik, P. Thomas, M. Barth, K. Johnson, S.K. Kurinec, A. Seabaugh, Z. Cheng, J.Z. Li, J.S. Park, J.M. Hydrick, J. Bai, M. Carroll, J.G. Fiorenza, A. Lochtefeld, International Electron Devices Meeting, 2008, p. 739. [16] Y.Q. Wu, M. Xu, P.D. Ye, Z. Cheng, J. Li, J.S. Park, J. Hydrick, J. Bai, M. Carroll, J.G. Fiorenza, A. Lochtefeld, Appl. Phys. Lett. 93 (2008) 242106.
Contents lists available at ScienceDirect
Journal of Crystal Growth journal homepage: www.elsevier.com/locate/jcrysgro
Growth and characterization of GaAs layers on polished Ge/Si by selective aspect ratio trapping J.Z. Li , J. Bai, J.M. Hydrick, J.S. Park, C. Major, M. Carroll, J.G. Fiorenza, A. Lochtefeld AmberWave Systems Corporation, 13 Garabedian Drive, Salem, NH 03079, USA
a r t i c l e in fo
abstract
Article history: Received 3 October 2008 Received in revised form 5 March 2009 Accepted 11 March 2009 Communicated by D.W. Shaw Available online 24 March 2009
Epitaxial GaAs layers have been deposited on polished Ge film grown on exactly (0 0 1) oriented Si substrate by metal-organic chemical vapor deposition (MOCVD) via aspect ratio trapping (ART) method. Double-crystal X-ray diffraction shows that the full-width at half-maximum (FWHM) of the (4 0 0) reflection obtained from 1 mm GaAs is 140 arcsec. Scanning electron microscopy (SEM) of the GaAs layer surface shows that the amount of antiphase domain defects (APD) raised from GaAs/Ge interface using Ge ART on Si is dramatically reduced compared to GaAs layers grown on exact (0 0 1) Ge substrate. Defect reduction and Ge diffusion at vicinal GaAs/Ge interface were investigated via cross-section transmission electron microscopy (X-TEM) and secondary ion mass spectrometry (SIMS). Film morphology and optical properties were evaluated via SEM and room temperature photoluminescence (PL). & 2009 Elsevier B.V. All rights reserved.
PACS: 81.05.Ea 81.15.Gh 78.55.Cr 71.55.Eq 73.40.Kp Keywords: A1. Defects A2. III–V on Si A3. Aspect ratio trapping A3. Metal-organic chemical vapor deposition B1. Gallium compounds
1. Introduction Monolithic integration of III–V optoelectronic materials onto elemental semiconductors such as Si and Ge has attracted a great deal of interest for decades in the hope of taking advantages of each material’s superiorities. Among those approaches, epitaxial growth of GaAs on Si has been the most extensively investigated subject. Although some progress has been reported [1–3], device quality of GaAs on Si has not materialized at the commercial level due to large mismatch in lattice constants and thermal expansion coefficients between GaAs and Si. Considering the actual material growth cost and the processing limit in practically realizing optoelectronic integrated circuits (OEIC) on Si substrates, growth of high-quality GaAs with minimal transitional buffer layer thickness on exact oriented (0 0 1) Si substrate platform is desired. Since Ge has a lattice constant very close to that of GaAs, with a mismatch of only 0.07%, much lower than the 4.1% mismatch between GaAs and Si, growth of virtual Ge/Si substrate followed
Corresponding author. Tel.: +1 603 870 8675.
E-mail address: [email protected] (J.Z. Li). 0022-0248/$ - see front matter & 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.jcrysgro.2009.03.018
by GaAs growth is a promising growth option. To date, several groups have reported on the growth of GaAs layers on Ge/Si substrates [4–6]. However, these GaAs layers have had rather higher dislocation density or involve a very thick Ge-containing buffer layer. The inferiority of these GaAs layers grown on Ge/Si is mainly due to the poor crystalline quality of the Ge buffer layers. Thus, the Ge crystalline quality must be improved in order to grow high-quality GaAs layers on Ge/Si. On the other hand, the common and principal difficulty in growing polar GaAs on nonpolar Ge is the creation of antiphase domain (APD) defects in GaAs layers. It has been reported that an effective way to obtain single domain GaAs is growing GaAs on off-cut Ge (0 0 1) substrates [7,8]. Thus, when using Ge/Si as a virtual substrate, the starting substrate would need to be an off-cut Si (0 0 1). However, this may not be an ideal solution for OEIC processes, for which exact (0 0 1) Si substrates have been the platform of choice. Previously, the authors have demonstrated an effective approach to GaAs heterointegration by using MOCVD via the aspect ratio trapping method to reduce threading dislocations during Ge and GaAs growth on exact (0 0 1) Si substrates [9,10]. Here, we demonstrate the growth and characterization of GaAs layers on such a Ge/Si template, where the Ge layer is coalesced and polished
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by chemical mechanical polishing (CMP), to serve as a buffer layer between GaAs and Si. The film quality of overgrown GaAs was inspected with SEM, SIMS, room temperature PL and X-TEM.
2. Experimental procedure Two-step low-pressure MOCVD processes were performed for GaAs/Ge/Si growth. A cross-sectional SEM image in Fig. 1 shows the layer structure. First, 2–3 mm coalesced Ge layer was grown by using MOCVD on exact (0 0 1) Si substrates with trench-patterned thermal SiO2 on the Si surface. Details of the Ge growth procedure and material characterization are described in Ref. [9]. After Ge growth, Ge layer was polished via chemical mechanical polishing to a thickness of about 1–1.5 mm. The CMP process is described in Ref. [11]. A mirror-like Ge surface was obtained with an etch pit density (EPD) level in the mid-106/cm2 range. Before GaAs overgrowth, the polished Ge/Si substrate was cleaned with successive dips in H2O2 solution and 1:50 diluted hydrofluoric acid (HF), with deionized water rinses between steps. A final dip in the HF solution left the Ge surface hydrophobic prior to loading in the MOCVD reactor. In the second step, GaAs layers were grown in a separate MOCVD reactor at a constant low pressure (70 Torr) by using triethylgallium (TEG) and arsine (AsH3) for buffer layer growth and trimethylgallium (TMG) and AsH3 for upper GaAs layer growth. Prior to buffer layer growth, the wafer was baked at 680 1C for 10 min under H2 overpressure followed by 2 min Ascoating by introducing AsH3 overpressure. An optimized threeperiod GaAs (10 nm)/Al0.40Ga0.6As (15 nm) superlattice buffer layer structure was grown at temperature of 600 1C. Finally, 1 mm GaAs layer was grown at temperature of 600 1C with an optimized annealing process. In addition, p- and n-type doping were investigated by using carbon tetrabromide and SiH3 during GaAs layer growth, respectively. The growth rates were kept at 7 nm/min for the buffer layer and at 50 nm/min for the top layer. In order to monitor any growth condition variation, a blanket GaAs (0 0 1) substrate and a blanket Ge (0 0 1) substrate were used in each growth run, in addition to the Ge virtual substrate.
substrate via ART are shown in Fig. 2(a) and (b), respectively. Clearly, a commonly seen high-density antiphase disordered network appeared in GaAs grown on exact (0 0 1) Ge substrate, while very few APD defects were observed for GaAs on Ge/Si in Fig. 2(b). A possible explanation for the APD reduction is related to the crystallographic growth behavior of the Ge buffer layer. It has been demonstrated that (11 3) facets are primarily formed during initial Ge growth inside the trenched area [12]. As the Ge film grows above the SiO2 mask, a coalesced wavy Ge growth front is formed, and faceting orientation gradually change from (11 3) to (0 0 1). Therefore, in the vicinity of coalesced Ge region, the aspolished Ge surface may have miss-oriented facets in a periodically modulated fashion, which would provide equivalent off-cut surface feature and lead to suppressed APD formation in the overgrown GaAs layers. In fact, further investigations indicated that the density of APD in overgrown GaAs layers decreases with increasing CMP depth. In other words, after CMP, a thinner Ge layer above the SiO2 patterning leads to higher GaAs overgrowth quality, which supports the above explanation.
3. Results and discussion 3.1. Surface morphology and room temperature PL Under the same growth conditions, mirror-like surfaces were observed from samples grown on the GaAs substrate and polished Ge/Si substrate while hazy GaAs surface was observed on the sample grown on the Ge substrate. SEM surface images of GaAs grown on exact (0 0 1) Ge substrate and on polished Ge/Si
Fig. 1. Cross-section SEM image of GaAs overgrown on polished Ge film grown on SiO2 trench patterned Si (0 0 1) substrate.
Fig. 2. Surface SEM images of GaAs samples grown in the same run: (a) grown on exact oriented (0 0 1) Ge substrate and (b) grown on polished Ge/Si substrate via ART.
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Shown in Fig. 3 are the room temperature PL results for the samples of Fig. 2. Both PL spectrums show a clean band gap emission at 867 nm, indicating no Ge-based complexes were formed inside the GaAs layer. This is confirmed by the SIMS profile in Fig. 5. However, the PL intensity for the GaAs layer grown on Ge/Si substrate is about 5 times higher than that of GaAs grown on exact (0 0 1) Ge substrate, which is attributed to the APD reduction in the GaAs/Ge/Si ART structure.
during GaAs overgrowth. As shown in growth chart (b), after growing 100 nm GaAs on top of the low-temperature buffer layer, the growth temperature was elevated up to 720 1C and annealed for 10 min under AsH3 overpressure with small TMG flow rate. After 10 min, the growth temperature was cooled to 300 1C, and then immediately ramped back up to 600 1C for the remaining upper GaAs layer growth. It is found that introducing such an insitu thermal annealing step during GaAs growth improves both GaAs layer and Ge layer crystalline quality. As seen from Fig. 4, the full-width at half-maximum (FWHM) of the XRD o angle for GaAs decreased from 248 to 145 arcsec and the FWHM for the Ge layer also decreased, from 198 to 137 arcsec.
3.2. Double-crystal X-ray diffraction In order to optimize growth conditions, a double-crystal XRD rocking curve was compared for GaAs/Ge/Si samples grown under different conditions. GaAs layers of 1 mm were grown on two samples cleaved from the same polished Ge/Si substrate. The upper curve in Fig. 4 was measured from a sample using a ‘‘standard’’ two-step growth recipe as illustrated in growth chart (a), where a low-temperature buffer layer is grown at 400 1C and a high-temperature upper layer is grown at 600 1C. The lower curve was measured from a sample with interrupted annealing process
3.3. SIMS analysis To determine the level of Ge diffusion and the as-grown doping profiles in GaAs, a doping-probe structure was grown for SIMS analysis. Fig. 5 shows SIMS profiles of a GaAs layer
Fig. 3. Room temperature PL comparison of 1 mm un-doped GaAs layer grown on exact (0 0 1) Ge substrate and on polished Ge/Si substrate via ART.
ω
0.1
3135
Fig. 5. SIMS profiles for GaAs grown on polished Ge/Si substrate. Ge layer was grown on exact (0 0 1) Si substrate via ART.
Ge: (ω) FWHM=198″
Si
0.0 GaAs: (ω) FWHM=248″
−0.1 −0.5
0.5 ω/2θ
0.0
a
1.0
1.5
b
Growth time Growth time 0.1 Si
ω
Ge: (ω) FWHM=137″ 0.0
−0.1
GaAs: (ω) FWHM=145″ −0.2
0.2
0.6
ω/2θ
1.0
1.4
Fig. 4. Double-crystal XRD rocking curve mapping of 1 mm GaAs samples grown on polished Ge/Si substrates. Upper results were measured from a sample grown using ‘‘standard’’ recipe as illustrated in chart (a). The lower results were measured from a sample with additional annealing steps during GaAs overgrowth as illustrated in chart (b).
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be observed after thermal annealing vs. samples grown without thermal annealing (not shown). As seen from Fig. 6(b), some of the defects originating from the Ge layer were terminated at the GaAs/Ge interface by annihilation or were inclined to the heterointerface. In addition, we have observed that the density of coalescence defects originating at the Ge/SiO2 interface was also reduced vs. non-thermally treated samples. It has been reported that deliberate post-growth thermal annealing of GaAs/Si materials enables misfit dislocation coalescence and annihilation due to GaAs dislocation movement under high temperature and thermal stress relaxation [13]. In addition, the level of defect reduction depends on the lattice-mismatched heterointerface orientation [14]. In this study, although no complicated annealing processes were conducted, we believe similar thermal annealing mechanisms found in GaAs/Si materials also apply to the GaAs/Ge/Si double heterostructure system. It should be noticed that the growth optimization of Ge on Si is the key to prevent Ge and overgrown GaAs layer from cracking. In this work, up to 5 mm crack-free Ge epilayers were achieved on 8 in Si (0 0 1) substrates via ART growth. After 2 mm GaAs overgrowth and thermal annealing, as shown in Fig. 4(b), no cracking has been observed on GaAs surface. These results suggest that further reduction of dislocation density in GaAs films on this virtual Ge/Si substrate could be realized with optimized post-growth or in-situ thermal treatment. In fact, high performance Esaki diodes [15] and MOSFET [16] devices based on this approach have been successfully demonstrated recently.
4. Conclusions
Fig. 6. Cross-section TEM images of GaAs/Ge/Si with SiO2-patterned trench/space ratio ¼ 1:2 (a) 1 mm GaAs grown on 1.7 mm polished Ge/Si substrate with annealing process and (b) close-up image of GaAs/Ge interface from the sample in (a).
grown under the same conditions as those described in Fig. 4(b) except with thicker GaAs layer, 2 mm. As shown in Fig. 5, the background Ge doping level dropped below 1 1017 cm3 during the first 200 nm of GaAs growth and was below the detection limit of 1 1016 cm3 after 450 nm of GaAs growth. Carbon contamination was also below detectable limits. Both n/p doping and oxygen contamination behaved very similar to those layers grown on GaAs substrates. The abrupt increases of Ge, Si, O and C at the sample surface, showed in Fig. 5, are SIMS process artifacts.
3.4. Cross-section TEM analysis Fig. 6 shows cross-section TEM images of a sample grown under the same conditions as described in Fig. 4(b). Ge layer of 3 mm was first grown on SiO2-patterned Si (0 0 1) substrate with trench/space ratio ¼ 1:2. After CMP, 0.8 mm GaAs was grown on 1.7 mm Ge layer. From Fig. 6(a), a clear GaAs/Ge interface line can
We have demonstrated the feasibility of growing high-quality GaAs on polished Ge/Si (0 0 1) substrate using aspect ratio trapping method. The results indicate that polished ART Ge grown on exact (0 0 1) Si substrate can be used as a thin template layer for GaAs growth, a promising approach to developing OEIC-compatible, high-quality GaAs on Si substrate. We found that an optimized AlGaAs/GaAs buffer layer could effectively suppress Ge diffusion and reduce dislocation propagation. We attribute the significant APD reduction in GaAs layer to the nature of ART-based Ge growth, which results in a virtual off-cut Ge surface after CMP. Improved GaAs layer quality has been illustrated by introducing an interrupted thermal annealing step during GaAs growth. According to our investigation, it is concluded that the use of a combination of an optimal GaAs buffer layer and in-situ thermal annealing treatment lead to further improvement of GaAs or other III–V material quality grown on Si (0 0 1) substrates.
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