SIAR: Customized real-time interactive router for analog circuits

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SIAR: Customized real-time interactive router for analog circuits$ Hailong Yao a,n, Fan Yang a, Yici Cai a, Qiang Zhou a, Chiu-Wing Sham b a b

Department of Computer Science and Technology, Tsinghua University, China The Hong Kong Polytechnic University, Hong Kong

art ic l e i nf o

a b s t r a c t

Article history: Received 11 March 2013 Received in revised form 21 March 2014 Accepted 21 March 2014

As analog and mixed-signal (AMS) circuitry gains increasing portions in modern SoCs, automatic analog routing is becoming more and more important. However, routing for analog circuits has always been an extremely challenging task due to complicated electrical and geometrical constraints. Due to these constraints, current analog routers often fail to obtain a routing solution that the designer wants. To incorporate the designer's expertise during routing, a customized real-time interactive analog router is attracting increasing concerns in industry. This paper presents a fast customized real-time interactive analog router called SIAR. A key feature of SIAR is that it allows for real-time interactions between the router and the designer. The designer can try different guiding points by moving the cursor in the user window and SIAR will return and display the corresponding routing solution in real-time, such that the designer could choose the most satisfactory one. The guiding points are very important for the designer to obtain satisfactory routing solutions, even for routing solutions with analog matching constraints by setting symmetric guiding points. A new splitting graph based routing model is presented to efficiently search the routing path and record the number of turns/vias during searching by efficient tile splitting operations. SIAR supports different routing modes such as point-to-point, point-to-module and module-to-module. An efficient connecting point selection method is presented such that an optimal routing solution is preserved when connecting to a module. Different design rules such as variable wire and via width/spacing rules, along with the same-net spacing rules, are supported in SIAR. Moreover, a global routing stage is presented to speedup the routing process for large designs. Experimental results are promising. & 2014 Elsevier B.V. All rights reserved.

Keywords: SIAR Interactive routing Analog routing Splitting graph Global routing

1. Introduction With the continuous advancement of IC manufacturing process, it is possible to fabricate analog and mixed-signal (AMS) circuits at 45 nm technology nodes and below [1], which boosts the AMS development and increases the portions of AMS parts in modern SoCs. This brings new challenges to analog design automation especially for analog routing. Routing for analog circuits has been a completely manual, time-consuming and error-prone task [2], which typically needs many iterations and becomes the bottleneck in the whole analog design flow. Automatic analog routing will greatly improve the designer's productivity and reduce the design cycle time. However, due to the complexity of the stringent analog

☆ A preliminary version of this work appeared in [22]. This work is supported in part by the National Natural Science Foundation of China (61106104 and 61274031), and by Doctoral Fund of Ministry of Education of China (20111011328). n Corresponding author. Tel.: +86 10 62795403; fax: +86 10 62781489. E-mail addresses: [email protected] (H. Yao), [email protected] (F. Yang), [email protected] (Y. Cai), [email protected] (Q. Zhou), [email protected] (C.-W. Sham).

routing constraints and the pursuit of high circuit performance, pure automatic router does not perform so well for sensitive analog nets as it is for digital signal nets. That is, automatic analog router is not intelligent enough to handle all kinds of routing constraints and requirements properly. In most cases, the designer wants to guide the path searching process, especially for those sensitive analog nets, such as nets with electrical and/or geometrical matching constraints. Therefore, a customized real-time interactive analog router is attracting more and more concerns in industry, which enjoys both the routing efficiency and the merit of including designers' expertise. There have been some research works on analog design automation. In [3], the constraint-driven physical design is discussed. In [4], an area routing method is presented for analog circuits with performance cost and shielding using the tile-based routing model, which may suffer from low routing efficiency. Besides, it does not consider the design rules of vias, etc. In [5,6], analog placement and routing approaches are presented with symmetry constraints. In [7], a matching-based placement and routing system is presented using matching patterns. In [8,9], the current-driven routing methods are presented based on Steiner tree and terminal tree, respectively. In [10], an analog shielding

http://dx.doi.org/10.1016/j.vlsi.2014.03.001 0167-9260/& 2014 Elsevier B.V. All rights reserved.

Please cite this article as: H. Yao, et al., SIAR: Customized real-time interactive router for analog circuits, INTEGRATION, the VLSI journal (2014), http://dx.doi.org/10.1016/j.vlsi.2014.03.001i

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routing algorithm is presented by net classification to handle different performance requirements of different nets. Due to the importance of constraints in analog circuits, more and more designs start to adopt the constraint-driven methodology [3,11,12, 13,14]. However, few research works in literature are on the analog routing methods with real-time and interactive applications [19,20]. Most automatic analog routers adopt the gridless routing model because of its capability of dealing with variable line width and spacing rules. Generally, the gridless routing model can be categorized as implicit-connection-graph-based and tile-based according to different representations of the routing region. In [15], a connection graph is constructed by expanding all the obstacles and then extending the boundary lines of the obstacles. The boundaries may become too dense with the increase in the number of obstacles, which will greatly slow down the path searching process. In [16–18], the routing region is partitioned into rectangular shapes called “tiles”, where a tile can be either a space tile or a block tile. However, the total number of vias/turns within the tiles cannot be estimated accurately during the path searching process, thus resulting in a routing solution with unnecessary vias/turns. As is known that vias/turns should be reduced because they degrade the circuit performance and reliability. Therefore, the above two classes of routing methods either suffer from the runtime issue or generate degraded routing solutions. An interactive router can be regarded as a semi-automatic router which allows the designer to guide the path searching process using guiding points. A guiding point can be input by a cursor as the designer moves or clicks the mouse in the user window. The designer typically wants to try different guiding points to find the most satisfactory routing path. A guiding point is very important to the designer especially for sensitive net with electrical and/or geometrical matching constraints. An efficient router that can respond in real-time is necessary in this context. Moreover, the designer may want to specify customized requirements for different nets before routing. These requirements include available routing layers, routing costs (e.g., unit cost for horizontal/vertical wires, cost for turns on each layer, cost for vias, etc.), and routing constraints such as line width, spacing, and the size of via arrays. This paper presents such a customized real-time interactive router called SIAR based on a new splitting graph. In SIAR, the routing efficiency is greatly improved based on the new splitting graph such that the designer can freely move the cursor and the computed optimal routing paths corresponding to the cursor positions are shown in real-time. SIAR greatly saves the designer from manual path connection tasks which is error-prone due to complicated design rules. In analog circuits, the pins of analog nets are typically rectilinear polygonal shapes (in this paper we call them modules). A path searching procedure from one module to another is called module-to-module routing. It is difficult to guarantee optimal routing solutions using the gridless routing model. The number of possible connection points of a module is theoretically infinite in gridless routing and the selected subset of connection points determine whether the optimal solution is preserved in the reduced solution space. This paper presents a method to choose a subset of connection points on a module such that at least one of the optimal routing paths to the module is available. That is, the solution space corresponding to the chosen subset of connection points contains at least one optimal routing solution. Moreover, SIAR considers more practical routing constraints. Typical design rules such as minimum line width, minimum line spacing, and rules for vias are all supported. Besides, the same-net spacing rule is also supported, which is one of the most important constraints for analog circuits. The same-net spacing rule is the

constraint for the minimum spacing between the net being routed and other same-net pre-routes. These pre-routes of the same net are considered as obstacles, though they are electrically equivalent to the current routing path. For example, when the user sequentially input several guiding points during routing, the accepted routing paths between previous guiding points are considered as the same-net pre-routes. These same-net pre-routes are considered as obstacles, and the same-net spacing rule should be guaranteed. SIAR deals with the same-net spacing constraint in the splitting graph construction procedure and guarantees the routing solution without design rule violations. In SIAR router, a new splitting-graph-based routing approach is presented, which guarantees to find an optimal routing solution considering the wirelength and the number of vias and/or turns, with enhanced routing efficiency. The main contributions are as follows:


A new splitting graph is proposed to represent the routing








region. During the path searching process, the tiles in the graph are efficiently split to record the number of vias/turns. Thus, an optimal routing solution is guaranteed with minimized vias/ turns. Module-to-point and module-to-module routing methods are proposed with an effective connection point selection method on the module boundaries. The connection point selection method ensures that an optimal routing solution exists. Effective methods are presented in SIAR to successfully handle different analog routing constraints including the same-net spacing constraint. A global routing stage with new gcell cost metrics is integrated to speedup SIAR router for large designs.

The rest of this paper is organized as follows. Section 2 gives an overview of SIAR router. Section 3 presents details of the splitting graph. Section 4 discusses the module-to-module routing. Section 5 covers the same-net spacing constraint. Section 6 presents the detailed searching process on the splitting graph. Section 7 presents the global routing stage for routing speedup. Section 8 gives the whole flow. Section 9 presents the experimental results. Section 10 concludes the paper with further research directions.

2. Overview of SIAR 2.1. Problem formulation For SIAR router, the input consists of the following parts: (1) user-specified routing source and target, which can be either modules or guiding points, (2) the routing layout data based on OA database [23], (3) the technology library with the default design rule constraints including minimum line width, minimum line spacing, via related design rules, the same-net spacing design rules, etc., and (4) customized input from User Interface including available routing layers, available vias with user-specified via enclosure values, customized line width and line spacing, and unit-length routing cost for horizontal and vertical routing directions on each routing layer. When the user specification is not valid, e.g., when the user-specified line width is less than the minimum design rule of the technology library, the values from the technology library are used. When all the input data are loaded and processed, the routing problem can be stated as follows: Input: (1) a set of rectilinear polygons and rectangles as the routing obstacles, (2) modules or points as the routing source and routing target, and (3) available routing layers and vias, along with

Please cite this article as: H. Yao, et al., SIAR: Customized real-time interactive router for analog circuits, INTEGRATION, the VLSI journal (2014), http://dx.doi.org/10.1016/j.vlsi.2014.03.001i

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the set of layer-specific and via-specific design rules and routing cost settings. Find: a routing path connecting source and target with minimized weighted sum of path length, the number of turns and the number of vias. Subject to: there are no design rule violations.

Import routing information

Construct splitting graph

2.2. Real-time interactive flow

Perform A* algorithm

SIAR provides an interactive Graphical User Interface (GUI) for the user. It allows the user to guide the path searching process using guiding points, which are input by the mouse cursor. The entire routing result is comprised of multiple sub-paths between sequential guiding points. When the user moves the cursor, the cursor point is set as the intermediate routing target and the router returns the routing result in real-time. In other words, the routing result updates in real-time with the cursor movement, which has critical requirements on the routing efficiency. Fig. 1 shows the real-time interactive routing flow. The user can interact with the routing process by single mouse click, double mouse click, mouse movement, the backspace key, etc. The left part of the figure shows the organization of SIAR which includes the router interface and the route engine. The router interface prepares routing information for the engine, where the information comes from either OA database [23] or User Interface. All the input data are synthesized and processed to populate the route engine. Then the routing engine starts path searching and returns the routing result to User Interface by Router interface. Besides, User Interface is responsible for storing the routing paths into the OA database.

As shown in Fig. 1, when all the routing information is determined by the router interface, the route engine starts, where a splitting graph is constructed. Module-to-module routing and the same-net spacing constraint are supported by special processing in the construction procedure. Then an improved An routing algorithm with tile splitting operations is performed on the graph. Finally, the routing result is returned. The overview of the route engine is shown in Fig. 2. The details of the route engine are presented in Section 8. Details of the routing algorithm is presented in the following sections. Table 1 shows the main notations used in the following paper.

User Interface Single click Routing information import

Routing starts Mouse move

Router interface Routing information update

Try different routings Single click Route engine Double click

Output routing result Fig. 2. Overview of the route engine.

Table 1 Notations. Notation

Meaning

S T gi nj vj wL wV sLL sLV sVV sn setH setV

Routing source Routing target The ith Hanan grid for routing The jth tile or splitting tile The jth vertex of a splitting tile The minimum line width Via diameter size The minimum line-to-line spacing The minimum line-to-via spacing Minimum via-to-via spacing Minimum same-net spacing The set of horizontal grid lines The set of vertical grid lines

3. Splitting graph

2.3. Overview of route engine

OA database

3

Current routing path is accepted, and next routing process starts The entire routing is finished

Fig. 1. Interactive flow.

Mouse move Backspace

3.1. Motivation Most analog routers adopt the gridless routing model because of its capability of dealing with variable line width and spacing rules. However, existing gridless routing methods either suffer from the runtime issues or obtain sub-optimal routing solutions in terms of wirelength and vias/turns. For example, the implicit-connectiongraph-based method suffers from inefficiency because that it constructs the graph by extending the boundaries of all obstacles, which will generate excessive searching points for large number of obstacles [15]. The searching procedure will slow down with the increasing number of points to be searched. The tile-based routing method has difficulty in counting the exact number of turns due to misalignment of the tiles so that it may not guarantee the optimal number of turns/ vias [17]. When a routing path changes its direction on the same routing layer, a turn is formed. When a routing path changes to a different routing layer, a via is formed. However, a turn may occur inside a tile and the router has no way to identify the turn. An example is shown in Fig. 3. Tile n0 is searched rightward to tile n1, and n1 is searched rightward to n2. The path always goes in the right direction without turns. That is, during the path searching process, the router does not know there is a turn from n0 to n2. However, because n0 and n2 are not aligned, a bend (i.e., a turn is formed) is necessary during the backtrace process. For different nets in a design, the designer may specify different wire and/or via width/spacing rules and different costs for turns and vias. Besides, for different routing layers, different routing costs can be assigned to preferred and non-preferred routing directions, respectively. A good analog router should be able to obtain a routing path with minimized total routing cost in realtime (e.g., no more than 2 s) under the constraints of pre-specified design rules. To the best of our knowledge, there is not such a good

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Fig. 3. Difficulty in couting the number of turns

Fig. 4. Construction of Hanan grids.

real-time interactive analog router. Therefore, in this paper, we present a new splitting graph, based on which a real-time efficient and effective analog router is developed for real applications. 3.2. Graph construction The splitting graph G(V, E) models the routing area with a set of splitting tiles, where each node in V represents a splitting tile and each edge in E represents the adjacency between the two corresponding splitting tiles. A splitting tile is the processing unit during the searching procedure, i.e., the number of splitting tiles needs to be decreased so as to speedup the path searching process. Splitting tiles are derived by the following steps. First, construct the Hanan grids. Then, determine the orientations of the Hanan grids. Finally, group the Hanan grids into splitting tiles according to their orientations. In the first step, the splitting graph uses zero-width wire model. As in [15], each obstacle is expanded with distance D1 and D2, respectively. Distance D1 corresponds to the space for general wires, while distance D2 corresponds to the space for vias. Assume all the obstacles are of polygonal shapes. And assume the minimum spacing rule between lines, between lines and vias, and between vias, are all different. For a non-via obstacle, D1 ¼wL/2þsLL, and D2 ¼wV/2þ sLV. Otherwise, for a via, D1 ¼wL/2þ sLV, and D2 ¼wV/2þsVV, where wL is the minimum line width, wV is the via diameter (the longer edge is used for non-square vias), sLL is the minimum line-to-line spacing, sLV is the minimum line-to-via spacing, and sVV is the minimum via-to-via spacing. The corresponding expanded obstacles are denoted by Ow and Ov, respectively. The boundaries of Ow and Ov extend until reaching the boundary of routing area, comprising the horizontal and vertical lines for available routing paths, as shown in Fig. 4. The set of horizontal lines and vertical lines are denoted by setH and setV, respectively. The intersection points between the lines are called Hanan grids. The second step is to determine the searching orientations of the Hanan grids. Hanan grids at the bounding box of Ow cannot search toward the obstacle on the same layer. This is to guarantee the minimum spacing design rule between the routing wire and the obstacle. Besides, Hanan grids inside box Ov cannot search to or from the adjacent routing layers, i.e., no vias can be inserted inside Ov. This is to guarantee the minimum spacing design rule between vias and the obstacle. We also mark the Hanan grids inside the obstacles as illegal for searching. The last step obtains the splitting tiles by grouping the Hanan grids with the same orientations (i.e., exactly the same searching directions). A splitting tile is a cluster of Hanan grids with the same orientations. Splitting tiles do not overlap with each other, and a Hanan grid can only belong to one splitting tile. A splitting tile is of a rectangular shape to facilitate the following tile splitting process and turn cost computation. Generally, each routing layer has a preferred routing direction. The Hanan grids along the preferred routing direction are grouped in higher priority, which possibly enables a fast searching

Fig. 5. Splitting graph with the preferred horizontal routing direction.

along the preferred routing direction. Fig. 5 shows an example of the splitting tile construction for Fig. 4. Assume the routing layer has horizontal preferred routing direction. Then the grouping process starts with the Hanan grid on the top left corner, and continues to merge rightward until reaching a Hanan grid with a different orientation. Here, we separate source/target grids from ordinary grids. Therefore, when reaching source grid S, a line-shape splitting tile is obtained. Then the line-shape splitting tile is swept downward to group segments of Hanan grids until reaching any Hanan grid with a different orientation. Thus a splitting tile is obtained (i.e., n1 in Fig. 5). The Hanan grids without a group are visited first from left to right, and then from top to bottom, until all the grids are grouped. Thus, the second grouped tile is n2. The tile numbers in Fig. 5 give the grouping order. The orientation of the splitting tile is assigned to be any of the Hanan grids it covers. Since all the Hanan grids in the splitting tile have the same orientation, the splitting tile can be regarded as a single searching unit during the path searching process. Note that in Fig. 5, Hanan grids g1 and g2 have different orientations, i.e., g1 can search in any direction, while g2 is forbidden to search upward or downward (due to the via spacing design rule) because it is inside the expanded obstacle Ov. Besides, n5 cannot search to “SOUTH” due to the obstacle. Then the horizontal grouping process terminates at g1. Thus, splitting tile n4 is formed. Two splitting tiles are regarded as adjacent if and only if they have adjacent Hanan grids. 3.3. Tile splitting Since the splitting tiles may not be aligned either horizontally or vertically, it is difficult to check whether a turn occurs during the searching process, as discussed in Section 3.1. As a result, the number of turns cannot be recorded for choosing the best routing path. We present the tile splitting operation to solve this problem. As shown in

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are grouped into a new sub-tile. The remaining Hanan grids are grouped into several rectangular shapes. All the Hanan grids in each rectangular shape are grouped into a new sub-tile. The subtiles do not overlap with each other, and the border of each subtile is derived according to the set of horizontal lines setH and vertical lines setV. For example, assume a searching process from ni to nj in the vertical direction. When tile nj is being split, the middle sub-tile has the vertical border lines aligned with ni. Assume the left and right borders of ni are the lth and mth elements in setV, respectively. Then the right border of the left sub-tile is setV(l  1), and the left border of the right sub-tile is setV(m þ1). Since the Hanan grids are discrete, there are gaps between the new adjacent sub-tiles. Note that in Fig. 7, some sub-tiles may not exist when ni and nj are aligned. As an example, in Fig. 6, n6 is split into two subtiles because n6 is aligned to n3 on the right boundary. Fig. 6. Splitting tiles not aligned cause difficulties in counting bends.

4. Module-to-module routing

Fig. 7. Tile splitting operation.

Fig. 5, one possible tile path connecting source S and target T is “Sn3-n6-n9-n11-T”. Because the search directions are all “downward” in the first few steps and then finally “leftward”, the number of turns estimated during searching is 1. However, it is obvious that there will be at least 3 turns following the path in Fig. 5. The problem is brought in by the searching step from n3 to n6, where only the right part of the Hanan grids in n6 can be directly visited from n3 without causing turns. Thus, to solve the problem, n6 needs to be split during the searching step “n3-n6”. Then two searching steps “n3-n(2) 6 ” and (1) “n(2) 6 -n6 ” are actually needed as shown in Fig. 6. After splitting n6, a better routing path with only 2 turns can be found by further splitting (1) (1) (2) n8, i.e., “S-n3-n(2) 6 -n6 -n8 -n8 -T”. Generally, for a searching step from tile ni to nj, nj needs splitting according to the searching direction and the width of direct path “ninj”. Here direct means no turns or vias. If the searching direction is one of the four orientations, i.e., “NORTH”, “SOUTH”, “WEST” and “EAST”, on the same routing layer, then nj will be split into at most three subsplitting-tiles (sub-tiles in short). If ni searches to nj on an adjacent routing layer, nj will be split into at most five sub-splitting-tiles. Tile splitting is performed according to the overlapping area of ni and nj along the searching direction. Fig. 7 shows the tile splitting operation. As mentioned before, a splitting tile is a group of Hanan grids in rectangular shape. When searching from tile ni to nj, nj will be split as follows. Tile ni is projected onto tile nj, and all the Hanan grids in the projected area

Module-to-module routing means that the routing source and target are not points but polygonal shapes called modules. Since the path searching unit is a splitting tile, the source and target must be splitting tiles, too. The key idea for module-to-module routing is to first transform a module into a set of Hanan grids (called source/target Hanan grids), and then group the Hanan grids into splitting tiles, i.e., a list of source splitting tiles and a list of target splitting tiles. As mentioned before, the set of vertical lines setV and horizontal lines setH contain all the available routing paths. Some of these lines intersect with the boundaries of the source and target modules. Besides, some intersection points of setV and setH may fall inside the two modules. In single layer routing, the routing path may walk along these lines and connect to source/target module at the intersection points on the module boundaries. Therefore, the intersection points should be added into the list of source/target Hanan grids. In multi-layer routing, the routing path may connect to the inner region of the module rather than the boundaries from the adjacent layer. So the list of source/target Hanan grids should also include the Hanan grids at the intersection points of setV and setH inside the module. Besides the above mentioned scenarios, it is possible for the shortest path to connect to the corners of the module when the source module and the target module do not overlap each other either horizontally or vertically. For example, when the target module is to the bottom right of the source module, the shortest path should connect to the bottom right corner of the source module. So the Hanan grids at the corners of the module should be included in the list of source/target Hanan grids. According to the minimum design rule, any module must have the width and length not less than minimum feature size or line width. Therefore, Hanan grids at the corner of the source/target module should shift backward by half the line width from the border of module, as is shown in Fig. 8. The dashed lines derived by module shrinking are appended into setV and setH at the beginning of the splitting graph construction process. The above mentioned module processing method guarantees that at least one shortest path exist between the source and target Hanan grids. After the above-mentioned module processing, module-tomodule routing is transformed into grids-to-grids routing. To perform the path searching algorithm on splitting tiles, a list of splitting tiles are constructed from the Hanan grids of the source and target modules. Thus path searching algorithm begins with a list of splitting tiles and also terminates with a list of splitting tiles. At the beginning of searching algorithm, we calculate the cost for each tile in the source splitting-tile list, and insert it into a list which holds all the splitting tiles to be searched. Then

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Fig. 8. Hanan grid set for module-to-module routing.

the searching starts from multiple tiles simultaneously. The terminating condition is that at least one splitting tile in the list of the target splitting tiles is visited. Fig. 9. Same-net obstacles.

5. Same-net spacing constraint In the routing procedure, all the modules and pre-routes except source and target are considered as routing obstacles. However, these obstacles may belong to the same net as the routing path, that is, the obstacles are electrically equivalent with the path. Such obstacles are called the same-net obstacles. The path should stay away from the same-net obstacles with the minimum same-net spacing sn. These obstacles cannot be processed as general obstacles. Now we will explain the reason. In the design procedure, the designer always generates several rectangles to make up a polygon, as shown in Fig. 9. For a route starting from rectangle S, the electrically equivalent modules are the same-net obstacles, denoted by R1 and R2. The user specifies S as the source module, which means the connection point should fall on the boundary of S or inside S. R1 and R2 cannot block the way. So the overlap area of R1 and R2 with S should not be regarded as obstacles during routing. While the other parts must keep distance sn from routing path. To solve this problem, we can subtract S from R1 and R2, and consider the remaining parts of R1 and R2 as general obstacles with minimum line spacing sn. During splitting graph construction, all the obstacles are expanded with distance wL/2 þsLL to ensure the spacing between routing path and obstacles. Similarly, the same-net obstacles also need to be expanded with distance wL/2 þsn. However, the remaining parts of R1 and R2 after subtraction will block again due to the expansion. Therefore, we present to first expand source S with distance wL/2 þ sn and then subtract expanded S from R1 and R2. After that, we can expand the remaining parts of R1 and R2 for the splitting graph construction, which pays back the regions of extra subtraction. The entire routing result is composed of several routing paths determined by the guiding points. This result is encountered in other types of the same-net obstacles during the routing processes. As shown in Fig. 10, the path is “S-P1-P2-T”, where points P1 and P2 are the guiding points. When routing for the path “P1-P2”, the former accepted routing path “S-P1” is considered as a same-net obstacle. In this case, the start point P1 falls on the boundary of the former path, i.e., on the boundary of the same-net obstacle. As a result, the expanded obstacle will cover the source point P1 such that P1 will be blocked for routing. This problem can be solved similarly by the above-mentioned shape subtraction. The former accepted path “S-P1” is subtracted by a square shape centered at P1 of the size wL þ2  sn. And the remaining part is treated as general routing obstacles with minimum line spacing sn, as is shown in Fig. 10. In the interactive routing context, it is not common for a routing path to have the same-net spacing violation with itself during path searching. Therefore, in this paper we do

Fig. 10. Same-net obstacles.

not focus on the same-net spacing constraint for a routing path with itself, which is typically more complicated to solve.

6. Modified An searching algorithm In SIAR, we use the An searching algorithm to find the optimal routing path in the splitting graph. Since a splitting tile is a group of Hanan grids, its searching cost is not a single value but a range of values covering the costs of all the inside Hanan grids. This cost range is bounded by the costs of the vertices of splitting tile. Here a vertex of a splitting tile is defined as the corner Hanan grid of a rectangular splitting tile. For a degenerate splitting tile with one Hanan grid or a segment of Hanan grids, there are only one or two vertices. In the implementation, each vertex of a splitting tile records its position and the searching costs H, G, and F. The position of a vertex is the indices of the corresponding Hanan grid in setV and setH. Cost H represents the estimated (minimum) cost from current vertex to the target vertex(es), calculated as the minimum cost of all the weighted costs wirelength and turns/vias from current vertex to the vertex(es) of target splitting tiles. Cost G is the actual searching cost from source vertex(es) to current vertex, and cost F is the sum of H and G. We define the vertex with the minimum cost F among all the vertices of a splitting tile as the best vertex of the splitting tile. A splitting tile n has a cost Fn, which equals to the cost of its best vertex. Besides, a vertex also records its parent direction, in which it is visited from the prior vertex during the searching process. The path searching algorithm maintains an ordered list of all the splitting tiles sorted by cost Fn in a non-decreasing order. This list of splitting tiles has been visited but not searched in the An algorithm. The tile at the front of the list will be picked out and searched first. In the implementation, a heap data structure is typically used instead of the sorted list for better efficiency.

Please cite this article as: H. Yao, et al., SIAR: Customized real-time interactive router for analog circuits, INTEGRATION, the VLSI journal (2014), http://dx.doi.org/10.1016/j.vlsi.2014.03.001i

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The pseudo-code of a single An searching step is given in Algorithm 1. In the An searching process, the first splitting tile with minimum cost in the ordered list is picked out to propagate searching to its neighbors in all the six directions including “NORTH”, “SOUTH”, “WEST”, “EAST”, “UP”, and “DOWN”. If the original cost of the neighboring tile is not less than the updated cost, the searching step will be accepted. Otherwise, the searching step is discarded. Function Pre-calculate determines whether the searching step is accepted or not, according to whether the cost of tile n can be updated by that of ni. If the searching step is accepted, tile splitting will be performed on the neighboring tile if it is misaligned. And the costs of the resulting list of sub-tiles will be updated. These sub-tiles are inserted into the sorted list according to their costs Fn for the following search process. Function Update calculates and updates costs H, G, and F for each vertex of splitting tile nj and cost Fn of nj. The parent direction of each vertex is also updated according to its cost. The pseudo-code of function Update is given in Algorithm 2. The calculation of cost H for an arbitrary vertex vj is to choose the minimum cost among all the costs between vj and the vertices of every target splitting tile in tList. Cost G of any vertex vj is determined by the minimum cost from every vertex of ni, where ni is the parent splitting tile that vj is visited from. Finally, cost F for a vertex is the sum of costs G and H, and the searching cost Fn for a splitting tile is the minimum cost F of its vertices. Algorithm 1. Single searching step. INPUT: current splitting tile ni, and list of target splitting tiles tList OUTPUT: sub-splitting tiles with updated cost or NULL Initialize list to store sub-splitting tiles Foreach searching direction dir do Get neighbor list nbList of ni in dir Foreach splitting tile n in nbList do If Pre-calculate(ni, n, dir) ¼FALSE do continue; Perform tile splitting on n according to ni and dir, getting the list of sub-splitting tiles nList Foreach splitting tile nj in nList do Update(ni, nj, tList, dir); Insert nj into list; return list Algorithm 2. Update the costs. INPUT: Splitting tile ni, Splitting tile nj, list of target splitting tiles tList, searching direction dir OUTPUT: Updated cost, parent direction Foreach vertex vj of nj do If cost H for vj has not been calculated do Foreach splitting tile t in tList do Foreach vertex vt of splitting tile t do calculate distance d between vj and vt vj.cost H’minimum of d Foreach vertex vj of nj do Foreach vertex vi of ni do calculate distance d between vi and vj If dir avi.parentDirection d’(dþ turnCost); If vj.cost G 4minimum of d do vj.cost G’minimum of d; vj.parentDirection’dir; Foreach vertex vj of nj do vj.cost F’vj.cost G þvj.cost H; nj.costFn’minimum of vj.costF;

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7. Global routing speedup For large layouts, directly applying the An searching algorithm on the whole layout is time-consuming. Therefore, a global routing stage is introduced to accelerate the searching process. The global routing stage consists of three major steps as follows: (1) nonuniform global routing cell (gcell) construction, (2) global routing, and (3) routing frame construction. 7.1. Non-uniform gcell construction When the horizontal and vertical grid lines are obtained from obstacle expansion, the non-uniform grids are grouped into global routing cells. Each gcell is of rectangular shape consisting of M horizontal grids and N vertical grids. Because the sizes of horizontal and vertical grids are non-uniform, the constructed gcells are of different sizes. This is one of the key differences from traditional global routing for digital circuits. Fig. 11(a) shows an example of the gcell construction. In Fig. 11(a), each gcell consists of 5 horizontal grids and 5 vertical grids. In the experiments, M and N are both set to be 15. 7.2. Global routing with new gcell cost metrics When the gcells are constructed, global routing is performed to find a path composed of gcells. The An searching algorithm is used to find the global routing path with the minimum total cost. The cost of the global routing path consists of following two parts: (1) cost of the gcells, and (2) cost of the turns and vias. By storing the previous searching directions of each gcell, the An searching algorithm can record and compute the turn costs during the path searching process. The cost of the gcells is traditionally abstracted as the edge cost in the global routing graph [24,25]. It is well known that there is a big gap between global routing and detailed routing, i.e., due to the inaccurate routing resource estimation, the global routing may make wrong decisions which result in detailed routing failure. Unlike traditional global routing, to make more accurate routing resource estimation, we present new gcell cost metrics (ΨEP) including six parts corresponding to the six expanding directions (EP): (1) EP ¼NORTH, (2) EP¼SOUTH, (3) EP ¼WEST, (4) EP¼EAST, (5) EP¼ UP, and (6) EP ¼DOWN. The first four items are for the routing cost on the same routing layer, and the remaining two items are for routing to different layers (i.e., via cost). The routing cost computation is based on the following equation [25]: f ðxÞ ¼ 1 þ

h 1 þekx

ð1Þ

where x represents the available routing capacity in percentage. h and k are the user-specified parameters. In the experiments, h and k are set to be 10. The gcell cost (ΨEP where EP is NORTH, SOUTH, WEST, and EAST) is computed as follows:

ψEP ¼ dEP þ pitch

ðm þ 1Þ=2  1

∑

i¼0

αi f i

ð2Þ

where dEP is the expanded Manhattan distance, pitch is the routing pitch (i.e., minimum line width plus minimum line spacing), m represents the number of grids in the gcell along the expanding direction, i.e., N (vertical grids) for the directions NORTH and SOUTH, and M (horizontal grids) for the directions EAST and WEST. f i represents the routing cost of the ith grid line in the gcell. The grid line indices are counted from the boundaries inward to the center of the gcell. And f i is computed using Eq. (1). Fig. 12 shows an example. In the figure, for f 2 of ψ EP in the direction NORTH, the obstacle takes 3 out of the total 9 grids. Therefore, the available routing capacity x in Eq. (1) is 6/9 ¼66.7%. αi is the weighting

Please cite this article as: H. Yao, et al., SIAR: Customized real-time interactive router for analog circuits, INTEGRATION, the VLSI journal (2014), http://dx.doi.org/10.1016/j.vlsi.2014.03.001i

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Fig. 11. Global routing speedup. (a) Gcell construction, (b) Global routing, (c) Routing frame constaction and (d) Detailed routing.

Fig. 12. Gcell cost computation. (a) Gcell cost and (b) Weighting parameter ai

parameter, which is also computed by Eq. (1). The key idea of αi is shown in Fig. 12(b). In the figure, for the two obstacles blocking all the horizontal grids, O1 and O2 have different effects from the global routing side of view. O2 is apparently more critical for blocking the route to enter the gcell. However, O1 still leaves some routing resource for routing inside the gcell and making turns or vias. Based on the above observation, αi is assigned higher value for grid lines near the boundary, which is computed as follows:     mþ1 1 ð3Þ αi ¼ f i= 2 where f ðxÞ is computed using Eq. (1). The gcell cost of vias (ΨEP where EP is UP and DOWN) is directly computed as viaCost  f ðxÞ where f ðxÞ is computed by Eq. (1).

Finally, the total cost of routing path is computed as follows: EP2 EP1 ψ path ¼ ψ EP2 ∑ ðψ EP1 S þ gc þ ψ gc Þ þ ψ T þ φ gc A path

ð4Þ

where φ denotes the total cost of turns on the path, EP1 denotes the routing cost for expanding to the gcell center, EP2 denotes the routing cost for expanding from gcell center to the gcell boundary or to the gcell center on the adjacent routing layers. Subscripts S and T denote the source and target gcells, respectively. 7.3. Routing frame construction When the global route is computed, the routing frame is constructed. All the gcells off the global route are set as routing

Please cite this article as: H. Yao, et al., SIAR: Customized real-time interactive router for analog circuits, INTEGRATION, the VLSI journal (2014), http://dx.doi.org/10.1016/j.vlsi.2014.03.001i

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obstacles (see Fig. 11(c)). Then the detailed routing is performed on the constructed routing frame as shown in Fig. 11(d). In the experiments, the routing frame is further enlarged by one gcell distance to allow more solution space exploration. Note that the presented global routing method is more effective for multi-layer routing than for single-layer routing. Upon detailed routing failures, global rerouting is needed to find an alternative global route using the negotiation-based technique [26].

8. Flow of SIAR Fig. 13 gives the overall routing flow of SIAR. The input consists of the routing information, a set of design rules, and the cost configurations. The cost configurations are specified from a pop-up window of the user interface, which include the turn cost of each routing layer, the via costs, the unit-length routing cost for each routing direction on each layer, etc. First, all the horizontal and vertical lines are obtained. The sets of horizontal and vertical lines consist of following three parts: (1) general obstacle processing, (2) source/target module processing, and (3)

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same-net obstacles processing. Second, the Hanan grids are constructed according to the lines. Then the routing obstacles and orientations of these Hanan grids are marked. Third, an optional global routing stage is performed. Note that the global routing stage is only designed for large designs. For example, only when the horizontal and vertical grid lines exceed 1000, will the global routing stage be necessary. Finally, the Hanan grids (in the constructed global routing frame when global routing is included) are clustered into splitting tiles according to their orientations. After the splitting graph construction, the routing region is represented with a set of splitting tiles. Then the An searching algorithm is performed on the graph. The source and target modules are transformed into lists of tiles in the An searching algorithm. In each An searching step, SIAR picks out the tile with minimum cost from the sorted list which keeps all the splitting tiles to be visited. The tile's neighbors may need splitting if the neighbor and the current tile are not aligned. Then all the neighboring tiles are processed and the resulting sub-tiles from tile splitting are inserted into the sorted list. The searching process continues until at least one target splitting tile is reached and the route with the best cost is found, or the sorted list is empty. If the path searching process is

Fig. 13. Flow of SIAR.

Please cite this article as: H. Yao, et al., SIAR: Customized real-time interactive router for analog circuits, INTEGRATION, the VLSI journal (2014), http://dx.doi.org/10.1016/j.vlsi.2014.03.001i

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routing areas by widths and lengths, “#L” gives the number of routing layers, “#obs.” gives the number of rectangular obstacles after fracturing the polygonal obstacles into rectangles, and “obs. ratio” gives the ratio of the area of all obstacles to the whole routing area. The columns under “Gridless” and “SIAR” give the routing results of the two routers, “CPU” gives the total runtime, “WL” gives the total wirelength, “#B” gives the number of turns, “#V” gives the number of vias, and “SU” gives the speedup of router SIAR compared to explicit-grid router variant [15]. For single-layer testcases, there are only turns in the routing solutions and the number of vias is 0. For multi-layer testcases, the number of turns may not be 0 because we allow both horizontal and vertical routing directions for each layer. The unit-length routing cost for each routing direction is set to 1. The cost of a turn is set to be a routing pitch and the cost of a via is 2  pitch for each layer. SIAR allows the user to set different costs for different routing directions to specify preferred routing directions on each routing layer. Because both routers use the same routing cost settings and searching

successful, the resulting path will be obtained during the backtrace process from the target. 9. Experimental results We have implemented the presented router SIAR in C þ þ with OA support [23]. SIAR is tested using the Linux server (3 GHz, 6 G memory) on a set of artificially generated testcases. The obstacles in the testcases are staggered with each other, which bring great complexities for routing. We also tested SIAR on some real analog testcases. But due to IP issues, we cannot disclose those results. We also note that most artificial testcases listed below are harder to route than real analog testcases, which better proves the effectiveness and efficiency of our router. Table 2 shows the results of SIAR (without global routing) vs. an explicit-grid routing version of Ref. [15]. In Table 2, the column under “Testcase” gives the names of testcases, “Size” gives the sizes of the

Table 2 Point-to-point routing results by SIAR router. Test-case

Single1 Single2 Single3 Single4 Single5 Multi1 Multi2 Multi3 Multi4

Size (μm2)

20  20 40  25 30  30 210  210 240  240 40  30 40  35 280  280 280  280

#L

1 1 1 1 1 2 3 3 3

#Obs.

Obs. ratio (%)

23 34 34 828 1034 117 91 424 724

46 34 32 52 30 25 19 9 11

Gridless [15]

SIAR

CPU (s)

CPU (s)

WL (μm)

#B

#V

SU

0.003999 0.013998 0.008999 0.369944 1.12983 0.647902 0.565915 90.9972 9.47756

0.003999 0.003999 0.004999 0.229965 0.634903 0.076989 0.083986 0.838873 0.896863

24.45 33.8 83.95 313.05 91.9 40 40.9 178.4 105.3

4 6 11 10 20 3 4 1 1

0 0 0 0 0 3 4 4 4

1.0  3.5  1.8  1.6  1.8  8.4  6.7  108.5  10.6 

#L ¼layer number, #obs. ¼number of obstacles, CPU¼runtime, WL¼ wirelength, #B¼ number of bends, #V ¼ number of vias, and SU ¼ speedup.

Fig. 14. Routing result by SIAR. (a) Point-to-Point routing result. (b) Module-to-Module routing result compared to Laker.

Table 3 Module-to-module routing results by SIAR router. Test-case

Single1 Single2 Single3 Single4 Single5 Multi1 Multi2 Multi3 Multi4

Gridless [15]

Laker

SIAR

CPU (s)

WL (μm)

#B

#V

CPU (s)

WL (μm)

#B

#V

CPU (s)

WL (μm)

#B

#V

SU1

SU2

0.007999 0.012998 0.007999 1.58876 3.51447 0.839872 0.684896 8.14476 121.464

17.785 32.1 82.2 298.9 88.2 38.3 39.2 97.1 174.4

2 6 10 10 20 3 4 1 0

0 0 0 0 0 3 4 2 4

0.19996 0.13998 0.12998 0.41994 0.8999 0.35994 0.34995 0.41993 0.67990

17.785 32.1 81.5 298.9 88.2 38.45 39.2 97.1 174.4

4 6 12 10 20 4 4 4 1

0 0 0 0 0 3 4 2 4

0.006998 0.004999 0.007999 0.318952 0.695894 0.111983 0.12998 1.18082 1.17483

17.785 32.1 82.2 298.9 88.2 38.3 39.2 97.1 174.4

2 6 10 10 20 3 4 1 0

0 0 0 0 0 3 4 2 4

1.1  2.6  1 5 5.1  7.5  5.3  6.9  103.4 

28.6  28  16.2  1.3  1.3  3.2  2.7  0.4  0.6 

CPU¼ runtime, WL¼wirelength, #B ¼number of bends, #V ¼number of vias, and SU ¼speedup.

Please cite this article as: H. Yao, et al., SIAR: Customized real-time interactive router for analog circuits, INTEGRATION, the VLSI journal (2014), http://dx.doi.org/10.1016/j.vlsi.2014.03.001i

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principles, the routing results are the same and omitted in the table. Note that the same routing results of the two routers prove that the optimal solutions are preserved using the new splitting graph method. From the experimental results, SIAR significantly improves the runtime with up to 108.5  speedup. For testcase Single1, runtime of SIAR does not improve due to the small number of obstacles so that clustering hardly produce large splitting tiles. While in Multi3, many staggered obstacles introduce dense Hanan grids and SIAR obtains great acceleration. Fig. 14(a) shows the routing results of SIAR on testcase Multi1. Table 3 shows the module-to-module routing results (without global routing). The testcases are the same as those used for point-topoint routing except that sources and targets are revised to polygons. Except the explicit-grid routing version [15], we also compare the results of SIAR with the commercial analog module-to-module router in Laker 3.2v3 [21]. The router in Laker adopts the tile-based routing model presented in [17] as mentioned in [7]. Note that the comparison between Laker and SIAR is kind of fair because SIAR also considers most of the analog design rules and both of them obtain similar routing results. “SU1” gives the speedup of SIAR over explicitgrid router, and “SU2” gives the speedup over Laker. From the results, SIAR obtains better solution quality in terms of wirelength and/or number of turns compared with the other two routers. Specifically, SIAR runs faster than the other two routers in most testcases with up

Fig. 15. Runtime speedup using global routing (GR).

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to 103.4  and 28.6  speedups, respectively. Note that Laker is a commercial router using tile model with acknowledged solution quality in industry. The comparison with Laker proves the efficiency and effectiveness of SIAR. The presented splitting graph model does improve the routing results considering the number of turns compared to the tile-based routing model. For Multi3 and Multi4, SIAR runs slower than Laker, but with improved solution quality (e.g., the number of turns is reduced from 4 to 1 for Multi3). For minimizing the number of turns, a splitting tile is typically smaller than a general tile [17] in size so that all turns/vias can be exactly estimated during the path searching process. But this may cost a little more time on searching, as for testcases Multi3 and Multi4. Fig. 14(b) shows the module-to-module routing results of testcase Single1 where the left figure is the routing result of Laker and the right figure is from SIAR. From the figure, the solution quality of SIAR is much better than Laker with reduced turns and exactly the same wirelength. Fig. 15 shows the runtime speedup by introducing the global routing stage. The testcases used for the figure are multi-layer cases with 3 routing layers. From the figure, the more number of obstacles, the more runtime is needed to finish routing both with global routing and without global routing. However, when the number of obstacles increases, the runtime reduction is also increased. The greatest speedup is more than 11 when the number of obstacles is 2618. From the results, with global routing integrated, SIAR router is more scalable for large layouts. Note that for multi-layer routing in analog circuits, our global routing solution typically corresponds to a valid detailed routing solution. And the quality of the routing solution is not degraded. However, for single-layer routing, a global routing solution may not correspond to a valid detailed routing solution. In this case, global rip-up and rerouting is needed with previously failed gcells penalized with higher routing cost [25]. Fig. 16 shows the snapshots of SIAR's user window. As shown in the figure, when the source module is selected, the routing result changes intermediately according to the movement of the cursor. The routing result starts from the source module, and router performs module-to-point routing if cursor moves in the empty region. Moduleto-module routing will be invoked when cursor falls in another module. The designer can choose the most satisfactory routing solution during the cursor movement. This is especially useful for routing nets with matching constraints. The last figure in Fig. 16 gives

Fig. 16. Routing result updates in real-time with the move of cursor.

Please cite this article as: H. Yao, et al., SIAR: Customized real-time interactive router for analog circuits, INTEGRATION, the VLSI journal (2014), http://dx.doi.org/10.1016/j.vlsi.2014.03.001i

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a result of the same-net constraint processing. The highlighted module is the source, and there are three pre-routed paths connected to the source which are the same-net obstacles. Current routing result comes out from the right boundary of source and stay away from the three same-net obstacles with the minimum distance 0.3 μm after leaving the source, where 0.3 μm is the value of the minimum same-net spacing constraint. The real-time interactions of SIAR greatly improve the user experience and introduce the designer's expertise to the semi-automatic design process.

10. Conclusion In this paper, a real-time interactive analog router called SIAR is presented. SIAR allows the designer to input guiding points for including the designer's expertise during design. Such guiding points are especially useful for routing sensitive nets with matching constraints. Based on a new splitting graph, SIAR can obtain a routing solution with minimized wirelength and number of vias/ turns. An effective module-to-module routing approach is also presented. Typical design constraints including the same-net constraints are all supported, which makes SIAR practical for real applications. Moreover, a global routing speedup is presented to make our method more scalable for large designs. Experimental results show notable improvements of SIAR in both solution quality and runtime compared with an existing work as well as the commercial router, which proves SIAR to be a promising realtime interactive analog router. Our future research includes the following: (1) extend the interactive router to multi-terminal net router for routing multi-terminal nets in one shot without interactions, (2) test SIAR on more industrial testcases, and (3) compare our algorithm with other state-of-the-art gridless routers. References [1] Cadence Design Systems, Inc., White Paper, Mixed-Signal Design Challenges and Requirements, 2009. [2] S. Piguet, F. Rahali, M. Declercq, M. Kayal, An analog-oriented routing tool for CMOS analog integrated circuits, in: Proceedings of the 15th European SolidState Circuits Conference, 1989, pp. 80–83. [3] G. Jerke, J. Lienig, Constraint-driven design: the next step towards analog design automation, in: Proceedings of the ISPD, 2009, pp. 75–82. [4] E. Malavasi, A. Sangiovanni-Vincentelli., Area routing for analog layout, IEEE Trans. Comput. Aided Des. 12 (8) (1993) 1186–1197. [5] Y. Yang, I.H.R. Jiang, Analog placement and global routing considering wiring symmetry, in: Proceedings of the ISQED, 2010, pp. 618–623. [6] P. Lin, S. Lin, Analog placement based on novel symmetry-island formulation, in: Proceedings of the DAC, 2007, pp. 465–470. [7] P. Lin, H. Yu, T. Tsai, S. Lin, A matching-based placement and routing system for analog design, in: Proceedings of the International Symposium on VLSI Design, Automation and Test, 2007, pp. 1–4. [8] T. Adler, H. Brocke, L. Hedrich, E. Barke, A current driven routing and verification methodology for analog applications, in: Proceedings of the DAC, 2000, pp. 385–389. [9] J. Lienig, G. Jerke, T. Adler, Electromigration avoidance in analog circuits: two methodologies for current-driven routing, in: Proceedings of the ASP-DAC, 2002, pp. 372–378. [10] Q. Gao, Y. Shen, Y. Cai, H. Yao, Analog circuit shielding routing algorithm based on net classification, in: Proceedings of the ISPLED, 2010, pp. 123–128. [11] C. Du, Y. Cai, X. Hong, Q. Zhou, A shortest-path-search algorithm with symmetric constraints for analog circuit routing, in: Proceedings of the ASICON, 2005, pp. 844–847. [12] E. Malavasi, U. Choudhury, A. Sangiovanni-Vincentelli, A routing methodology for analog integrated circuits, in: Proceedings of the ICCAD, 1990, pp. 202–205. [13] A. Nassaj, J. Lienig, G. Jerke, A new methodology for constraint-driven layout design of analog circuits, in: Proceedings of the International Conference on Electronics, Circuits, and Systems, 2009, pp. 996–999. [14] C. Du, Y. Cai, X. Hong, A novel analog routing algorithm with constraints of variable wire widths, in: Proceedings of the ICCCS, 2006, pp. 2459–2463. [15] J. Cong, J. Fang, K. Khoo, An implicit connection graph maze routing algorithm for ECO routing, in: Proceedings of the ICCAD, 1999, pp. 163–167. [16] A. Margarino, A. Romano, A. De Gloria, F. Curatelli, P. Antognetti, A tileexpansion router, IEEE Trans. Comput. Aided Des. 6 (4) (1987) 507–517. [17] J. Dion, L.M. Monier, A tile-based gridless router, Western Research Laboratory Research Rep95/3, Western Res. Lab., Palo Alto.

[18] Y.L. Li, H.Y. Chen, C.T. Lin, NEMO: a new implicit-connection-graph-based gridless router with multilayer planes and pseudo tile propagation, IEEE Trans. Comput. Aided Des. 26 (4) (2007) 705–718. [19] G.G.E. Gielen, R.A. Rutenbar. Computer-aided design of analog and mixedsignal integrated circuits, in: Proceedings of the IEEE, 2000, pp. 1825–1854. [20] M.G.R. Degrauwe, O. Nys, E. Dijkstra, IDAC: an interactive design tool for analog CMOS circuits, IEEE J. Solid-State Circuits 22 (6) (1987) 1106–1116. [21] Laker User Manual, SpringSoft Inc. 〈http://www.springsoft.com〉. [22] F. Yang, H. Yao, Q. Zhou, Y. Cai, SIAR: splitting-graph-based interactive analog router, in: Proceedings of the GLSVLSI, 2011, pp. 367–370. [23] Silicon Integration Initiative, Inc, Si2 OpenAccess API Tutorial, Ninth edition. 〈http://www.si2.org/?page=414〉. [24] J. Hu, S.S. Sapatnekar, A survey on multi-net global routing for integrated circuits,, Integr.: VLSI J. 31 (1) (2001) 1–49. [25] M. Pan, C. Chu, FastRoute: a step to integrate global routing into placement, in: Proceedings of the ICCAD, 2006, pp. 464–471. [26] L. McMurchie, C. Ebeling, PathFinder: a negotiation-based performance-driven router for FPGAs, in: Proceedings of the International ACM Symposium on Field-Programmable Gate Arrays, 1995, pp. 111–117.

Dr. Haiong Yao received B.S. degree in computer science and technology from Tianjin University, P.R. China in 2002, received M.S. and Ph.D. degree in computer science and technology from Tsinghua University, P.R. China in 2007. From 2007 to 2009, he was a Post-Doctoral Research Scholar with the Department of Computer Science and Engineering, University of California at San Diego. Since 2009, he has been an assistant professor with the Department of Computer Science and Technology, Tsinghua University. His research interests include very large scale integration physical design, design-manufacturing interface, analog routing, microfluidic biochips, etc. Dr. Yao has published over 30 journal and conference papers. He received two Best Paper Nominations at ICCAD in 2006 and 2008, respectively. He received one ISQED Best Paper Nomination in 2011.

Yang Fan received B.S. degree in Computer Science and Technology from Tsinghua University, Beijing, China in 2008, received M.S. degree in Computer Science and Technology from Tsinghua University, Beijing, China in 2011. Her research interests concentrate on the routing algorithms for VLSI integrated circuits design.

Cai Yici received B.S degree in Electronic Engineering from Tsinghua University, Beijing, China in 1983, received M.S. degree in Computer Science and Technology from Tsinghua University, Beijing, China in 1986, and received Ph.D in Computer Science, University of Science & Technology of China, Hefei, China, in 2007. She has been a professor with the Department of Computer Science & Technology, Tsinghua University. Her research interests include design automation for VLSI integrated circuits algorithms and theory, power/ground distribution network analysis and optimization, high performance clock synthesis, low power physical design.

Qiang Zhou received B.S degree in Computer Science and Technology from University of Science and Technology of China in 1983, received M.S degree in Computer Science and Technology from Tsinghua University in 1986, and received PhD. in Control Theory and Control Engineering from Chinese University of Mining and Technology in 2002. He has been a professor in the Department of Computer Science and Technology, Tsinghua University. Beijing, China. His research interests include VLSI layout theory and algorithms.

Please cite this article as: H. Yao, et al., SIAR: Customized real-time interactive router for analog circuits, INTEGRATION, the VLSI journal (2014), http://dx.doi.org/10.1016/j.vlsi.2014.03.001i

H. Yao et al. / INTEGRATION, the VLSI journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎ Bruce Sham received the Bachelor degree (Computer Engineering) and MPhil. degree from the Chinese University of Hong Kong in 2000 and 2002 respectively, and received the PhD. degree from the same university in 2006. He began his research work on digital design during the final year project as an undergraduate which focused on improving the performance, reducing the logic complexity of the system and, hence, power consumption. He has worked as an Electronic Engineer on the FPGA applications of motion control system and system security with cryptography in ASM Pacific Technology Ltd (HK). During the years at the Hong Kong Polytechnic University, he has also engaged in various University projects for the commercialization of technology, in particular, a

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few optical communication projects which are in collaboration with Huawei. He also worked on physical design of VLSI design automation. He was invited to work at Synopsys, Inc (Shanghai) in the summer of 2005 as a Visiting Research Engineer.

Please cite this article as: H. Yao, et al., SIAR: Customized real-time interactive router for analog circuits, INTEGRATION, the VLSI journal (2014), http://dx.doi.org/10.1016/j.vlsi.2014.03.001i