- Email: [email protected]
SiO2 stacked tunneling dielectric
Microelectronics Reliability 49 (2009) 912–915
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
A study on the improved programming characteristics of flash memory with Si3N4/SiO2 stacked tunneling dielectric L. Liu a, J.P. Xu a,*, L.L. Chen a, P.T. Lai b,* a b
Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan 430074, People’s Republic of China Department of Electrical and Electronic Engineering, The University of Hong Kong, Pokfulam Road, Hong Kong, China
a r t i c l e
i n f o
Article history: Received 23 January 2009 Received in revised form 13 May 2009 Available online 21 June 2009
a b s t r a c t The programming characteristics of memories with different tunneling-layer structures (Si3N4, SiO2 and Si3N4/SiO2 stack) dielectrics are investigated using 2-D device simulator of MEDICI. It is theoretically confirmed that the memory with the SiO2/Si3N4 stacked tunneling layer exhibits better programming characteristics than ones with single tunneling layer of SiO2 or Si3N4 for programming by channel hot electron (CHE) injection. A 10-ls programming time with a threshold-voltage shift of 5 V can be obtained for the memory with SiO2/Si3N4 stacked tunneling layer at Vcg = 10 V and Vds = 3.3 V. This is attributed to the fact that the floating-gate voltage is close to drain voltage for the stacked tunneling dielectric (TD), and thus the CHE injection current is the largest. Furthermore, optimal substrate concentration is determined to be 5 1016–2 1017 cm 3, by considering a trade-off between the programming characteristics and power dissipation/lifetime of the devices. Lastly, the effects of interface states on the programming characteristics are investigated. Low interface-state density gives short programming time and small post-programming control-gate current. Ó 2009 Elsevier Ltd. All rights reserved.
1. Introduction New non-volatile memory technologies are pursued as candidates for the next generation memories due to its superb memory performance such as high speed, low power consumption, and high long-term reliability [1]. Especially the employment of high-permittivity (j) dielectrics in flash memory has recently attracted increasing attention. Usually, the dielectric with higher permittivity inherently has lower barrier height (uB, conduction-band difference between dielectric and Si substrate) [2]. So replacing tunnel oxide (TOX) by high-j TD is beneficial for enhancing carrier injection from substrate to the floating gate due to the smaller uB. However, taking the charge retention into consideration, the uB between the silicon substrate and the adopted high-j TDs should be larger than 1.5 eV to suppress the loss of floating gate charges through electron thermal emission [3]. So far, Si3N4 [4] and stacked Si3N4/SiO2 [5] dielectrics have been adopted as tunnel layer of the flash memory and good programming and erasing properties have been demonstrated. The programming efficiency of the stackedgate flash memory with high-j tunnel dielectric has been evaluated by 2-D MEDICI simulation [2]. Enhanced charge injection from the substrate through the high-j tunnel dielectric was confirmed by experimental results [5]. However, effects of substrate concentration on the performance of flash memories were seldom inves* Corresponding authors. E-mail addresses: [email protected] (J.P. Xu), [email protected] (P.T. Lai). 0026-2714/$ - see front matter Ó 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2009.05.010
tigated when different kinds of tunnel dielectrics were used. In this work, the programming characteristics of the memory with stacked Si3N4/SiO2 as tunnel layer and its dependences on substrate concentration are theoretically investigated by means of the 2-D device simulator MEDICI. Simulated results show its excellent programming properties compared to memories with SiO2 or Si3N4 as the tunneling layer. Furthermore, suitable substrate concentration is determined by considering a trade-off between the programming characteristics and power dissipation/lifetime of the devices for the memory with stacked Si3N4/SiO2 as tunneling layer. 2. Device model The device structure of the n-channel floating-gate memory is shown in Fig. 1. The channel length is fixed to be 0.5 lm. The thickness of the blocking oxide between the control-gate electrode and the floating gate is 20 nm. The n+ floating gate thickness is 25 nm. The tunneling layer is SiO2, Si3N4, or stacked Si3N4/SiO2, with a physical thickness of 10 nm. The thickness ratio for the Si3N4/ SiO2 stacked structure is varied from 4/6 nm to 7/3 nm. The source/drain concentration is 3 1019 cm 3. Programming of the devices is achieved by channel hot electron (CHE) injection at Vcg = 10 V and Vds = 3.3 V (Vcg is control-gate voltage and Vds is drain–source voltage). The initial value of the programming time is set to be 10 9 s. The programming properties are characterized as a function of the substrate concentration.
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L. Liu et al. / Microelectronics Reliability 49 (2009) 912–915
4.0
SiO2
Floating Gate Voltage (V)
3.8 3.6
Si3N4/SiO2(4/6) 3.4
Si3N4/SiO2(5/5) Si3N4/SiO2(6/4)
3.2
Si3N4/SiO2(7/3)
3.0
Si3N4 Fig. 1. Schematic cross-section of a floating-gate n-channel flash memory.
2.8 10
3. Results and discussion
Fig. 3. Dependence of initial floating-gate voltage of the flash memories with different TD’s on substrate concentration. Vcg = 10 V, Vds = 3.3 V.
to-control gate capacitance and CT is the total capacitance of the floating gate [6]. So the coupling voltage Vfg’s of the three devices are not very sensitive to substrate doping. The initial control-gate currents of the three devices are shown in Fig. 4. Since the control-gate current reflects the level of the injected charge into the floating gate, it can be said that the flash memories with Si3N4/SiO2 stacked TD and Si3N4 TD have the highest and lowest initial programming speed due to the largest and smallest initial control-gate current, respectively, (fresh VT can be found in Fig. 2). This can be explained by the lucky electron model (LEM). It is well known that when Vfg Vds, the CHE injection current is the largest, and when Vfg < Vds or Vfg > Vds, the CHE injection current is decreased, due to a reversed oxide field near drain (i.e. negative bias) and thus increased tunneling barrier for the former, and reduction of horizontal electric field and thus reduced impact ionization rate near drain for the latter. Therefore, the initial control-gate current is closely related to the TD structure, and the Si3N4/SiO2 TD can give a Vfg close to Vds as mentioned above. Generally, for the stacked TD of the flash memory, by proper barrierlayer design, the current conduction through the barrier can become more sensitive to the electric field in TOX than that through a single barrier [7].
Control Gate Current (10-11A/μm)
Threshold voltages (V)
17
-3
SiO2 Si3N4 Si3N4/SiO2
3.0
10
Substrate concentration (cm )
Fig. 2 shows that the fresh threshold voltages of the three kinds of structures are increased as the substrate concentration increases before programming. The fresh threshold voltages of the memory device with SiO2 and Si3N4 tunnel layers are the largest and smallest, respectively, while the one with stacked tunnel layer of Si3N4/ SiO2 (6/4 nm) is between the two (almost same fresh threshold voltage for the other three Si3N4/SiO2 stacked structures with different thickness ratios and same total physical thickness of 10 nm). Fig. 3 is the floating-gate voltage (Vfg) at the onset of programming for the three kinds of structures. Obviously, the different TD’s give different Vfg’s. Vfg is decided through the coupling capacitor network, not the external bias directly. The electrical field in TD tends to rapidly decrease as the j-value of the TD increases due to reduced coupling ratio, which is associated with the capacitances of floating gate-to-control gate, to-substrate, to-drain, tosource and boundary capacitances [2]. So the Vfg of the memory device with SiO2 and Si3N4 tunnel layers are the largest (>Vds) and smallest (
3.5
16
2.5 2.0 1.5 1.0 0.5
10
Si3N4/SiO2
8
6
SiO 2
4
Si 3N4
2
0.0 16
10
16
17
10
10
-3
Substrate Doping (cm ) Fig. 2. Fresh threshold voltage of the flash memories with different TDs versus substrate concentration.
17
10
Substrate concentration (cm-3) Fig. 4. Dependence of the initial control-gate current of the flash memories with different TDs on substrate concentration. Vcg = 10 V, Vds = 3.3 V.
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L. Liu et al. / Microelectronics Reliability 49 (2009) 912–915
Figs. 5 and 6 show the programming time and the maximum control-gate current when the programming process reach saturation, respectively. The latter has a direct impact on the final charge storage capacity of the floating gate. Corresponding to results in Figs. 3 and 4, the memory with Si3N4/SiO2 TD exhibits the shortest saturated time and the largest saturated control-gate current, which, furthermore, are decreased and increased, respectively, as the substrate concentration increases. This is because as the substrate concentration increases, the electrical field in deletion region near drain is enhanced and thus impact ionization rate is increased, resulting in creation of more hot carriers and injection of more CHE. The saturation threshold voltages of the three kinds of structures increase rapidly as the substrate concentration increases, with the largest for the Si3N4/SiO2 stacked sample. The higher saturation threshold voltage contributes to the larger memory window. Fig. 7 is the change of threshold voltage (DVth) of the three memory devices versus substrate concentration for a programming time of 15 ls. The DVth of the memory with the Si3N4/SiO2 TD is far
larger than that of the other two memories, especially in high substrate concentrations due to generation and injection of more CHE. The DVth of the memory with Si3N4 TD become larger than that of the memory with SiO2 TD for substrate concentrations above 1 1017 cm 3. This is contributed for an enhanced field near drain and thus increased impact ionization rate with increasing substrate concentration, giving rise to injection of more CHE. Fig. 8 depicts variation of the programming time with substrate concentration when setting DVth = 3 V. The programming time of the memory with Si3N4/SiO2 stacked TD is only 10 ls at Vcg = 10 V and Vds = 3.3 V, demonstrating high programming speed. Moreover, as the substrate concentration increases, the programming time is shortened due to enhanced charge-injection efficiency. From the above discussions, it seems to be that the higher the substrate concentration, the better the programming characteristics of the memories. However, although the high substrate concentration can induce the high impact ionization rate, producing a large number of hot carriers, the generated hot electrons are injected into the floating gate, while the generated hot holes become the substrate current. The large substrate current undoubtedly
-4
1.4x10
5
Si 3N4
-4
SiO2
-4
Saturation time (s)
Change in Threshold Voltage (V)
1.2x10 1.0x10
-5
8.0x10
-5
Si 3N4/SiO2
6.0x10
-5
4.0x10
4
t=15μs
Si3N4/SiO2
3
SiO2 2
Si3N4
-5
2.0x10
1 16
10
10
Fig. 5. Saturation programming time of the flash memories with different TDs versus substrate concentration. Vcg = 10 V, Vds = 3.3 V.
10
Substrate concentration (cm-3)
Substrate concentration (cm-3)
Fig. 7. Change of threshold voltage of the flash memories with different TDs versus substrate concentration. Vcg = 10 V, Vds = 3.3 V.
16 4.0x10
12 10
Si3N4/SiO2
8 6 4
Si3N4
-5
14
Programming time (s)
Saturated Control Gate Current (10-11A/μm)
17
10
17
16
δVth = 3 V 3.0x10
-5
2.0x10
-5
SiO2
Si3N4/SiO2
SiO2 1.0x10
-5
Si 3N4
2 16
10
16
10
17
10
-3
Substrate concentration (cm ) Fig. 6. Saturation control-gate current of the flash memories with different TDs versus substrate concentration. Vcg = 10 V, Vds = 3.3 V.
17
10
Substrate concentration (cm-3) Fig. 8. Programming time of the flash memories with different TDs as a function of substrate concentration. Vcg = 10 V, Vds = 3.3 V.
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L. Liu et al. / Microelectronics Reliability 49 (2009) 912–915
Table 1 Programming time and post-programming control-gate current under different interface-state densities for the three TD structures (substrate concentration = 8 1016 cm 3, Vcg = 10 V and Vds = 3.3 V).
A/μm)
16
Control gate current (10
18
-15
20
14
SiO2
5 1011 1 1012 5 1012
7.407 10 8.609 10 1.657 10
5
5 1011 1 1012 5 1012
1.064 10 1.241 10 2.564 10
4
11
4.212 10 4.719 10 1.336 10
5
Si3N4
10 Si3N4/SiO2
8 10
16
10
5 10 1 1012 5 1012
eV
1
Dit (cm
Si3N4/SiO2 = 6 nm/4 nm
12
2
TDs
)
Saturation programming time (s) 5 4
4 4
5 4
Post-programming control-gate current (A/lm) 2.899 10 3.577 10 8.679 10
14 14 13
8.36 10 15 1.268 10 14 6.481 10 12 1.989 10 3.965 10 9.571 10
14 14 13
17
-3
Substrate concentration (cm ) Fig. 9. Post-programming control-gate current versus substrate concentration for the Si3N4/SiO2 (6 nm/4 nm) stacked TD. Vcg = 10 V, Vds = 3.3 V.
leads to large programming power dissipation, which could be unacceptable for low-power applications of the flash memory. Besides, the excessively large saturation injection current, especially for substrate concentration above 2 1017 cm 3 as shown in Fig. 6, easily induces the avalanche breakdown at the drain, which is harmful for the device lifetime [5]. On the other hand, after saturation programming, the control-gate current of the flash memories with SiO2/Si3N4 stacked TD increases as the substrate concentration increases (as shown in Fig. 9), causing a higher power dissipation too. Therefore, a trade-off between the high programming speed and the good device performances has to be considered for designing the memory with different TDs, e.g. Si3N4/ SiO2. From the results in Figs. 6–9, it is suitable to choose the substrate concentrations between 5 1016 cm 3 and 2 1017 cm 3 to obtain good programming characteristics while keeping low power dissipation and long device lifetime. Finally, the effects of interface-state density (Dit) at the dielectric/Si interface on the programming characteristics and power dissipation are investigated for the three TD memories. As shown in Table 1, the saturation programming time and post-programming control-gate current increase as Dit increases. It is well known that the SiO2/Si interface has low interface-state density but the Si3N4/ Si interface exhibits poorer quality. Therefore, the memory with a single Si3N4 layer as TD would have poorer programming properties, while the effects of interface states on the programming properties of the memory with Si3N4/SiO2/Si stacked TD are negligible. However, it is worth pointing out that the oxide charge trapping could be enhanced at the SiO2/Si3N4 interface, which will result in reliability issues. So in order to suppress the effect, a smooth SiO2/ Si3N4 interface is needed, and could be realized by using the atomic-layer deposition of Si3N4 film [8].
4. Conclusions A theoretical validation that the memory with the SiO2/Si3N4 stacked tunneling layer has higher hot electron-injected efficiency and thus better programming characteristics than ones with single tunneling layer of SiO2 or Si3N4 has been done by means of device simulation. The involved mechanism lies in the fact that the floating-gate voltage close to drain voltage can conveniently be realized by the stacked TD. In addition, the relation between the programming speed and the substrate concentration has been investigated and optimal substrate concentration between 5 1016 cm 3 and 2 1017 cm 3 is obtained by considering a trade-off between the programming characteristics and power dissipation/lifetime of the devices. Lastly, simulation results show that the interface-state density of the dielectric/Si interface has a large effect on programming properties. Therefore, Si3N4/SiO2/Si stacked TD with an excellent SiO2/Si interface is a promising tunneling-layer structure for improving the programming characteristics of the flash memories. References [1] Kim Kinam, Lee SY. Memory technology in the future. Microelectron Eng 2007;84:1976–81. [2] Chen YY et al. Programming efficiency of stacked-gate flash memories with high-j dielectrics. In: IEEE conference on emerging technologiesnanoelectronics; 2006. p. 302–5. [3] Yoshikawa K. Research challenges for next decade flash memories. Int. electron device and material symposia (IEDMS); 2000. p. 11–8. [4] Shim Sun IL, Wang XW, Ma TT. SONOS-type flash memory cell with metal/ Al2O3/SiN/Si3N4/Si structure for low-voltage high-speed program/erase operation. IEEE Electron Dev Lett 2008:512–4. [5] Wang Ying Qian et al. Electrical characteristics of memory devices with a high-j HfO2 trapping layer and dual SiO2/Si3N4 tunneling layer. IEEE Trans Electron Dev 2007:2699–705. [6] Paul I, Bill P, et al. Cell model for EEPROM floating-gate memories. In: IEEE IEDM tech dig; 1982. p. 737–40. [7] Sun Zi Min et al. Simulation and analysis of substrate current in deep-sub micrometer MOSFET’s. Microelectronics 1998;25:93–8. [8] Hong Sug Hun et al. Improvement of the current–voltage characteristics of a tunneling dielectric by adopting a Si3N4/SiO2/Si3N4 multilayer for flash memory application. Appl Phys Lett 2005;87:152106–8.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
A study on the improved programming characteristics of flash memory with Si3N4/SiO2 stacked tunneling dielectric L. Liu a, J.P. Xu a,*, L.L. Chen a, P.T. Lai b,* a b
Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan 430074, People’s Republic of China Department of Electrical and Electronic Engineering, The University of Hong Kong, Pokfulam Road, Hong Kong, China
a r t i c l e
i n f o
Article history: Received 23 January 2009 Received in revised form 13 May 2009 Available online 21 June 2009
a b s t r a c t The programming characteristics of memories with different tunneling-layer structures (Si3N4, SiO2 and Si3N4/SiO2 stack) dielectrics are investigated using 2-D device simulator of MEDICI. It is theoretically confirmed that the memory with the SiO2/Si3N4 stacked tunneling layer exhibits better programming characteristics than ones with single tunneling layer of SiO2 or Si3N4 for programming by channel hot electron (CHE) injection. A 10-ls programming time with a threshold-voltage shift of 5 V can be obtained for the memory with SiO2/Si3N4 stacked tunneling layer at Vcg = 10 V and Vds = 3.3 V. This is attributed to the fact that the floating-gate voltage is close to drain voltage for the stacked tunneling dielectric (TD), and thus the CHE injection current is the largest. Furthermore, optimal substrate concentration is determined to be 5 1016–2 1017 cm 3, by considering a trade-off between the programming characteristics and power dissipation/lifetime of the devices. Lastly, the effects of interface states on the programming characteristics are investigated. Low interface-state density gives short programming time and small post-programming control-gate current. Ó 2009 Elsevier Ltd. All rights reserved.
1. Introduction New non-volatile memory technologies are pursued as candidates for the next generation memories due to its superb memory performance such as high speed, low power consumption, and high long-term reliability [1]. Especially the employment of high-permittivity (j) dielectrics in flash memory has recently attracted increasing attention. Usually, the dielectric with higher permittivity inherently has lower barrier height (uB, conduction-band difference between dielectric and Si substrate) [2]. So replacing tunnel oxide (TOX) by high-j TD is beneficial for enhancing carrier injection from substrate to the floating gate due to the smaller uB. However, taking the charge retention into consideration, the uB between the silicon substrate and the adopted high-j TDs should be larger than 1.5 eV to suppress the loss of floating gate charges through electron thermal emission [3]. So far, Si3N4 [4] and stacked Si3N4/SiO2 [5] dielectrics have been adopted as tunnel layer of the flash memory and good programming and erasing properties have been demonstrated. The programming efficiency of the stackedgate flash memory with high-j tunnel dielectric has been evaluated by 2-D MEDICI simulation [2]. Enhanced charge injection from the substrate through the high-j tunnel dielectric was confirmed by experimental results [5]. However, effects of substrate concentration on the performance of flash memories were seldom inves* Corresponding authors. E-mail addresses: [email protected] (J.P. Xu), [email protected] (P.T. Lai). 0026-2714/$ - see front matter Ó 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2009.05.010
tigated when different kinds of tunnel dielectrics were used. In this work, the programming characteristics of the memory with stacked Si3N4/SiO2 as tunnel layer and its dependences on substrate concentration are theoretically investigated by means of the 2-D device simulator MEDICI. Simulated results show its excellent programming properties compared to memories with SiO2 or Si3N4 as the tunneling layer. Furthermore, suitable substrate concentration is determined by considering a trade-off between the programming characteristics and power dissipation/lifetime of the devices for the memory with stacked Si3N4/SiO2 as tunneling layer. 2. Device model The device structure of the n-channel floating-gate memory is shown in Fig. 1. The channel length is fixed to be 0.5 lm. The thickness of the blocking oxide between the control-gate electrode and the floating gate is 20 nm. The n+ floating gate thickness is 25 nm. The tunneling layer is SiO2, Si3N4, or stacked Si3N4/SiO2, with a physical thickness of 10 nm. The thickness ratio for the Si3N4/ SiO2 stacked structure is varied from 4/6 nm to 7/3 nm. The source/drain concentration is 3 1019 cm 3. Programming of the devices is achieved by channel hot electron (CHE) injection at Vcg = 10 V and Vds = 3.3 V (Vcg is control-gate voltage and Vds is drain–source voltage). The initial value of the programming time is set to be 10 9 s. The programming properties are characterized as a function of the substrate concentration.
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L. Liu et al. / Microelectronics Reliability 49 (2009) 912–915
4.0
SiO2
Floating Gate Voltage (V)
3.8 3.6
Si3N4/SiO2(4/6) 3.4
Si3N4/SiO2(5/5) Si3N4/SiO2(6/4)
3.2
Si3N4/SiO2(7/3)
3.0
Si3N4 Fig. 1. Schematic cross-section of a floating-gate n-channel flash memory.
2.8 10
3. Results and discussion
Fig. 3. Dependence of initial floating-gate voltage of the flash memories with different TD’s on substrate concentration. Vcg = 10 V, Vds = 3.3 V.
to-control gate capacitance and CT is the total capacitance of the floating gate [6]. So the coupling voltage Vfg’s of the three devices are not very sensitive to substrate doping. The initial control-gate currents of the three devices are shown in Fig. 4. Since the control-gate current reflects the level of the injected charge into the floating gate, it can be said that the flash memories with Si3N4/SiO2 stacked TD and Si3N4 TD have the highest and lowest initial programming speed due to the largest and smallest initial control-gate current, respectively, (fresh VT can be found in Fig. 2). This can be explained by the lucky electron model (LEM). It is well known that when Vfg Vds, the CHE injection current is the largest, and when Vfg < Vds or Vfg > Vds, the CHE injection current is decreased, due to a reversed oxide field near drain (i.e. negative bias) and thus increased tunneling barrier for the former, and reduction of horizontal electric field and thus reduced impact ionization rate near drain for the latter. Therefore, the initial control-gate current is closely related to the TD structure, and the Si3N4/SiO2 TD can give a Vfg close to Vds as mentioned above. Generally, for the stacked TD of the flash memory, by proper barrierlayer design, the current conduction through the barrier can become more sensitive to the electric field in TOX than that through a single barrier [7].
Control Gate Current (10-11A/μm)
Threshold voltages (V)
17
-3
SiO2 Si3N4 Si3N4/SiO2
3.0
10
Substrate concentration (cm )
Fig. 2 shows that the fresh threshold voltages of the three kinds of structures are increased as the substrate concentration increases before programming. The fresh threshold voltages of the memory device with SiO2 and Si3N4 tunnel layers are the largest and smallest, respectively, while the one with stacked tunnel layer of Si3N4/ SiO2 (6/4 nm) is between the two (almost same fresh threshold voltage for the other three Si3N4/SiO2 stacked structures with different thickness ratios and same total physical thickness of 10 nm). Fig. 3 is the floating-gate voltage (Vfg) at the onset of programming for the three kinds of structures. Obviously, the different TD’s give different Vfg’s. Vfg is decided through the coupling capacitor network, not the external bias directly. The electrical field in TD tends to rapidly decrease as the j-value of the TD increases due to reduced coupling ratio, which is associated with the capacitances of floating gate-to-control gate, to-substrate, to-drain, tosource and boundary capacitances [2]. So the Vfg of the memory device with SiO2 and Si3N4 tunnel layers are the largest (>Vds) and smallest (
3.5
16
2.5 2.0 1.5 1.0 0.5
10
Si3N4/SiO2
8
6
SiO 2
4
Si 3N4
2
0.0 16
10
16
17
10
10
-3
Substrate Doping (cm ) Fig. 2. Fresh threshold voltage of the flash memories with different TDs versus substrate concentration.
17
10
Substrate concentration (cm-3) Fig. 4. Dependence of the initial control-gate current of the flash memories with different TDs on substrate concentration. Vcg = 10 V, Vds = 3.3 V.
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L. Liu et al. / Microelectronics Reliability 49 (2009) 912–915
Figs. 5 and 6 show the programming time and the maximum control-gate current when the programming process reach saturation, respectively. The latter has a direct impact on the final charge storage capacity of the floating gate. Corresponding to results in Figs. 3 and 4, the memory with Si3N4/SiO2 TD exhibits the shortest saturated time and the largest saturated control-gate current, which, furthermore, are decreased and increased, respectively, as the substrate concentration increases. This is because as the substrate concentration increases, the electrical field in deletion region near drain is enhanced and thus impact ionization rate is increased, resulting in creation of more hot carriers and injection of more CHE. The saturation threshold voltages of the three kinds of structures increase rapidly as the substrate concentration increases, with the largest for the Si3N4/SiO2 stacked sample. The higher saturation threshold voltage contributes to the larger memory window. Fig. 7 is the change of threshold voltage (DVth) of the three memory devices versus substrate concentration for a programming time of 15 ls. The DVth of the memory with the Si3N4/SiO2 TD is far
larger than that of the other two memories, especially in high substrate concentrations due to generation and injection of more CHE. The DVth of the memory with Si3N4 TD become larger than that of the memory with SiO2 TD for substrate concentrations above 1 1017 cm 3. This is contributed for an enhanced field near drain and thus increased impact ionization rate with increasing substrate concentration, giving rise to injection of more CHE. Fig. 8 depicts variation of the programming time with substrate concentration when setting DVth = 3 V. The programming time of the memory with Si3N4/SiO2 stacked TD is only 10 ls at Vcg = 10 V and Vds = 3.3 V, demonstrating high programming speed. Moreover, as the substrate concentration increases, the programming time is shortened due to enhanced charge-injection efficiency. From the above discussions, it seems to be that the higher the substrate concentration, the better the programming characteristics of the memories. However, although the high substrate concentration can induce the high impact ionization rate, producing a large number of hot carriers, the generated hot electrons are injected into the floating gate, while the generated hot holes become the substrate current. The large substrate current undoubtedly
-4
1.4x10
5
Si 3N4
-4
SiO2
-4
Saturation time (s)
Change in Threshold Voltage (V)
1.2x10 1.0x10
-5
8.0x10
-5
Si 3N4/SiO2
6.0x10
-5
4.0x10
4
t=15μs
Si3N4/SiO2
3
SiO2 2
Si3N4
-5
2.0x10
1 16
10
10
Fig. 5. Saturation programming time of the flash memories with different TDs versus substrate concentration. Vcg = 10 V, Vds = 3.3 V.
10
Substrate concentration (cm-3)
Substrate concentration (cm-3)
Fig. 7. Change of threshold voltage of the flash memories with different TDs versus substrate concentration. Vcg = 10 V, Vds = 3.3 V.
16 4.0x10
12 10
Si3N4/SiO2
8 6 4
Si3N4
-5
14
Programming time (s)
Saturated Control Gate Current (10-11A/μm)
17
10
17
16
δVth = 3 V 3.0x10
-5
2.0x10
-5
SiO2
Si3N4/SiO2
SiO2 1.0x10
-5
Si 3N4
2 16
10
16
10
17
10
-3
Substrate concentration (cm ) Fig. 6. Saturation control-gate current of the flash memories with different TDs versus substrate concentration. Vcg = 10 V, Vds = 3.3 V.
17
10
Substrate concentration (cm-3) Fig. 8. Programming time of the flash memories with different TDs as a function of substrate concentration. Vcg = 10 V, Vds = 3.3 V.
915
L. Liu et al. / Microelectronics Reliability 49 (2009) 912–915
Table 1 Programming time and post-programming control-gate current under different interface-state densities for the three TD structures (substrate concentration = 8 1016 cm 3, Vcg = 10 V and Vds = 3.3 V).
A/μm)
16
Control gate current (10
18
-15
20
14
SiO2
5 1011 1 1012 5 1012
7.407 10 8.609 10 1.657 10
5
5 1011 1 1012 5 1012
1.064 10 1.241 10 2.564 10
4
11
4.212 10 4.719 10 1.336 10
5
Si3N4
10 Si3N4/SiO2
8 10
16
10
5 10 1 1012 5 1012
eV
1
Dit (cm
Si3N4/SiO2 = 6 nm/4 nm
12
2
TDs
)
Saturation programming time (s) 5 4
4 4
5 4
Post-programming control-gate current (A/lm) 2.899 10 3.577 10 8.679 10
14 14 13
8.36 10 15 1.268 10 14 6.481 10 12 1.989 10 3.965 10 9.571 10
14 14 13
17
-3
Substrate concentration (cm ) Fig. 9. Post-programming control-gate current versus substrate concentration for the Si3N4/SiO2 (6 nm/4 nm) stacked TD. Vcg = 10 V, Vds = 3.3 V.
leads to large programming power dissipation, which could be unacceptable for low-power applications of the flash memory. Besides, the excessively large saturation injection current, especially for substrate concentration above 2 1017 cm 3 as shown in Fig. 6, easily induces the avalanche breakdown at the drain, which is harmful for the device lifetime [5]. On the other hand, after saturation programming, the control-gate current of the flash memories with SiO2/Si3N4 stacked TD increases as the substrate concentration increases (as shown in Fig. 9), causing a higher power dissipation too. Therefore, a trade-off between the high programming speed and the good device performances has to be considered for designing the memory with different TDs, e.g. Si3N4/ SiO2. From the results in Figs. 6–9, it is suitable to choose the substrate concentrations between 5 1016 cm 3 and 2 1017 cm 3 to obtain good programming characteristics while keeping low power dissipation and long device lifetime. Finally, the effects of interface-state density (Dit) at the dielectric/Si interface on the programming characteristics and power dissipation are investigated for the three TD memories. As shown in Table 1, the saturation programming time and post-programming control-gate current increase as Dit increases. It is well known that the SiO2/Si interface has low interface-state density but the Si3N4/ Si interface exhibits poorer quality. Therefore, the memory with a single Si3N4 layer as TD would have poorer programming properties, while the effects of interface states on the programming properties of the memory with Si3N4/SiO2/Si stacked TD are negligible. However, it is worth pointing out that the oxide charge trapping could be enhanced at the SiO2/Si3N4 interface, which will result in reliability issues. So in order to suppress the effect, a smooth SiO2/ Si3N4 interface is needed, and could be realized by using the atomic-layer deposition of Si3N4 film [8].
4. Conclusions A theoretical validation that the memory with the SiO2/Si3N4 stacked tunneling layer has higher hot electron-injected efficiency and thus better programming characteristics than ones with single tunneling layer of SiO2 or Si3N4 has been done by means of device simulation. The involved mechanism lies in the fact that the floating-gate voltage close to drain voltage can conveniently be realized by the stacked TD. In addition, the relation between the programming speed and the substrate concentration has been investigated and optimal substrate concentration between 5 1016 cm 3 and 2 1017 cm 3 is obtained by considering a trade-off between the programming characteristics and power dissipation/lifetime of the devices. Lastly, simulation results show that the interface-state density of the dielectric/Si interface has a large effect on programming properties. Therefore, Si3N4/SiO2/Si stacked TD with an excellent SiO2/Si interface is a promising tunneling-layer structure for improving the programming characteristics of the flash memories. References [1] Kim Kinam, Lee SY. Memory technology in the future. Microelectron Eng 2007;84:1976–81. [2] Chen YY et al. Programming efficiency of stacked-gate flash memories with high-j dielectrics. In: IEEE conference on emerging technologiesnanoelectronics; 2006. p. 302–5. [3] Yoshikawa K. Research challenges for next decade flash memories. Int. electron device and material symposia (IEDMS); 2000. p. 11–8. [4] Shim Sun IL, Wang XW, Ma TT. SONOS-type flash memory cell with metal/ Al2O3/SiN/Si3N4/Si structure for low-voltage high-speed program/erase operation. IEEE Electron Dev Lett 2008:512–4. [5] Wang Ying Qian et al. Electrical characteristics of memory devices with a high-j HfO2 trapping layer and dual SiO2/Si3N4 tunneling layer. IEEE Trans Electron Dev 2007:2699–705. [6] Paul I, Bill P, et al. Cell model for EEPROM floating-gate memories. In: IEEE IEDM tech dig; 1982. p. 737–40. [7] Sun Zi Min et al. Simulation and analysis of substrate current in deep-sub micrometer MOSFET’s. Microelectronics 1998;25:93–8. [8] Hong Sug Hun et al. Improvement of the current–voltage characteristics of a tunneling dielectric by adopting a Si3N4/SiO2/Si3N4 multilayer for flash memory application. Appl Phys Lett 2005;87:152106–8.