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Stress analysis of airgaps under process-induced thermo-mechanical loads
Microelectronic Engineering 156 (2016) 70–77
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Stress analysis of airgaps under process-induced thermo-mechanical loads Houman Zahedmanesh ⁎, Mario Gonzalez, Ivan Ciofi, Kristof Croes, Jürgen Bömmels, Zsolt Tőkei imec, Kapeldreef 75, Leuven 3001, Belgium
a r t i c l e
i n f o
Article history: Received 4 June 2015 Received in revised form 12 February 2016 Accepted 13 February 2016 Available online 15 February 2016 Keywords: Airgap Ultra low-k dielectric (ULK) Interconnect Finite element model (FEM)
a b s t r a c t In order to understand the state of process induced stresses in airgap interconnect structures fabricated by the etch-back approach, finite element (FE) models of a 90 nm pitch interconnect were developed and a stress analysis of the structure was conducted as a function of the dielectric liner (silicon nitride) and metal barrier (MB) thicknesses. Models of similar structures without airgaps were also developed and the stresses were evaluated as a benchmark case. In addition, a static field solver was used to extract the capacitance of the interconnect structure and evaluate the capacitance reduction by introducing airgaps compared to structures without airgaps. The results identified the sidewall dielectric liner as a critical location where high tensile stress concentration can result in failure of structures under thermo-mechanical loads. Reducing the thickness of the MB and the dielectric liner simultaneously to 1 nm and 2 nm respectively, minimized metal barrier tensile stresses but increased the tensile stress in the dielectric liner dramatically to 1 GPa. Meanwhile, this configuration provided the lowest capacitance and reduced the capacitance of the interconnect by 27% compared to a similar structure without airgaps. In general, reducing the thickness of the MB decreased its stresses both in interconnect structures with and without airgaps. © 2016 Elsevier B.V. All rights reserved.
1. Introduction The performance of ultra large scale integration (ULSI) integrated circuits is limited by the resistive and capacitive (RC) delays in the interconnect [1]. This challenge necessitates development of technologies that reduce resistances and capacitances. Moreover, interconnect capacitance also entails excessive interconnect cross-talk and power dissipation that underlines the importance of capacitance mitigation. Therefore, novel inter-line ultra-low-k dielectric materials (ULK) with k values lower than 2.5 have been employed whereby the k value is further reduced by inclusion of pores into the dielectric material to form porous low-k materials [2]. Nonetheless, as the porosity of the ULK materials is increased, their mechanical properties deteriorate dramatically which constitutes a major integration challenge [3]. ULK materials suffer from lower stiffness, low fracture toughness and inferior adhesion mainly due to their porous structure which renders them susceptible to damage during the Damascene process steps [3,4]. This dramatic reduction of mechanical robustness of ULK materials constitutes a limit for further lowering the effective k value. Therefore, although integration of ULK materials has led to a considerable reduction of interconnect capacitive delay, currently there is a significant effort ongoing for replacing the interline dielectric fully with air by integration of airgaps given that air offers the ⁎ Corresponding author. E-mail address: [email protected] (H. Zahedmanesh).
http://dx.doi.org/10.1016/j.mee.2016.02.019 0167-9317/© 2016 Elsevier B.V. All rights reserved.
best dielectric constant value of 1 [5–9]. However, implementing airgaps adds further to the integration challenge which necessitates a thorough understanding of the stress state of the interconnect structure and the impact of each process step [10]. One of the potential airgap integration approaches is the etch-back approach where the inter-line low-k is removed by an etch step [10]. However, in order to ensure mechanical stability and chemical stability of such a structure, it is necessary to implement a relatively stiff dielectric liner such as silicon nitride to cover the metal structure which prevents oxidation of the metal and also provides mechanical support and stability to the airgap and metal lines [10,11]. Process induced stresses not only can complicate interconnect integration itself, but also will have important implications for reliability under chip package interaction (CPI) and electro-migration (EM) loads. Tensile hydrostatic stresses in copper lines facilitate EM induced void formation [12] and also expansion of copper due to thermal effects or EM induced extrusion can lead to airgap failure at the liner or MB. Specifically, as the inter-line space is down-scaled it is necessary to reduce the thickness of the liner to ensure capacitance reduction and that can potentially constitute a reliability challenge as the stiff liner will be compromised [11]. Clearly therefore, it is of outmost importance to devise methodologies that provide quantitative understanding of the process induced interconnect stresses. To this end, in this study numerical models of interconnect structures are developed in order to investigate the mechanical stresses and shed light on the influence of two main airgap design parameters for the etch-back approach, (i) the thickness of the metal barrier (MB)
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Fig. 1. Summary of the modeled process steps.
and (ii) the thickness of the dielectric liner and also to devise potential strategies for stress mitigation. 2. Methods 2.1. Stress analysis A 2D plane strain FE model of a single level interconnect structure with 90 nm pitch and line aspect ratio of 1 was developed within the MSC-Marc® FEM package. Two groups of interconnect structures were modeled; (i) the mainstream structure with ULK without airgaps and (ii) similar structures but with airgaps using the etch-back process. In order to model the deposition of each material, elements corresponding to each material were activated at each subsequent analysis step of the multistep thermo-mechanical simulation, see Fig. 1. The model was discretized using solid planar quadrilateral plane-strain elements (element type 11 in MSC-Marc® FEM package) and approximately 800–1000 elements were used to model each line structure. The existing stresses within each deposited material, in addition to the thermal expansion mismatch, are induced due to complex molecular/ atomic re-organization during deposition. In order to capture the overall effect of such phenomena, the intrinsic stress of each material was extracted from the wafer bowing experiments on single blanket layers using the Stoney's approach (Table 1) [13]. Subsequently, the intrinsic stress values were implemented in the FE model by including stress initial conditions in each step of the simulation which were allowed to reach an equilibrium state during the step. Airgap formation in the etch-back process was modeled by deactivation of intermetallic ULK related FE elements. Ultimately a heat-up step of 200 °C was applied to the sequentially built-up structure in order to investigate the stresses at elevated temperatures, specifically the ability of the airgaps to withstand copper expansion without failure. The mechanical and thermal material properties used in the simulations are summarized in Table 2. In order to understand the variation in stresses of copper lines, MB and the dielectric liner with the thickness, the thickness of the MB was altered from 1 to 6 nm and the thickness of the dielectric liner from 2 to 10 nm at the sidewall whilst it was presumed that the thickness of the liner at the top of the liner is twice the thickness of the liner at the sidewall i.e. (4–20 nm). The copper line dimensions were
kept constant. Interconnect mechanical failures are mainly brittle cracking events specifically given the low fracture toughness and adhesion of the low-k dielectrics and the dramatic dimensional downscaling of copper lines [4,14,15]. Such brittle mechanical failures have been shown to be driven by the maximum tensile principal stresses [14–16]. Therefore, in this paper the maximum principal stresses are reported for the dielectric liner and MB. On the other hand, the hydrostatic stresses in copper are also reported given that hydrostatic stress is a predictor of electro-migration and stress migration [16,17]. 2.2. Capacitance analysis Capacitance models of the interconnect structure were developed using the Raphael™ field solver [11,18] and the various designs were simulated consistent with the case studies discussed for the mechanical model by interfacing Raphael™ with the Optimus™ software. The capacitance of the airgapped interconnects were benchmarked against a similar structure but with the mainstream technology (i.e. without airgaps and using ULK material with a k = 2.4) to decipher the capacitance benefits when incorporating airgaps. The capacitance value is the total capacitance including the capacitance of the line with the two neighboring lines and the top and bottom lines presuming a Manhattan interconnect structure. The dielectric barrier and liner material were considered to be silicon nitride with a dielectric constant of 7.3 and the k value of the ULK was set to 2.4 in all cases. 3. Results and discussion The stresses in the interconnect structure were calculated using the developed FE model as a function of MB and dielectric liner thickness. The dielectric liner was found to endure highest tensile maximum principal stresses at the sidewall compared to MB, see Fig. 2. In the case were the thickest MB and dielectric liner were implemented (i.e. 6 nm MB and 10 nm liner) the maximum principal stresses reached 628 MPa in the liner and 255 MPa in MB. In contrast the thinnest MB and liner within the studied range resulted in a liner maximum principal stress of Table 2 Thermal and mechanical material properties used in the simulations. Material
Table 1 Intrinsic stresses obtained from wafer bowing. Layer
Thickness (nm)
Residual Stress (MPa)
Low-k (OSG 2.4) MB (Ta) Liner (silicon nitride) Cu
100 7 20 60
+40 (tensile) −1375 (compressive) −120 (compressive) +500 (tensile)
Low-k organo-silicate glass with k value of 2.4 (OSG 2.4) MB (Ta) Liner (silicon nitride) Cu
Young's modulus (GPa) 9 186 265 117
Poisson's ratio
Coefficient of thermal expansion (CTE)
0.2
1.2 × 10−5
0.34 0.27 0.3
6.3 × 10−6 1.5 × 10−6 1.67 × 10−5
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Fig. 2. Stress distribution in airgapped interconnect with MB thickness = 6 nm, sidewall liner thickness = 10 nm, top liner thickness = 20 nm at a temperature of 200 °C. (a) Stresses in the fully integrated structure (b) stresses in the silicon nitride dielectric liner (c) stresses in the MB. Arrows show the location of the highest tensile stresses. Positive values show tensile stresses.
1 GPa and 76 MPa in MB and again the dielectric liner at the sidewall endured the highest stresses, see Fig. 3. Figs. 4 and 5, summarize the variation in maximum principal stress values in the MB and the liner with thickness, respectively. It can be seen that simultaneous reduction of the thickness of the MB and the liner, increases the liner tensile stresses specifically at the sidewall reaching maximum principal stresses of up to 1 GPa, see Fig. 4. Comparing the calculated value of the maximum principal stress in the dielectric liner which is assumed to be silicon nitride with an illustrative value of 1.54 ± 0.37 GPa for the ultimate tensile strength of silicon nitride [19], indicates that although ideally a 2 nm silicon nitride liner should still withstand the incurred stresses but the chances of failure due to imperfections in the processes and material, which cannot be fully recapitulated by an idealistic model, indeed increase at such high calculated stress levels. In stark contrast to stresses in the dielectric
liner, simultaneous reduction of the MB and liner thicknesses reduced MB tensile stresses, see Fig. 5. In addition, liner stresses were found to be more strongly influenced by variations in the liner thickness rather than the MB thickness, while MB stresses were more strongly influenced by variation in MB thickness, see Figs. 4 & 5. It was found that depending on the combination of MB and liner thicknesses, MB and liner stresses can vary between 76 and 274 MPa (3.3 fold) and 692–1131 MPa (1.4 fold) respectively, which demonstrates that MB stresses are more sensitive to variations of thicknesses compared to liner stresses. In this context, comparing the stress values in the MB in airgap models with that of the non-airgap structures can provide a better understanding of the influence of airgaps. In a similar structure but without airgaps, increasing the thickness of the MB from 1 nm to 6 nm resulted in maximum principal stresses of 22 MPa and 243 MPa in the MB, respectively. Comparing these values with the
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Fig. 3. Stress distribution in airgapped interconnect with MB thickness = 1 nm, sidewall liner thickness = 2 nm, top liner thickness = 4 nm at a temperature of 200 °C. (a) Stresses in the fully integrated structure (b) stresses in the silicon nitride dielectric liner (c) stresses in the MB. Arrows show the location of the highest tensile stresses. Positive values show tensile stresses.
values from airgapped structures reveals that the MB stresses are only marginally higher in the airgapped structures compared to the case without airgaps, see also Fig. 6. As discussed, our model shows that both in the airgapped interconnects and in the interconnects without airgap, increasing MB thickness resulted in its elevated stress level unanimously. This finding, although counterintuitive at the first glance, was found to be due to the dominant bending deformation mode in the MB which is shown in Fig. 6 (i.e. thinner MB is more compliant in bending and endures lower stress). Important to note is that, although reducing the MB thickness will decrease its stresses, it provides lower mechanical support to the copper lines and instead follows the deformation of copper. In order to prevent potential outward extrusion of the copper lines, this lack of mechanical support by the MB needs to be compensated by the dielectric liner. In addition to MB and liner stresses, the stress state of the copper lines can also have crucial implications for the reliability of airgapped structures. Tensile hydrostatic stresses in copper lines facilitate void formation due to EM [12]. Therefore, a combination of MB and liner thicknesses that can induce a more compressive hydrostatic stress state in copper lines can help reduce EM induced void formation. In this context, Fig. 7 shows the variation of the hydrostatic stress in the copper lines during the consecutive steps of the simulated process steps. The simulations show that the hydrostatic stress state in copper lines is more
compressive in the case of airgaps compared to without airgaps which can be potentially beneficial from an EM induced voiding standpoint. Indeed, at the final heat-up step the hydrostatic stress is compressive throughout the entire cross section of the copper line in the airgapped structure while in the structure without airgaps only the top part of the copper line is compressive. Copper endures a highly tensile inplane stress when deposited within the etched trench in the low-k [20,21]. The tensile stress in the copper line is partly released following low-k removal from the lateral sides of the copper lines during airgap formation as shown in Fig. 7. In the case where airgaps are not introduced, the tensile stress remains in the copper line given that the lowk at either sides of the line doesn't allow full stress relaxation. Of course, during low-k etch-back for airgap formation the MB remains intact, therefore, a thicker metal barrier resists the relaxation of the tensile stress of the copper more than a thin metal barrier. This prediction by the presented FE model is also consistent with experimental measurements of stresses in copper lines using X ray diffraction (XRD) [20,21]. The liner deposition step proceeds this stress relaxation phase and in comparison was found to have a minor influence on the hydrostatic stresses in the copper lines for relatively thin liners. As such, minimizing the MB thickness and increasing the thickness of the liner induces more compressive hydrostatic stresses in the copper lines given that the thin and compliant MB allows for maximum relaxation of the tensile stresses
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Fig. 4. Maximum tensile stresses in liner as a function of MB and liner thicknesses.
in the copper during the etch-back step for airgap formation and the thicker liner resists the expansion of copper at elevated temperatures generating compressive stresses in the copper. In order to devise strategies for stress mitigation it is essential to examine the capacitive implications of changing liner and MB thicknesses and to ensure that any stress mitigation approach is also consistent with the main purpose of airgap implementation which is minimizing the capacitance. Given that the copper line dimensions were assumed constant at 45 nm width and an aspect ratio of 1 in all case studies, changes of the MB and the liner thickness only influence
the capacitance of the line. To this end, the capacitance of the interconnect structure was calculated using static field stimulations for the airgapped structures and were benchmarked against a similar structure without airgaps and with a ULK 2.4 inter-line dielectric, a 10 nm silicon nitride dielectric barrier and a 2 nm MB, for which the total capacitance was calculated to be 0.170217 fF/μm, see Fig. 8. As shown in Fig. 8, isocapacitance design regions can be identified where different combinations of MB and sidewall liner thicknesses result in the same capacitance. The highest relative reduction in capacitance is clearly the case where a combination of minimum 1 nm MB thickness and 2 nm liner
Fig. 5. Maximum tensile stresses in MB as a function of MB and liner thicknesses.
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Fig. 6. Stress distribution and deformation of the MB in the fully processed BEOL at 200 °C, deformations are exaggerated at 100×. In the airgap cases the dielectric liner thickness is 2 nm at the sidewall and 4 nm at the top.
Fig. 7. Hydrostatic stresses in the Cu lines of (left) a structure with airgap (right) a similar structure without airgap, and its variation throughout the modeled process steps. The MB thickness in both cases is 1 nm and the thickness of the dielectric liner in the airgapped case is 2 nm. Stress contours are related to stresses at 200 °C.
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Fig. 8. Comparison of capacitance using airgaps with a similar structure without airgaps in percentage, each color band represents an iso-capacitance region where the difference of consecutive color bands is 1% and positive percentage shows lower capacitances compared to the reference case (reference case: ULK 2.4, 10 nm silicon nitride dielectric barrier and 2 nm metallic barrier).
thickness is implemented where the simulation showed that airgaps resulted in 27% reduction in capacitance compared to the benchmark case. In order to obtain this capacitance reduction the possible combinations of liner and MB thicknesses are limited to 1 nm MB and 2 nm liner where the mechanical model predicts the lowest MB stress of 76 MPa and the maximum liner stress of 1 GPa at the sidewall. Hence, under this configuration the vulnerable location is the sidewall liner. On the other hand, implementing the thickest MB of 6 nm and liner of 10 nm leads to 30% increase in capacitance compared to the benchmark case with ULK which clearly violates capacitance reduction. However, between these two extremes there are cases where within the isocapacitance bands, various combinations of MB and liner thicknesses can be implemented that result in the same capacitance, although
they have different mechanical implications. As an example, from Fig. 8 it can be seen that a capacitance reduction of 10% can be achieved by airgap implementation using either of the following designs (i) MB thickness = 1 nm and sidewall liner thickness = 7 nm or (ii) MB thickness = 6 nm and sidewall liner thickness = 3 nm. Interestingly, design (i), compared to design (ii), will reduce MB stresses by almost 70% while liner stresses increase negligibly. In another case from Fig. 8 it is clear that 15% reduction in capacitance can be achieved by either (i) MB thickness = 3 nm and sidewall liner thickness = 4.5 nm or (ii) MB thickness = 6 nm and sidewall liner thickness = 2 nm. Using design (i), compared to design (ii), will reduce MB stresses by 40% and liner stresses change negligibly. Also, 20% reduction in capacitance can be achieved by either of the designs,
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(i) MB thickness = 1 nm and sidewall liner thickness = 4.2 nm or (ii) MB thickness = 4 nm and sidewall liner thickness = 2 nm. The former can reduce the MB stresses by about 50% while liner stress changes negligibly. As such, the combination of MB and liner thicknesses within each iso-capacitance design space can be configured to mitigate process induced stresses without compromising capacitance. In general, keeping the thinnest MB possible within the iso-capacitance design space and implementing a liner thicker than the MB, yields the lowest possible stresses in both the MB and liner for the same capacitance. Finally, it is worth mentioning that in this study it was assumed that within the investigated range of thickness variations of MB and liner, the film's residual stress derived from wafer bow measurements is constant. Given that the range of variations in MB and dielectric liner thicknesses studied were relatively small, this constitutes a plausible assumption. Nonetheless, film residual stresses can be potentially influenced by thickness variations which require further investigation using wafer bow measurements on MB and dielectric films with different thicknesses to further ascertain this assumption within the studied range. 4. Conclusions We previously addressed the capacitance trade-off between dielectric liner thickness and line-to-line dimensions where we concluded that the capacitance benefit of airgaps reduces with scaling due to the increasing proportion of space occupied by the liner [11]. This motivated the current study to investigate the influence of thickness variations on mechanical stresses in MBs, liners and also copper lines specifically for the etch-back airgap integration process. The highest value of maximum principal stress was identified to occur at the sidewalls of the dielectric liner. MB stresses were found to have a direct relation with its thickness and increasing the MB thickness from 1 nm to 6 nm significantly increased maximum principal stresses within the MB both where airgaps were implemented and also in interconnects without airgaps. Capacitance simulations as a function of the MB and the liner thickness identified iso-capacitance design spaces where for each target capacitance various combinations of MB and liner thicknesses could be potentially implemented. The mechanical model showed that the stresses can be mitigated without compromising the capacitance by implementing the thinnest MB and thickest liner possible within the iso-capacitance design space for a target capacitance. It was also shown that airgaps result in a more compressive hydrostatic stress state in the copper lines compared to the interconnects without airgaps and hence could potentially help reduce EM induced void formation. References [1] K. Yamashita, S. Odanaka, Impact of crosstalk on delay time and a hierarchy of interconnects, Proc. IEEE Electron Devices Meeting IEDM 1998, pp. 291–294.
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[2] M.R. Baklanov, K. Maex, Porous low dielectric constant materials for microelectronics, Philos. Transact. A Math. Phys. Eng. Sci. 364 (2006) 201–215. [3] K. Vanstreels, C. Wu, M. Gonzalez, D. Schneider, D. Gidley, P. Verdonck, M. Baklanov, Effect of pore structure of nanometer scale porous films on the measured elastic modulus, Langmuir 29 (2013) 12025–12035. [4] K. Vanstreels, I. De Wolf, H. Zahedmanesh, H. Bender, M. Gonzalez, J. Lefebvre, S. Bhowmick, In-situ scanning electron microscopy study of fracture events during back-end-of-line microbeam bending tests, Appl. Phys. Lett. 105 (2014) 213102, http://dx.doi.org/10.1063/1.4902516. [5] P. Shieh, L.C. Bassman, D.K. Kim, K.C. Saraswat, M.D. Deal, J.P. McVittie, Integration and reliability issues for low capacitance air-gap interconnect structures, Proc. IEEE International Interconnect Technology Conference IITC 1998, pp. 125–127. [6] R.J.O.M. Hoofman, R. Daamen, D. Ernur-Badaroglu, A. Humbert, S.L. Shue, C.H. Yu, Air gaps as a viable alternative for low-k dielectrics in future technology nodes, Proc. Advanced Metallization Conference 2007, pp. 411–417. [7] J. Noguchi, K. Sato, N. Konishi, S. Uno, T. Oshima, K. Ishikawa, H. Ashihara, T. Saito, M. Kubo, T. Tamaru, Y. Yamada, H. Aoki, T. Fujiwara, Process and reliability of air-gap Cu interconnect using 90-nm node technology, IEEE Trans. Electron Devices 52 (2005) 352–359. [8] L.G. Gosset, V. Arnal, P. Brun, M. Broekaart, C. Monget, N. Casanova, M. Rivoire, J.C. Oberlin, J. Torres, Integration of SiOC air gaps in copper interconnects, Microelectron. Eng. 70 (2003) 274–279. [9] S. Nitta, D. Edelstein, S. Ponoth, L. Clevenger, X. Liu, T. Standaert, Performance and reliability of airgaps for advanced BEOL interconnects, Proc. IEEE International Interconnect Technology Conference IITC 2008, pp. 191–192. [10] X. Zhang, S.-K. Ryu, R. Huang, P.S. Ho, J. Liu, D. Toma, Mechanical stability of air-gap interconnects, Futur. Fab Int. 27 (2008). [11] V. Kumaresan, C.J. Wilson, P. Verdonck, E. Van Besien, F. Lazzarino, V. Truffert, J. Bömmels, Zs. Tőkei, T.K.S. Wong, Simulation and measurement of the capacitance benefit of air gap interconnects for advanced technology nodes, Microelectron. Eng. 120 (2014) 90–94. [12] P.S. Ho, K.D. Lee, S. Yoon, X. Lu, E.T. Ogawa, Effect of low k dielectrics on electromigration reliability for Cu interconnects, Mater. Sci. Semicond. Process. 7 (2004) 157–163. [13] G.G. Stoney, The tension of metallic films deposited by electrolysis, Proc. R. Soc. Lond. A 82 (1909) 172–175. [14] H. Zahedmaesh, M. Gonzalez, K. Vanstreels, A numerical study on nano-indentation induced fracture of low dielectric constant brittle thin films using cube corner probes, Microelectron. Eng. 156 (2016) 108–115. [15] H. Zahedmanesh, M. Gonzalez, I. Ciofi, K. Croes, J. Bömmels, Zs. Tőkei, Design considerations for the mechanical integrity of airgaps in nano-interconnects under chip– package interaction; a numerical investigation, Microelectron. Reliab. (2016), http://dx.doi.org/10.1016/j.microrel.2016.01.015 (in press). [16] L.C. Bassman, R.P. Vinci, B.P. Shieh, D.-K. Kim, J.P. McVittie, K.C. Saraswat, M.D. Deal, Simulation of the effect of dielectric air gaps on interconnect reliability, MRS Proc. 473 (1997) 323–328, http://dx.doi.org/10.1557/PROC-473-323. [17] C.J. Zhai, H.W. Yao, A.P. Marathe, P.R. Besser, R.C. Blish, Simulation and experiments of stress migration for Cu/low-k BEoL, IEEE Trans. Device Mater. Reliab. 4 (2004) 523–529. [18] Raphael Interconnect Analysis Program Reference Manual, Version D-2010.03, Synopsys Inc., Mountain View, CA, 2010. [19] W. Zhou, J. Yang, Y. Li, A. Ji, F. Yang, Fracture properties of PECVD silicon nitride thin films by long rectangular membrane bulge Test, Proc. of the 3rd IEEE Int. Conf. on Nano/Micro Engineered and Molecular Systems 2008, pp. 261–264. [20] C.J. Wilson, C. Zhao, L. Zhao, T.H. Metzger, Zs. Tőkei, K. Croes, M. Pantouvaki, G.P. Beyer, A.B. Horsfall, A.G. O'Neill, Study of the effect of dielectric porosity on the stress in advanced Cu/low- k interconnects using x-ray diffraction, Appl. Phys. Lett. 94 (2009) 181914, http://dx.doi.org/10.1063/1.3133345. [21] C.J. Wilson, K. Croes, C. Zhao, T.H. Metzger, L. Zhao, Gerald P. Beyer, Alton B. Horsfall, Anthony G. O'Neill, Zsolt Tőkei, Synchrotron measurement of the effect of linewidth scaling on stress in advanced Cu/low-k interconnects, J. Appl. Phys. 106 (2009) 053524, http://dx.doi.org/10.1063/1.3212572.
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Stress analysis of airgaps under process-induced thermo-mechanical loads Houman Zahedmanesh ⁎, Mario Gonzalez, Ivan Ciofi, Kristof Croes, Jürgen Bömmels, Zsolt Tőkei imec, Kapeldreef 75, Leuven 3001, Belgium
a r t i c l e
i n f o
Article history: Received 4 June 2015 Received in revised form 12 February 2016 Accepted 13 February 2016 Available online 15 February 2016 Keywords: Airgap Ultra low-k dielectric (ULK) Interconnect Finite element model (FEM)
a b s t r a c t In order to understand the state of process induced stresses in airgap interconnect structures fabricated by the etch-back approach, finite element (FE) models of a 90 nm pitch interconnect were developed and a stress analysis of the structure was conducted as a function of the dielectric liner (silicon nitride) and metal barrier (MB) thicknesses. Models of similar structures without airgaps were also developed and the stresses were evaluated as a benchmark case. In addition, a static field solver was used to extract the capacitance of the interconnect structure and evaluate the capacitance reduction by introducing airgaps compared to structures without airgaps. The results identified the sidewall dielectric liner as a critical location where high tensile stress concentration can result in failure of structures under thermo-mechanical loads. Reducing the thickness of the MB and the dielectric liner simultaneously to 1 nm and 2 nm respectively, minimized metal barrier tensile stresses but increased the tensile stress in the dielectric liner dramatically to 1 GPa. Meanwhile, this configuration provided the lowest capacitance and reduced the capacitance of the interconnect by 27% compared to a similar structure without airgaps. In general, reducing the thickness of the MB decreased its stresses both in interconnect structures with and without airgaps. © 2016 Elsevier B.V. All rights reserved.
1. Introduction The performance of ultra large scale integration (ULSI) integrated circuits is limited by the resistive and capacitive (RC) delays in the interconnect [1]. This challenge necessitates development of technologies that reduce resistances and capacitances. Moreover, interconnect capacitance also entails excessive interconnect cross-talk and power dissipation that underlines the importance of capacitance mitigation. Therefore, novel inter-line ultra-low-k dielectric materials (ULK) with k values lower than 2.5 have been employed whereby the k value is further reduced by inclusion of pores into the dielectric material to form porous low-k materials [2]. Nonetheless, as the porosity of the ULK materials is increased, their mechanical properties deteriorate dramatically which constitutes a major integration challenge [3]. ULK materials suffer from lower stiffness, low fracture toughness and inferior adhesion mainly due to their porous structure which renders them susceptible to damage during the Damascene process steps [3,4]. This dramatic reduction of mechanical robustness of ULK materials constitutes a limit for further lowering the effective k value. Therefore, although integration of ULK materials has led to a considerable reduction of interconnect capacitive delay, currently there is a significant effort ongoing for replacing the interline dielectric fully with air by integration of airgaps given that air offers the ⁎ Corresponding author. E-mail address: [email protected] (H. Zahedmanesh).
http://dx.doi.org/10.1016/j.mee.2016.02.019 0167-9317/© 2016 Elsevier B.V. All rights reserved.
best dielectric constant value of 1 [5–9]. However, implementing airgaps adds further to the integration challenge which necessitates a thorough understanding of the stress state of the interconnect structure and the impact of each process step [10]. One of the potential airgap integration approaches is the etch-back approach where the inter-line low-k is removed by an etch step [10]. However, in order to ensure mechanical stability and chemical stability of such a structure, it is necessary to implement a relatively stiff dielectric liner such as silicon nitride to cover the metal structure which prevents oxidation of the metal and also provides mechanical support and stability to the airgap and metal lines [10,11]. Process induced stresses not only can complicate interconnect integration itself, but also will have important implications for reliability under chip package interaction (CPI) and electro-migration (EM) loads. Tensile hydrostatic stresses in copper lines facilitate EM induced void formation [12] and also expansion of copper due to thermal effects or EM induced extrusion can lead to airgap failure at the liner or MB. Specifically, as the inter-line space is down-scaled it is necessary to reduce the thickness of the liner to ensure capacitance reduction and that can potentially constitute a reliability challenge as the stiff liner will be compromised [11]. Clearly therefore, it is of outmost importance to devise methodologies that provide quantitative understanding of the process induced interconnect stresses. To this end, in this study numerical models of interconnect structures are developed in order to investigate the mechanical stresses and shed light on the influence of two main airgap design parameters for the etch-back approach, (i) the thickness of the metal barrier (MB)
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Fig. 1. Summary of the modeled process steps.
and (ii) the thickness of the dielectric liner and also to devise potential strategies for stress mitigation. 2. Methods 2.1. Stress analysis A 2D plane strain FE model of a single level interconnect structure with 90 nm pitch and line aspect ratio of 1 was developed within the MSC-Marc® FEM package. Two groups of interconnect structures were modeled; (i) the mainstream structure with ULK without airgaps and (ii) similar structures but with airgaps using the etch-back process. In order to model the deposition of each material, elements corresponding to each material were activated at each subsequent analysis step of the multistep thermo-mechanical simulation, see Fig. 1. The model was discretized using solid planar quadrilateral plane-strain elements (element type 11 in MSC-Marc® FEM package) and approximately 800–1000 elements were used to model each line structure. The existing stresses within each deposited material, in addition to the thermal expansion mismatch, are induced due to complex molecular/ atomic re-organization during deposition. In order to capture the overall effect of such phenomena, the intrinsic stress of each material was extracted from the wafer bowing experiments on single blanket layers using the Stoney's approach (Table 1) [13]. Subsequently, the intrinsic stress values were implemented in the FE model by including stress initial conditions in each step of the simulation which were allowed to reach an equilibrium state during the step. Airgap formation in the etch-back process was modeled by deactivation of intermetallic ULK related FE elements. Ultimately a heat-up step of 200 °C was applied to the sequentially built-up structure in order to investigate the stresses at elevated temperatures, specifically the ability of the airgaps to withstand copper expansion without failure. The mechanical and thermal material properties used in the simulations are summarized in Table 2. In order to understand the variation in stresses of copper lines, MB and the dielectric liner with the thickness, the thickness of the MB was altered from 1 to 6 nm and the thickness of the dielectric liner from 2 to 10 nm at the sidewall whilst it was presumed that the thickness of the liner at the top of the liner is twice the thickness of the liner at the sidewall i.e. (4–20 nm). The copper line dimensions were
kept constant. Interconnect mechanical failures are mainly brittle cracking events specifically given the low fracture toughness and adhesion of the low-k dielectrics and the dramatic dimensional downscaling of copper lines [4,14,15]. Such brittle mechanical failures have been shown to be driven by the maximum tensile principal stresses [14–16]. Therefore, in this paper the maximum principal stresses are reported for the dielectric liner and MB. On the other hand, the hydrostatic stresses in copper are also reported given that hydrostatic stress is a predictor of electro-migration and stress migration [16,17]. 2.2. Capacitance analysis Capacitance models of the interconnect structure were developed using the Raphael™ field solver [11,18] and the various designs were simulated consistent with the case studies discussed for the mechanical model by interfacing Raphael™ with the Optimus™ software. The capacitance of the airgapped interconnects were benchmarked against a similar structure but with the mainstream technology (i.e. without airgaps and using ULK material with a k = 2.4) to decipher the capacitance benefits when incorporating airgaps. The capacitance value is the total capacitance including the capacitance of the line with the two neighboring lines and the top and bottom lines presuming a Manhattan interconnect structure. The dielectric barrier and liner material were considered to be silicon nitride with a dielectric constant of 7.3 and the k value of the ULK was set to 2.4 in all cases. 3. Results and discussion The stresses in the interconnect structure were calculated using the developed FE model as a function of MB and dielectric liner thickness. The dielectric liner was found to endure highest tensile maximum principal stresses at the sidewall compared to MB, see Fig. 2. In the case were the thickest MB and dielectric liner were implemented (i.e. 6 nm MB and 10 nm liner) the maximum principal stresses reached 628 MPa in the liner and 255 MPa in MB. In contrast the thinnest MB and liner within the studied range resulted in a liner maximum principal stress of Table 2 Thermal and mechanical material properties used in the simulations. Material
Table 1 Intrinsic stresses obtained from wafer bowing. Layer
Thickness (nm)
Residual Stress (MPa)
Low-k (OSG 2.4) MB (Ta) Liner (silicon nitride) Cu
100 7 20 60
+40 (tensile) −1375 (compressive) −120 (compressive) +500 (tensile)
Low-k organo-silicate glass with k value of 2.4 (OSG 2.4) MB (Ta) Liner (silicon nitride) Cu
Young's modulus (GPa) 9 186 265 117
Poisson's ratio
Coefficient of thermal expansion (CTE)
0.2
1.2 × 10−5
0.34 0.27 0.3
6.3 × 10−6 1.5 × 10−6 1.67 × 10−5
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Fig. 2. Stress distribution in airgapped interconnect with MB thickness = 6 nm, sidewall liner thickness = 10 nm, top liner thickness = 20 nm at a temperature of 200 °C. (a) Stresses in the fully integrated structure (b) stresses in the silicon nitride dielectric liner (c) stresses in the MB. Arrows show the location of the highest tensile stresses. Positive values show tensile stresses.
1 GPa and 76 MPa in MB and again the dielectric liner at the sidewall endured the highest stresses, see Fig. 3. Figs. 4 and 5, summarize the variation in maximum principal stress values in the MB and the liner with thickness, respectively. It can be seen that simultaneous reduction of the thickness of the MB and the liner, increases the liner tensile stresses specifically at the sidewall reaching maximum principal stresses of up to 1 GPa, see Fig. 4. Comparing the calculated value of the maximum principal stress in the dielectric liner which is assumed to be silicon nitride with an illustrative value of 1.54 ± 0.37 GPa for the ultimate tensile strength of silicon nitride [19], indicates that although ideally a 2 nm silicon nitride liner should still withstand the incurred stresses but the chances of failure due to imperfections in the processes and material, which cannot be fully recapitulated by an idealistic model, indeed increase at such high calculated stress levels. In stark contrast to stresses in the dielectric
liner, simultaneous reduction of the MB and liner thicknesses reduced MB tensile stresses, see Fig. 5. In addition, liner stresses were found to be more strongly influenced by variations in the liner thickness rather than the MB thickness, while MB stresses were more strongly influenced by variation in MB thickness, see Figs. 4 & 5. It was found that depending on the combination of MB and liner thicknesses, MB and liner stresses can vary between 76 and 274 MPa (3.3 fold) and 692–1131 MPa (1.4 fold) respectively, which demonstrates that MB stresses are more sensitive to variations of thicknesses compared to liner stresses. In this context, comparing the stress values in the MB in airgap models with that of the non-airgap structures can provide a better understanding of the influence of airgaps. In a similar structure but without airgaps, increasing the thickness of the MB from 1 nm to 6 nm resulted in maximum principal stresses of 22 MPa and 243 MPa in the MB, respectively. Comparing these values with the
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Fig. 3. Stress distribution in airgapped interconnect with MB thickness = 1 nm, sidewall liner thickness = 2 nm, top liner thickness = 4 nm at a temperature of 200 °C. (a) Stresses in the fully integrated structure (b) stresses in the silicon nitride dielectric liner (c) stresses in the MB. Arrows show the location of the highest tensile stresses. Positive values show tensile stresses.
values from airgapped structures reveals that the MB stresses are only marginally higher in the airgapped structures compared to the case without airgaps, see also Fig. 6. As discussed, our model shows that both in the airgapped interconnects and in the interconnects without airgap, increasing MB thickness resulted in its elevated stress level unanimously. This finding, although counterintuitive at the first glance, was found to be due to the dominant bending deformation mode in the MB which is shown in Fig. 6 (i.e. thinner MB is more compliant in bending and endures lower stress). Important to note is that, although reducing the MB thickness will decrease its stresses, it provides lower mechanical support to the copper lines and instead follows the deformation of copper. In order to prevent potential outward extrusion of the copper lines, this lack of mechanical support by the MB needs to be compensated by the dielectric liner. In addition to MB and liner stresses, the stress state of the copper lines can also have crucial implications for the reliability of airgapped structures. Tensile hydrostatic stresses in copper lines facilitate void formation due to EM [12]. Therefore, a combination of MB and liner thicknesses that can induce a more compressive hydrostatic stress state in copper lines can help reduce EM induced void formation. In this context, Fig. 7 shows the variation of the hydrostatic stress in the copper lines during the consecutive steps of the simulated process steps. The simulations show that the hydrostatic stress state in copper lines is more
compressive in the case of airgaps compared to without airgaps which can be potentially beneficial from an EM induced voiding standpoint. Indeed, at the final heat-up step the hydrostatic stress is compressive throughout the entire cross section of the copper line in the airgapped structure while in the structure without airgaps only the top part of the copper line is compressive. Copper endures a highly tensile inplane stress when deposited within the etched trench in the low-k [20,21]. The tensile stress in the copper line is partly released following low-k removal from the lateral sides of the copper lines during airgap formation as shown in Fig. 7. In the case where airgaps are not introduced, the tensile stress remains in the copper line given that the lowk at either sides of the line doesn't allow full stress relaxation. Of course, during low-k etch-back for airgap formation the MB remains intact, therefore, a thicker metal barrier resists the relaxation of the tensile stress of the copper more than a thin metal barrier. This prediction by the presented FE model is also consistent with experimental measurements of stresses in copper lines using X ray diffraction (XRD) [20,21]. The liner deposition step proceeds this stress relaxation phase and in comparison was found to have a minor influence on the hydrostatic stresses in the copper lines for relatively thin liners. As such, minimizing the MB thickness and increasing the thickness of the liner induces more compressive hydrostatic stresses in the copper lines given that the thin and compliant MB allows for maximum relaxation of the tensile stresses
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Fig. 4. Maximum tensile stresses in liner as a function of MB and liner thicknesses.
in the copper during the etch-back step for airgap formation and the thicker liner resists the expansion of copper at elevated temperatures generating compressive stresses in the copper. In order to devise strategies for stress mitigation it is essential to examine the capacitive implications of changing liner and MB thicknesses and to ensure that any stress mitigation approach is also consistent with the main purpose of airgap implementation which is minimizing the capacitance. Given that the copper line dimensions were assumed constant at 45 nm width and an aspect ratio of 1 in all case studies, changes of the MB and the liner thickness only influence
the capacitance of the line. To this end, the capacitance of the interconnect structure was calculated using static field stimulations for the airgapped structures and were benchmarked against a similar structure without airgaps and with a ULK 2.4 inter-line dielectric, a 10 nm silicon nitride dielectric barrier and a 2 nm MB, for which the total capacitance was calculated to be 0.170217 fF/μm, see Fig. 8. As shown in Fig. 8, isocapacitance design regions can be identified where different combinations of MB and sidewall liner thicknesses result in the same capacitance. The highest relative reduction in capacitance is clearly the case where a combination of minimum 1 nm MB thickness and 2 nm liner
Fig. 5. Maximum tensile stresses in MB as a function of MB and liner thicknesses.
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Fig. 6. Stress distribution and deformation of the MB in the fully processed BEOL at 200 °C, deformations are exaggerated at 100×. In the airgap cases the dielectric liner thickness is 2 nm at the sidewall and 4 nm at the top.
Fig. 7. Hydrostatic stresses in the Cu lines of (left) a structure with airgap (right) a similar structure without airgap, and its variation throughout the modeled process steps. The MB thickness in both cases is 1 nm and the thickness of the dielectric liner in the airgapped case is 2 nm. Stress contours are related to stresses at 200 °C.
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Fig. 8. Comparison of capacitance using airgaps with a similar structure without airgaps in percentage, each color band represents an iso-capacitance region where the difference of consecutive color bands is 1% and positive percentage shows lower capacitances compared to the reference case (reference case: ULK 2.4, 10 nm silicon nitride dielectric barrier and 2 nm metallic barrier).
thickness is implemented where the simulation showed that airgaps resulted in 27% reduction in capacitance compared to the benchmark case. In order to obtain this capacitance reduction the possible combinations of liner and MB thicknesses are limited to 1 nm MB and 2 nm liner where the mechanical model predicts the lowest MB stress of 76 MPa and the maximum liner stress of 1 GPa at the sidewall. Hence, under this configuration the vulnerable location is the sidewall liner. On the other hand, implementing the thickest MB of 6 nm and liner of 10 nm leads to 30% increase in capacitance compared to the benchmark case with ULK which clearly violates capacitance reduction. However, between these two extremes there are cases where within the isocapacitance bands, various combinations of MB and liner thicknesses can be implemented that result in the same capacitance, although
they have different mechanical implications. As an example, from Fig. 8 it can be seen that a capacitance reduction of 10% can be achieved by airgap implementation using either of the following designs (i) MB thickness = 1 nm and sidewall liner thickness = 7 nm or (ii) MB thickness = 6 nm and sidewall liner thickness = 3 nm. Interestingly, design (i), compared to design (ii), will reduce MB stresses by almost 70% while liner stresses increase negligibly. In another case from Fig. 8 it is clear that 15% reduction in capacitance can be achieved by either (i) MB thickness = 3 nm and sidewall liner thickness = 4.5 nm or (ii) MB thickness = 6 nm and sidewall liner thickness = 2 nm. Using design (i), compared to design (ii), will reduce MB stresses by 40% and liner stresses change negligibly. Also, 20% reduction in capacitance can be achieved by either of the designs,
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(i) MB thickness = 1 nm and sidewall liner thickness = 4.2 nm or (ii) MB thickness = 4 nm and sidewall liner thickness = 2 nm. The former can reduce the MB stresses by about 50% while liner stress changes negligibly. As such, the combination of MB and liner thicknesses within each iso-capacitance design space can be configured to mitigate process induced stresses without compromising capacitance. In general, keeping the thinnest MB possible within the iso-capacitance design space and implementing a liner thicker than the MB, yields the lowest possible stresses in both the MB and liner for the same capacitance. Finally, it is worth mentioning that in this study it was assumed that within the investigated range of thickness variations of MB and liner, the film's residual stress derived from wafer bow measurements is constant. Given that the range of variations in MB and dielectric liner thicknesses studied were relatively small, this constitutes a plausible assumption. Nonetheless, film residual stresses can be potentially influenced by thickness variations which require further investigation using wafer bow measurements on MB and dielectric films with different thicknesses to further ascertain this assumption within the studied range. 4. Conclusions We previously addressed the capacitance trade-off between dielectric liner thickness and line-to-line dimensions where we concluded that the capacitance benefit of airgaps reduces with scaling due to the increasing proportion of space occupied by the liner [11]. This motivated the current study to investigate the influence of thickness variations on mechanical stresses in MBs, liners and also copper lines specifically for the etch-back airgap integration process. The highest value of maximum principal stress was identified to occur at the sidewalls of the dielectric liner. MB stresses were found to have a direct relation with its thickness and increasing the MB thickness from 1 nm to 6 nm significantly increased maximum principal stresses within the MB both where airgaps were implemented and also in interconnects without airgaps. Capacitance simulations as a function of the MB and the liner thickness identified iso-capacitance design spaces where for each target capacitance various combinations of MB and liner thicknesses could be potentially implemented. The mechanical model showed that the stresses can be mitigated without compromising the capacitance by implementing the thinnest MB and thickest liner possible within the iso-capacitance design space for a target capacitance. It was also shown that airgaps result in a more compressive hydrostatic stress state in the copper lines compared to the interconnects without airgaps and hence could potentially help reduce EM induced void formation. References [1] K. Yamashita, S. Odanaka, Impact of crosstalk on delay time and a hierarchy of interconnects, Proc. IEEE Electron Devices Meeting IEDM 1998, pp. 291–294.
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