Study of the cross contamination effect on post CMP in situ cleaning process

Microelectronic Engineering 136 (2015) 36–41

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Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee

Study of the cross contamination effect on post CMP in situ cleaning process Hong Jin Kim a,⇑, Girish Bohra b, Hyucksoo Yang b, Si-Gyung Ahn a, Liqiao Qin a, Dinesh Koli a a b

Advanced Module Engineering (AME), GLOBALFOUNDRIES, 400 Stone Break Road Extension, Malta, NY 12020, USA Technology Development Yield Enhancement (TDYE), GLOBALFOUNDRIES, 400 Stone Break Road Extension, Malta, NY 12020, USA

a r t i c l e

i n f o

Article history: Received 1 December 2014 Received in revised form 12 February 2015 Accepted 18 March 2015 Available online 24 March 2015 Keywords: CMP Brush scrubber Cross contamination

a b s t r a c t Scaling of gate lengths has led to significant improvement in semiconductor device performance. However, fabrication complexities have also increased and surface defects control becomes very critical for yield enhancement. In particular, chemical mechanical polishing (CMP) process is considered as one of the dirtiest processes to wafer surface contamination. And brush scrubber is the most effective method for post CMP in situ cleaning. Many literatures have reported brush scrubber mechanism and proposed particle removal efficiency based on remaining particles at post brush scrubber cleaning. However, concerns associated with brush to wafer surface contamination have not been addressed properly although real manufacturing has a lot of issues on that effect. This paper discuss cross contamination at brush scrubber process and emphasize that optimum cleaning should consider brush cross contamination in addition to brush particle removal efficiency. Ó 2015 Elsevier B.V. All rights reserved.

1. Introduction Chemical mechanical polishing (CMP) becomes an enabling technology for Fin Field-Effect Transistor (FinFET) device fabrication and process complexities are very much increased as compared to the planar device nodes [1–5]. In addition to its planarization function, defect reduction in the CMP process itself draws serious attention for device manufacturing. Major defects from CMP process are slurry abrasive particle, abraded film, organic residue from polishing pad, particles from the tool, and micro scratches [6]. CMP tool has polisher module and in situ cleaning module which can drive defects on the wafers. Except for micro scratch, in situ cleaning is mainly responsible for particles removal before wafer dried out. Depending on the tool manufacturer, in situ cleaning module use different cleaning processes, such as megasonic and brush scrubber. Among various cleaning methods, brush scrubber cleaning is the most popular and effective method in CMP tool because of its single wafer processing, low cost of ownership (COO) and high cleaning performance by physical force. Most of the brushes used in CMP in situ cleaning are made of polyvinyl alcohol (PVA) material and composed of a lot of cylindrical nodules on the surface. Each cylindrical nodule has meshed structure, with lots of pores. Cleaning performance is determined

⇑ Corresponding author. E-mail address: [email protected] (H.J. Kim). http://dx.doi.org/10.1016/j.mee.2015.03.033 0167-9317/Ó 2015 Elsevier B.V. All rights reserved.

by kinematics of brush module, brush design, mechanical properties of brush and chemicals flowed in the brush [7–9]. For FinFET devices, post CMP defects can directly impact yield loss and critical killer defect size becomes very small with shrinking gate lengths. For example, W residue and organic residues can be root cause of M1 electrical short and open contacts [5,10]. Multiple studies and research works have been done to analyze brush cleaning performance with focus on particle adhesion and removal mechanism, tribology and contact mechanics, and cleaning chemicals [7,11– 12]. From these studies, the importance of hydrodynamic drag force and criteria for particle removal was highlighted. Recent study by Sun et al. [13] also outlined the effect of brush design and its mechanism for particle removal. However, all studies have investigated only particle removal aspects, and contamination from brush itself was not considered much, which can be direct source of organic residues. This paper shows strong evidence for particle contamination coming from brush to the wafer surface and results of experiments performed to understand the effects of brush rotation speed, brush gap and de-ionized wafer (DIW) flow rate for brush generated particle contamination.

2. Experimental details Reflection-LK model CMP tool from Applied Materials Inc. was used for post CMP in situ cleaning experiment. Its post polishing cleaning module is composed of megasonic tank, 1st brush

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scrubber, 2nd brush scrubber, and isopropyl alcohol (IPA) dryer. The schematic of brush cleaning module is shown in the Fig. 1. Wafer is located vertically in the brush cleaning box and wafer as well as brushes is rotating for effective particle removal. It also has spray bars above brushes and either chemical or DIW flows from spray bar and flows through the brush core. In order to investigate particle cross contamination effect, 300 mm tetraethyl orthosilicate (TEOS) blanket wafers were used for this study. TEOS thickness was 3 kÅ for all experimental conditions. To focus on only brush effect, TEOS blanket wafers ran in the one brush module (processed with 1st brush scrubbing) only without polishing, and dried out. To explore slurry abrasive contamination, wafers ran with silica slurry CMP before experiment and brush lifetime less than 500 wafers was used for all these experiments. Table 1 gives summary of details for experimental conditions. Rotational speed, brush gap, and DIW flow rate were set as variables for these experiments. We define brush gap as distance between wafer surface and brush nodule, which means smaller gap creates high pressure to the wafer. Post defect characterization was performed by SP3 tool from KLA Tencor Inc., which is commonly used tool for defect inspection in the semiconductor area. And inspection resolution is to detect defect size of 65 nm and above. Scanning electron microscopy (SEM) review was done afterwards to identify types of each defect. Since experiment performed without polishing, post defects are purely driven by cross contaminated particle from brush (here, it is defined as CCP). Except DIW, no other chemical was flowed in the brush clean module. And effects of brush gap and DIW flow rate for CCP on the TEOS wafer were studied.

Table 1 Experimental conditions. Wafer rotation (rpm)

Brush rotation (rpm)

1 2

0 50

3

50

0 100, 200, 300, 400, 500, 600 400

4

50

400

Brush gap (mm)

0.5 0.5 0, 0.25, 0.5, 0.75, 1.0, 1.25, 1.5 0.5

DI flow (ml/ min) 1500 1500 1500 500, 750, 1000, 1250, 1500

(a)

3. Results and discussions Fig. 2(a) shows wafer defect map and defect images from experimental condition 1 in Table 1. Before running wafer, pre-test wafer map is also provided in the same figure, and its total defects count (TDC) is less than 20, which can be ignored at post defect analysis. With brush contacting wafer with 0.5 mm brush gap for 30 s, strong brush nodule marks are observed as shown in Fig. 2(a) and adder defect count is over 3000. Defect was identified with SEM and most defects were revealed as either silica particles

wafer Nodule

Brush

Fig. 1. Schematic of brush cleaner module in LK CMP tool.

(b) Fig. 2. (a) Wafer defect map from SP3 inspection before and after brush contact and (b) defect images from (a) (after brush contact with experimental condition 1 at Table 1).

or organic materials, of which images are shown in Fig. 2(b). Silica particle is from the slurry abrasive trapped inside the brush and organic residue is from brush itself or pad debris. Since brush and wafer were not rotated in this case, these defects are solely originated from the brush and it is clear that DIW flow from brush to wafer moved these particles from brush to the wafer surface. Effect of brush rotation speed on the CCP is shown in the Fig. 3(a) and corresponding defect map is given in Fig. 3(b). At low brush rotation (100 RPM), a lot of defects are observed in the wafer and defect map shows strong brush nodule mark as well. As rotation speed increase, CCP drops quickly and it has minimum CCP count for 400 RPM condition. The defect map shows no brush nodule signature at higher RPM conditions but defects spread out across the wafer. From the result, it indicates that longer brush contact time (i.e., low RPM) increases CCP to the wafer surface. With Increased brush rotating speed, brush cleaning is working more efficiently and CCP can be removed. However, the frequency of brush contact also increases as brush rotating speed increases, resulting in increasing behavior of CCP at over 400 RPM condition.

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Parcle Count

10000

1000

100 100

200

300

400

500

600

Brush Rotaonal Speed (RPM)

(a)

RPM = 100

RPM = 200

RPM = 300

RPM = 400

RPM = 500

RPM = 600

(b) Fig. 3. (a) Particle counts on the wafer surface contaminated from brush with respect to brush rotation speed, and (b) wafer defect map with respect to brush rotation speed.

The result also suggests longer brush contact is more vulnerable to defect generation (i.e., CCP) rather than higher brush contact frequency. The effect of brush gap is summarized in Fig. 4(a) and corresponding wafer maps are given in Fig. 4(b). As mentioned earlier, the smaller number for brush gap indicates the higher contact pressure between wafer and brush nodule. As shown in the Fig. 4(a), except for 0 brush gap, defect count increases as brush gap decreases. Increased contact pressure and contact area

according to brush gap decrease can accelerate CCP. And at the same time, high contact pressure is efficient for particle removal [7]. However, this result indicates that the CCP is more dominant than particle removal by scrubbing. Due to the non-uniformity in brush nodule height, several nodules at 0 brush gap barely touches wafer as shown in Fig. 4(b) and CCPs are hard to be removed, which results in higher CCP count remain. During the brush scrubbing, DIW flows through the brush core and hydrodynamics of fluid, which is one of the key parameter to

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Parcle Count

10000

1000

100 -1.25

-1

-0.75

-0.5

-0.25

0

Brush Gap (mm)

(a)

Gap = -1.25mm

Gap = -1.0mm

Gap = -0.5mm

Gap = -0.25mm

Gap = -0.75mm

Gap = 0mm

(b) Fig. 4. (a) Particle counts on the wafer surface contaminated from brush with respect to brush gap and (b) wafer defect map with respect to brush gap.

determine particle removal efficiency, is strongly influenced by DIW flow rate. The investigation of DIW flow rate effect on CCP was also checked and a plot of CCP with DIW flow rate is plotted in Fig. 5(a). Although DIW flow rate increased up to 1500 ml/min from 250 ml/min, CCP is not as much changed as it was changed with brush rotation speed or brush gap (shown in Figs. 3 and 4 trend). Although it is expected that high flow DIW rate can transfer more particles from brush to wafer surface, this result suggests that CCP is more sensitively influenced by real contact conditions between brush nodule and wafer surface.

Many literatures have reported brush particle removal efficiency during post in situ CMP cleaning based on the particle adhesion and removal force [7–9,12]. However, most of them have not paid proper attention to the particle transfer from brush to wafer, although it is widely known that removed particle is absorbed in the brush and organic particles remain there in the brush. While brush is being compressed to the wafer, those particles contaminate wafer surface depending on scrubbing conditions and particles are removed by physical force of compressed brush. Combined effect of particle removal and generation (which

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Parcle Count

10000

1000

100 250

500

750

1000

1250

1500

DI Flow Rate (ml/min)

(a)

Flow rate = 250 ml/min

Flow rate = 500 ml/min

Flow rate = 750 ml/min

Flow rate = 1000 ml/min

Flow rate = 1250 ml/min

Flow rate = 1500 ml/min

(b) Fig. 5. (a) Particle counts on the wafer surface contaminated from brush with respect to DIW flow rate through the brush core and (b) wafer defect map with respect to DIW flow rate though the brush core.

is defined as CCP in this paper), leads to optimum process condition. From CCP aspect, brush RPM is the most sensitive parameter to minimize wafer contamination and get cleanest wafer surface. Although experimental results in this paper do not provide the most effective or optimal process condition to the particle removal efficiency, this paper gives an important parameter to consider post CMP in-situ cleaning process optimization.

4. Summary and conclusions This paper presents evidence for wafer contamination caused by brush to the wafer surface (cross contaminated particle, CCP) during post CMP in situ cleaning process. CCP generation is mostly driven by brush nodule contact and it strongly depends on brush cleaning recipe configuration. These experimental results shows that brush rotation speed is the most critical parameter to

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determine CCP and DIW flow is not much sensitive to CCP generation. During brush scrubbing, CCP as well as particle removal occur simultaneously and these two processes together determine optimum process conditions for post CMP in situ cleaning. Particle adhesion and removal models have provided best particle removal conditions so far. However the realistic defectivity is more complicated as device gate lengths shrink towards their fundamental limits, making CMP process more challenging and complicated. CCP should be considered as one of the most important mechanism for brush scrubber cleaning process to maximize particle removal efficiency at the end of process. References [1] Yongsik Moon, in: Inter. Conf. CMP/Planar. Technol. (ICPT), Oct. 30, 2013. [2] Sidney Hueya, Balaji Chandrasekarana, Doyle Bennetta, Stan Tsaia, Kun Xua, Jun Qiana, Siva Dhandapania, Jeff Davida, Bogdan Swedeka, Lakshmanan Karuppiaha, ECS Trans. 44 (2012) 543–552. [3] Mahadevaiyer Krishnan, Jakub W. Nalaskowski, Lee M. Cook, Chem. Rev. 11 (2010) 178–204.

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[4] Jiyoung Kim, Angustin J. Hong, Masaaki Ogawa, Siguang Ma, Emil B. Song, YouSheng Lin, U-In Chung, Kang L. Wang, in: Symp. VLSI Technol., Jun. 17–19, 2008, pp. 122–123. [5] Hong Jin Kim, Robert Solan, Liqiao Qin, Si-Gyung Ahn, Bohra Girish, Dinesh Koli, Venugopal Govindarajulu, Yongsik Moon, in: Center For Advanced Materials Processing (CAMP) 19th international CMP symposium, Aug. 10, 2014. [6] Liming Zhang, Srini Raghavan, Milind Weling, J. Vac. Sci. Technol. B 17 (1999) 2284. [7] Ahmed A. Busnaina, Hong Lin, Naim Moumen, Jiang-wei Feng, Jack Taylor, IEEE Trans. Semicond. Manuf. 14 (4) (2002) 374–382. [8] Zuqiang Qi, Wanjia Lu, Weiming Lee, Int. J. Mach. Tools Manuf. 85 (2014) 30– 35. [9] K. Xu, R. Vos, G. Vereecke, G. Doumen, W. Fyen, P.W. Mertens, M.M. Heyns, C. Vinckier, J. Fransaer, F. Kovacs, J. Vac. Sci. Technol. B 23 (5) (2005) 2160– 2175. [10] Y.C. Ee, S.K. Tan, C.S. Chee, J.B. Tan, B.C. Zhang, Y.K. Siew, P.K. Tan, F. Zhang, K.H. Lai, M.S. Chettiar, X.B. Wang, Thomas Fu, L.C. Hsia, 65 nm Yield Detractor Caused by M1 Filament Shorts and Solution, Publications, PDF Solution, . [11] Yair Ein-Eli, David Starosvertsky, Electrochim. Acta 52 (2007) 1825–1838. [12] Fan Zhang, Ahmed A. Busnaina, Goodarz Ahmadi, J. Electrochem. Soc. 146 (7) (1999) 2665–2669. [13] T. Sun, Y. Zhuang, W. Li, A. Philipossian, Microelectron. Eng. 100 (2012) 20–24.