Superconducting electronics testing

An I/0 assembly has been designed and constructed to support the operation of superconducting circuitry. The system, previously described 9 for chip testing, has been adapted for use with a Josephson technology system level experiment. The cryoinsert assembly, constructed of non-magnetic parts, provides 80 high frequency I/0 lines between room temperature and 4.2 K.

Superconducting electronics testing P.A. Moskowitz, R.W. Guernsey, J.W. Stasiak, and E.B. Flint Key words: superconductor,electronics, chip, testing assembly Test environment High speed Josephson switching circuits operate in a 4.2 K liquid helium environment. 1'2 This and other unique conditions under which Josephson circuits operate place severe restrictions on the type of contact system for chip testing. The length of each individual contact must be minimized, so as to provide a low inductance to be consistent with the fast switching times. Also, the entire sample holder and cryoinsert assembly must be made of non-magnetic materials, in order to maintain a low ambient magnetic field for the proper operation of circuitry. The 6.35 mm silicon chips to be tested have a double peripheral row of 228 solder pads. Each pad is approximately 100/ira in diameter and the pads are placed on 200 #m centres. Differential contraction experienced upon cooling the contact array to 4.2 K is a serious problem. A 6 mm silicon chip will shrink only 1 #m when cooled to 4.2 K. However, for some materials the contraction across the width of the contact array is of the order of the contact pad size. Thus, materials having small coefficients of contraction must be used.

During removal of the system from the dewar, the vacuum jacket is maintained at a low pressure of helium gas. This keeps the inner and outer walls at the same temperature and avoids the possibility of stresses in the structure caused by differential contraction. A thin teflon collar the inner diameter of which is slightly less than the outer diameter of the vacuum housing is mounted on the top of the dewar. This collar prevents gases from entering the dewar and condensing in the neck, while still permitting free movement of the cryoinsert.

Contact array The chip connector array must make a reliable and nondestructive contact at room temperature, and maintain that contact through multiple cycles to 4.2 K. Thus, careful attention must be paid to differential contraction. The Josephson technology chips to be tested have a double peripheral row of 228 solder pads. Each pad is approximately 100/~m in diameter and the pads are placed on 200 #m

Flange and housing The brass flange shown in Fig. 1 mates with the top flange of a liquid helium dewar and in turn holds the pyrex centre support tube and the pyrex housing. Pumping ports, a pyrex push-rod, the cable feed-through, and bulkhead support for the coaxial cable connectors are mounted on the flange. The housing core and vacuum jacket are kept at a low pressure during insertion so that the chip stays above its critical superconducting temperature (Tc) until it is placed within the low field region of the dewar. In order to cool the chip, additional helium gas is let into the core and vacuum jacket. Then liquid is admitted into the core by using a push rod to break a thin polyimide seal at the bottom. ~

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It is sometimes necessary to warm the system under test above Tc in order to eliminate magnetic flux trapped in the superconducting structures. This is accomplished by evacuating the housing jacket, slightly pressurizing the core so as to drive the liquid out, and then energizing heaters as necessary. Once the temperature of the system has exceeded Tc, the heaters are turned off and the liquid is readmitted. The authors are at the IBM Thomas J. Watson Research Center Yorktown Heights, New York 10598, RWG and JWS are currently at IBM Carp, East Fishkill, NY 12533, USA. Paper received 20 August 1982.

0011-2275/83/002107-03 C R Y O G E N I C S . F E B R U A R Y 1983

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at 300 K. A signal that is introduced with a 200 ps risetime at one end of the 1.4 m cable arrives with a 400 ps risetime at the other end, and is attenuated about 15% in amplitude. Under these conditions, the worst-case forward crosstalk is 3.5%. These results are in substantial agreement with theoretical expectations. 8 The propagation velocity is 0.6 c. Heat loss, ameliorated by vapour cooling, is of the order of 1.7 mW per lead. Cables have been cycled over thirty times between room temperature and 4.2 K without apparent degradation of their characteristics. Discussion

0.46

Since our first report on the cryoinsert design, five complete systems have been constructed. 9 Two of these systems have been used for a Josephson technology system level experiment.l° For this experiment, the 80 line I/O cable was connected to an adapter in the same way that connections were made to the chip-test adapter described above. Superconducting lines on the adapter connected the I/Os to arrays of platinum pins which were used to interconnect the package parts. The complete package for this experiment, known as the Cross Sectional Model (CSM) is described in detail elsewhere) 1 The CSM data path operated with a minimum cycle time of 3.7 ns.

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All five of the cryoinserts are now in use for chip testing. Two are used with 116 contact array chips which differ from the 228 contact array chips by the absence of the inner row of pads. Work is in progress to replace the 80 SMA connectors used at the room temperature and of the cryoinsert with a single stripline to printed circuit

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Table 1.

Electrical characteristics of I/0 system

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Materials

Polyimide and copper

centres. An array of Cobra springs, developed by IBM/East Fishkill, contacts these pads. 4's'6 The cobras are formed from 1.6 mm lengths of 63.5/~m diameter Neyoro-G, a wire manufactured by the J.M. Ney Company. This wire is an alloy of gold, copper, platinum, silver, and zinc. It is nonmagnetic, does not oxidize, and maintains it resilience at 4.2 K. The Cobras are held in polyimide dies in such a way as to allow free movement at both ends. While one end of each Cobra presses into a pad on the chip, the other end makes contact with a similar pad on a 25 mm silicon wafer, the adapter, that has thin film wiring from the contact pads to the I/O cable connection.

Length

1.4 meter (55 in)

I / 0 cable The flexible polyimide I/O cable consists of eighty 36/~m (.0014 in) thick copper lines over a continuous ground plane. Each line is .18 mm (.007 in) wide, spaced on a 51 mm (.020 in) pitch with a fan-in to .36 mm .014 in at the adapter end. The room temperature end of the cable is terminated by eighty SMA coaxial connectors, while at the low temperature end there is a spring-loaded connection to the adapter. 7 Initial plans to solder the adapter connection were abandoned because of difficulty in achieving a joint that would withstand the differential contraction on multiple cycles to 4.2 K. The nominal cable impedance of 50 ~2 has been met to within 5%, by the manufacturer, the Rogers Corporation. When in use, one end of the cable is at 4.2 K and the other

108

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Impedance

50

Propagation

0.6 c

Heat loss

1.7 mW/line

For 200 ps risetime signal (RT to 4.2 K), 3.5% back crosstalk (worst case) 7.0% forward crosstalk (worst case) 15% attenuation 400 ps arrival risetime

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CRYOGENICS . FEBRUARY 1983

board connector. This c o n n e c t o r is to be a scaled-up version o f the one used to make the cable to adapter connection. This change is expected to greatly improve the ease with which the systenr is used for the testing o f large numbers o f chips where quick turn around time is required.

References 1 2 3 4

1osephson computer technology, IBM J Res Develop 24 11980) 105-264 Matisoo, J. The superconducting computer, Scientific American, 242 t 1980) 50-60 Stasiak, J.W., Guernsey, R.W. Slip-on vacuum connection for !o\~ temperature use, IBM Technical Disclosure Bulletht, 23 ~1980) 3384 Byrnes, II.P., Wahl, R. ('ontact for an electrical contactor assembly, I S I'atent No 4 027 935 hme 7 119771

C R Y O G E N I C S . FEBRUARY 1983

5 6

7 8 9

10 11

Byrnes, H.P., Moskowitz, P.A., Wahl, Ro Cryogenic testing of .losephson chips, IBM Technical Disclosure Bulletin, 23 11981) 4363-4364 Moskowitz, P.A.F.lectrical performance of high density probe array for testing .losephson circuit chips, IELT Transactions on Magnetics, Nag-17 11981) 761-763

Bickford, H.R., Guernsey, R.W., Jenkins, L.C., Moskowitz, P.A., Sokolowski, J. Flexible I/O cable to thin film connector, IBM Technical Disclosure Bulletin, 25 (1982) 1701-1702 Anderson, C J . Electrical properties of an I/O cable for Josephson applications, Rev Sci Instru (to be pubfished) Moskowitz, P.A., Guernsey, R.W., Stasiak, J.W. tligh frequency multi-s'tripline cryoinsert for superconducting electronics, Advances in Cryogenic Engineering, 27 Plenum Press, New York, (1982) 201-206 Ketchen, M.B. et al., A Josephson technology system level experiment,/EEL" Elec Dev Lett, EDL-2, ((1981) 262-265 Lahiri, S.K., et al., Packaging technology fi)r Joscphson integrated circuits, lEEk." Trans Components llybrids. ManuJ Tcchnol CIIMT-5, (1982) 271-280

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