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Surface Ge-rich p-type SiGe channel tunnel field-effect transistor fabricated by local condensation technique
Solid State Electronics 164 (2020) 107701
Contents lists available at ScienceDirect
Solid State Electronics journal homepage: www.elsevier.com/locate/sse
Surface Ge-rich p-type SiGe channel tunnel field-effect transistor fabricated by local condensation technique
T
Junil Leea, Ryoongbin Leea, Sihyun Kima, Kitae Leea, Hyun-Min Kima, Soyoun Kima, ⁎ Munhyeon Kima, Sangwan Kimb, Jong-Ho Leea, Byung-Gook Parka, a Inter-University Semiconductor Research Center (ISRC) and Department of Electrical and Computer Engineering (ECE), Seoul National University, 08826 Seoul, Republic of Korea b Department of Electrical and Computer Engineering, Ajou University, Suwon 16499, Republic of Korea
A B S T R A C T
In this study, tunnel field-effect transistor (TFET) which has surface Ge-rich SiGe nanowire as a channel has been demonstrated. There are improvements in terms of on-current and subthreshold swing (SS) comparing with control groups (constant Ge concentration SiGe TFET and Si TFET) fabricated by the same process flow except for the channel formation step. In order to obtain the concentration-graded SiGe channel, Ge condensation method which is a kind of oxidation is adopted. The rectangular shape of the channel becomes a rounded nanowire through the Ge condensation process. The TFET with the concentration-graded SiGe channel can improve drive current due to a smaller band gap at the Ge-condensed surface of the channel compared to Si or non-condensed SiGe channel TFET.
1. Introduction Tunnel field effect transistors (TFETs) have been regarded as promising energy efficient switching devices because they can achieve subthreshold swing (SS) below 60 mV/decade, which is the limit of conventional metal-oxidesemiconductor FETs (MOSFETs) at the room temperature. [1]. Carrier injection mechanism in TFETs relies on bandto-band tunneling (BTBT) less affected by temperature. At small gate voltages (VGS), the Fermi-tail part is cut from participating in the current drive, resulting in a small off current and SS [2,3]. It has been reported that tunneling rate of carriers from source to channel is inversely proportional to the band gap of channel materials [4]. Therefore, materials having a small band gap are preferred to increase the current of TFET. In recent years, extensive research has been conducted to improve on-current. Various materials have been studied to reduce the width and height of tunnel barriers [5–7]. That is, using Ge or SiGe rather than Si may be a good alternative to reduce the tunneling barrier. In addition, SiGe is complementary MOS (CMOS) compatible because it is a group IV material [8]. Also, Ge or SiGe have high hole mobility and might be promising for pTFETs [9–14]. Although high Ge content is preferred for improving the on-current, there is a trade-off especially in terms of process capability due to the crystal lattice mismatch with the Si substrate which increases the defect concentration on the channel surface. Fig. 1 shows dislocation lines starting from interface between Si substrate and SiGe channel. These lines act as trap sites on the surface and degrade the mobility of carriers when current flows through the
⁎
Corresponding author. E-mail address: [email protected] (B.-G. Park).
https://doi.org/10.1016/j.sse.2019.107701
Available online 07 November 2019 0038-1101/ © 2019 Published by Elsevier Ltd.
SiGe channel. This paper aims to solve the abovementioned problems. we fabricate p-channel SiGe nanowire with graded Ge concentration. The proposed SiGe channel has high Ge concentration (about 45%) at the channel surface to boost on-current, while Ge content is low (about 20%) at the interface between SiGe and Si substrate to reduce the lattice mismatch. In order to verify the feasibility, technology computer-aided design (TCAD) simulation are preceded. As the control groups, SiGe channel TFET with constant Ge content of 20% and Si channel TFET are fabricated. By changing channel Ge concentration, improvements of electrical characteristics are observed. In addition, in order to improve gate controllability in the SS region, post metallization annealing (PMA) with high pressure condition is performed to reduce the interface trap density. 2. Device structure Fig. 2(a) and (b) depict a schematic of the fabricated device and process flow, respectively. In this study, three different structures are fabricated. The step that makes the difference between the experimental group and the control group is the active formation step. After active Si fin etch, Si TFET without SiGe epitaxial growth step are made into a control group. After SiGe epitaxial growth, the group in which the Ge condensation step is omitted is made into the other control group (Si0.8Ge0.2 TFET). Fig. 2(c) and (d) depict the high-resolution transmission electron microscope (HRTEM) images of the fabricated
Solid State Electronics 164 (2020) 107701
J. Lee, et al.
perform better than transistors made with a planar structure [15]. Also, the Ge content on the surface of the SiGe channel is raised by the subsequent treatment (called Ge condensation technique) immediately after the epitaxial growth of SiGe. Since the material having a small band gap is used on the surface where the BTBT mainly occurred, the driving current of can be improved. In order to confirm the electrical performance of the surface Ge-rich TFET and the controls (constant Ge content Si0.8Ge0.2 TFET and Si TFET), the TCAD simulation is performed using Synopsys Sentaurus. Fig. 3(a)–(c) show the two-dimensional (2D) cross-sectional structures of the simulated TFETs. The physical parameters of the TFETs used for the simulations are shown in Fig. 3(d). Cylindrical model is applied to simulate the structure in which the gate surrounds the channel. Fig. 3(e) and its inset show the energy band diagrams and Fig. 3(f) depicts BTBT generation rates when the device is turned on [VGS = −1 V, drain voltage (VDS) = −1 V], respectively. The tunnel barrier width (WT) seen by the carrier on the source side of the experimental group is reduced compared to the control groups. This is because the band gap of the material becomes smaller as the content of Ge increases. As WT decreases, the probability that the carrier go through from the source to the channel exponentially increases [16], so that the drive current can be expected to increase. Actually, the amount of electrons generated in the same structure on the simulation is 4.27 × 1030 cm−3/s, which is larger than 6.71 × 1029 cm−3/s and 1.63 × 1029 cm−3/s of the control groups.
Fig. 1. Threading dislocation lines found at the channel surface of SiGe due to different lattice constants with Si.
devices. Fig. 2(c) is obtained by cutting the plane parallel to the channel, while Fig. 2(d) is obtained by cutting the channel perpendicularly. As shown in Fig. 2(c), HfO2 is used as a gate dielectric and thin Al2O3 is deposited before HfO2 step as an interlayer dielectric for better interface quality with SiGe. Fig. 2(d) shows the channel of this device. The omega-shaped channel allows the gate potential to be better transmitted to the channel. It can be able to fabricate transistors that
Fig. 2. (a) Process sequences and (b) schematic diagrams to fabricate SiGe and Si channel TFETs. HR cross-sectional TEM images (c) in parallel to channel and (d) in perpendicular to channel directions. 2
Solid State Electronics 164 (2020) 107701
J. Lee, et al.
Fig. 3. Simulated TFET structures. (a) surface Gerich SiGe TFET, (b) constant Ge concentration SiGe TFET, and (c) Si TFET. (The structure is drawn in 2D, and then rotated around the bottom of the Si substrate to form a nanowire structure.) (d) The physical parameters of the TFETs used for the simulations (e) energy band diagrams at turn on state (VGS and VD = −1 V), (f) Comparison of electron band to band generation rate.
Fig. 4. Process sequences for active formation.
Fig. 5. Capacitance-Voltage (C-V) curves (a) before PMA, (b) after PMA (red line is real capacitance value extracted from 2 frequency method). (c) comparison of hysteresis C-V curves. (d) Interfacial trap state density as a function of trap energy. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
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Solid State Electronics 164 (2020) 107701
J. Lee, et al.
post metallization annealing (PMA) is performed in a gas ambient containing 5% of H2 and 95% of N2 with high pressure at 450 °C for 30 min. 4. Result and discussion The cross-section of the channel after two step oxidations (rounding oxidation & Ge condensation) is shown in Fig. 2(d). By energy-dispersive x-ray spectroscopy (EDS), of Fig. 5 shows that the initial Ge content is about 20% and the Ge content of the channel surface reaches to ~45% after Ge condensation. The core part (bright part in the figure) is pure Si, but it can be seen that the portion surrounding the core (dark part of the figure) is SiGe and the Ge content increases to ~45% with increasing distance from the core. The oxide layer formed by the second oxidation process can be used as a buffer layer in subsequent processes without stripping, and the remaining processes can be performed using the gate-last process as depicted in Fig. 2(a). The effects of PMA on the quality of the high-κ/metal gate stacks are examined by capacitance measurements as a function of VGS in MOS capacitors by using HP4284A precision LCR meter. The capacitance–voltage (C–V) characteristics shown in Fig. 5(a) & (b). Capacitance is measured in parallel mode with changing frequency, and real capacitance value (red dot) is extracted by using 2 frequency method [17,18]. The capacitance equivalent thickness (CET) before and after PMA is 1.70 nm and 1.72 nm, respectively. This leads to a slight difference in the potential of the gate applied to the channel, while PMA has a greater benefit in terms of hysteresis and Dit. As shown in Fig. 5(c), the hysteresis decreases by 160 mV. And, Dit extracted by conductance method [19,20] is reduced by about 20%. Fig. 6 shows the comparison of the transfer characteristics of the fabricated TFETs for −1.0 V drain voltages (VDS). In the case of the experimental group, minimum subthreshold swing (SSmin) of 43 mV/ dec is obtained and the on–off ratio is 106, whereas those of control SiGe TFET are 97 mV/dec and 4.5 × 104. The differences are attributed to the narrower Wt as indicated in Fig. 2(b). Fig. 7 shows the SS of the surface Ge-rich TFET as a function of drain current (ID). The SS is maintained less than 60 mV/dec from OFF-state to more than three orders.
Fig. 6. Transfer characteristics of fabricated devices.
Fig. 7. SS vs. drain current curve for surface Ge-rich SiGe TFET.
3. Experiment The actual experiments are performed in the order shown in Fig. 2(a), and unit tests are conducted for some important steps such as active formation step and Ge condensation step. Devices are fabricated on the full 6 in sized Si-on-insulator (SOI) substrate. Si dioxide (SiO2) used as buried oxide layer has 375 nm thickness while silicon as a substrate is 60 nm thickness. The process of forming the active channel at the front-end-of-line (FEOL) is very important, and a related figure is shown in Fig. 4. A two-step oxidation method (Fig. 4) is used to make a nanowire with graded Ge concentration. After the active region with the narrow fin is formed by electron beam lithography [Fig. 4(a)], a first oxidation is performed to round the channel [Fig. 4(b)]. The edges of a rectangular channel are rounded because the oxidation speed of the edges is faster than a flat surface. Si atoms in the corner are more prone to encounter oxygen molecules, so the oxidation speed is faster at the corner. The temperature and time of the first oxidation process should be appropriately selected. Otherwise, the rounded shape may not be formed or the Si may be exhausted during the oxidation. After the first oxidation, the oxide layer which is formed by the first oxidation process is removed [Fig. 4(c)]. Then, the epitaxial growth of 20-nm thick SiGe layer with 20% Ge concentration is carried out [Fig. 4(d)]. Second oxidation process, called Ge condensation, is conducted [Fig. 4(e)]. Here, the temperature at which the oxidation rate of Si is higher than that of Ge should be selected. When the Si atoms in the SiGe are selectively oxidized, in reduced volume, the amount of Ge atom is preserved, leaving SiGe with increased Ge content. This Ge condensation is experimentally proved by 30 min. oxidation under an oxygen atmosphere at 950 °C. After the channel formation is completed, the next step follows the gate-last process shown in Fig. 2(a). In the process of forming high-κ metal gate stack (HKMG), HfO2 is used as a main dielectric material, and Al2O3 is inserted as an interlayer (IL) to improve interfacial state with SiGe. Additionally, in order to improve the quality of the electric [i.e., in order to lower the interface trap density (Dit)],
5. Conclusions In this study, the TFET with Ge-condensed SiGe nanowire channel is demonstrated. The problem of directly growing SiGe with a high concentration of Ge on a Si substrate is solved by using a technique called Ge condensation with SiGe initially having low concentration of Ge (~20%). We have confirmed that the ION and SS are improved as expected from the TCAD simulation. The omega shaped nanowires are formed by the two step oxidation processes; The first oxidation is the edge-rounding oxidation of rectangular-shape Si channel and the second oxidation is the Ge condensation oxidation. Moreover, PMA is conducted for better quality of gate dielectric. Consequently, the surface Ge-rich SiGe TFET shows remarkable performances in terms of SS and ION/IOFF (minimum 47 mV/dec and 106 ION/IOFF). Declaration of Competing Interest The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper. Acknowledgments This work was supported in part by the Brain Korea 21 Project in 2019, in part by the Future Semiconductor Device Technology Development Program (10067739 & 10080575) funded by Ministry of Trade, Industry and Energy (MOTIE) and Korea Semiconductor 4
Solid State Electronics 164 (2020) 107701
J. Lee, et al.
Research Consortium (KSRC), and in part by Synopsys Inc.
determined by the metal-insulator-silicon conductance technique. Bell Syst Tech J 1967;46(6):1055–133. [20] Atkin JM, Cartier E, Shaw TM, Laibowitz RB, Heinz TF. Charge trapping at the lowk dielectric-silicon interface probed by the conductance and capacitance techniques. Appl Phys Lett 2008;93(12):122902.
References [1] Choi WY, et al. Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett 2007;28:743–5. [2] Wang P-Y, Tsui B-Y. Band engineering to improve average subthreshold swing by suppressing low electric field band-to-band tunneling with epitaxial tunnel layer tunnel FET structure. IEEE Trans Nanotechnol 2016;15(1):74–9. [3] Kim SW, Choi WY, Kim H, Sun M-C, Kim HW, Park B-G. Investigation on hump effects of L-shaped tunneling filed-effect transistors Honolulu, HI, USA Proc. IEEE Silicon Nanoelectron.Workshop (SNW)2012. p. 1–2. [4] Patel N, Ramesha A. Drive current boosting of n-type tunnel FET with strained SiGe layer at source. Microelectron J 2008;39:1671–7. [5] Lee M, et al. Driving current enhancement of strained Ge (110) p-type tunnel FETs and anisotropic effect. IEEE Electron Device Lett 2011;32:1355–7. [6] Moselund K, et al. InAs-Si nanowire heterojunction tunnel FETs. IEEE Electron Device Lett 2012;33:1453–5. [7] Zhou G, et al. InGaAs/InP tunnel FETs with a subthreshold swing of 93 mV/dec and ION/IOFF ratio near 106. IEEE Electron Device Lett 2012;33:782–4. [8] Wang W, et al. Design of U-shape channel tunnel FETs with SiGe source regions. IEEE Trans Electron Devices 2014;61:193–7. [9] Yang Y, et al. Towards direct band-to-band tunneling in P-channel tunneling field effect transistor (TFET): technology enablement by germanium-tin (GeSn). IEEE Int Electron Devices Meeting. 2012. San Francisco, CA. [10] Mallik A, et al. The impact of fringing field on the device performance of a pchannel tunnel field-effect transistor with a high-κ gate dielectric. IEEE Trans Electron Devices 2012;59(2):277–82. [11] Yang Y, et al. Germanium–tin P-channel tunneling field-effect transistor: device design and technology demonstration. IEEE Trans Electron Devices 2013;60(12):4048–56. [12] Wang P-Y, et al. Experimental demonstration of p-channel germanium epitaxial tunnel layer (ETL) tunnel FET with high tunneling current and high ON/OFF Ratio. IEEE Electron Device Lett 2015;36(12):1264–6. [13] Pandey R, et al. Performance benchmarking of p-type In0.65Ga0.35As/GaAs0.4Sb0.6 and Ge/Ge 0.93 Sn 0.07 hetero-junction tunnel FETs San Francisco, CA IEEE Int. Electron Devices Meeting. 2016. [14] Kumar A, Souza M. A p-channel GaN heterostructure tunnel FET with high ON/OFF current ratio. IEEE Trans Electron Devices 2019;66(7):2916–22. [15] Bohr MT, Young IA. CMOS scaling trends and beyond. IEEE Micro 2017;37(6):20–9. [16] Ionescu AM, Riel H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature 2011;479(7373):329–37. [17] Yang K, Hu C. MOS capacitance measurements for high-leakage thin dielectrics. IEEE Trans Electron Devices 1999;46(7):1500–1. [18] Nara A, et al. Applicability limits of the two-frequency capacitance measurement technique for the thickness extraction of ultrathin gate oxide. IEEE Trans Semicondutor Manuf 2002;15(2):209–13. [19] Nicollian EH, Goetzberger A. The Si-SiO2 interface—electrical properties as
Junil Lee was born in Changwon, Korea, in 1987. He received the B.S degree in Electrical Engineering from Seoul National University in 2013. He is currently working toward Ph.D degree in electrical engineering. His research interests include nanoscale devices, tunnel field-effect transistor (TFET). Mr. Lee is a Student Member of the Institute of Electrical and Electronics Engineers (IEEE) and the Institute of Electronics Engineers of Korea (IEEK).
Byung-Gook Park received his B.S. and M.S. degrees in electronics engineering from Seoul National University (SNU) in 1982 and 1984, respectively, and his Ph. D. degree in electrical engineering from Stanford University in 1990. From 1990 to 1993, he worked at the AT&T Bell Laboratories, where he contributed to the development of 0.1 micron CMOS and its characterization. From 1993 to 1994, he was with Texas Instruments, developing 0.25 micron CMOS. In 1994, he joined SNU as an assistant professor in the School of Electrical Engineering (SoEE), where he is currently a professor. In 2002, he worked at Stanford University as a visiting professor, on his sabbatical leave from SNU. He led the Inter-university Semiconductor Research Center (ISRC) at SNU as the director from 2008 to 2010. His current research interests include the design and fabrication of nanoscale CMOS, flash memories, silicon quantum devices and organic thin film transistors. He has authored and co-authored over 1000 research papers in journals and conferences. Prof. Park has served as a committee member on several international conferences including Microprocesses and Nanotechnology, IEEE International Electron Devices. Meeting, International Conference on Solid State Devices and Materials, and IEEE SiliconNanoelectronics Workshop and served as an Editor of IEEE Electron Device Letters. He received “Best Teacher” Award from SoEE in 1997, Doyeon Award for Creative Research from ISRC in 2003, Haedong Parper Award from the Institude of Electronic Engineers of Korea (IEEK) in 2015, Educational Award from College of Engineering, SNU, in 2006, Haedong Research Award from IEEK in 2008, Nano Research Innovation Award from the Ministry of Science, ICT and Future Planning of Korea in 2013, and Academic Training Award from Seoul National University in 2015.
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Contents lists available at ScienceDirect
Solid State Electronics journal homepage: www.elsevier.com/locate/sse
Surface Ge-rich p-type SiGe channel tunnel field-effect transistor fabricated by local condensation technique
T
Junil Leea, Ryoongbin Leea, Sihyun Kima, Kitae Leea, Hyun-Min Kima, Soyoun Kima, ⁎ Munhyeon Kima, Sangwan Kimb, Jong-Ho Leea, Byung-Gook Parka, a Inter-University Semiconductor Research Center (ISRC) and Department of Electrical and Computer Engineering (ECE), Seoul National University, 08826 Seoul, Republic of Korea b Department of Electrical and Computer Engineering, Ajou University, Suwon 16499, Republic of Korea
A B S T R A C T
In this study, tunnel field-effect transistor (TFET) which has surface Ge-rich SiGe nanowire as a channel has been demonstrated. There are improvements in terms of on-current and subthreshold swing (SS) comparing with control groups (constant Ge concentration SiGe TFET and Si TFET) fabricated by the same process flow except for the channel formation step. In order to obtain the concentration-graded SiGe channel, Ge condensation method which is a kind of oxidation is adopted. The rectangular shape of the channel becomes a rounded nanowire through the Ge condensation process. The TFET with the concentration-graded SiGe channel can improve drive current due to a smaller band gap at the Ge-condensed surface of the channel compared to Si or non-condensed SiGe channel TFET.
1. Introduction Tunnel field effect transistors (TFETs) have been regarded as promising energy efficient switching devices because they can achieve subthreshold swing (SS) below 60 mV/decade, which is the limit of conventional metal-oxidesemiconductor FETs (MOSFETs) at the room temperature. [1]. Carrier injection mechanism in TFETs relies on bandto-band tunneling (BTBT) less affected by temperature. At small gate voltages (VGS), the Fermi-tail part is cut from participating in the current drive, resulting in a small off current and SS [2,3]. It has been reported that tunneling rate of carriers from source to channel is inversely proportional to the band gap of channel materials [4]. Therefore, materials having a small band gap are preferred to increase the current of TFET. In recent years, extensive research has been conducted to improve on-current. Various materials have been studied to reduce the width and height of tunnel barriers [5–7]. That is, using Ge or SiGe rather than Si may be a good alternative to reduce the tunneling barrier. In addition, SiGe is complementary MOS (CMOS) compatible because it is a group IV material [8]. Also, Ge or SiGe have high hole mobility and might be promising for pTFETs [9–14]. Although high Ge content is preferred for improving the on-current, there is a trade-off especially in terms of process capability due to the crystal lattice mismatch with the Si substrate which increases the defect concentration on the channel surface. Fig. 1 shows dislocation lines starting from interface between Si substrate and SiGe channel. These lines act as trap sites on the surface and degrade the mobility of carriers when current flows through the
⁎
Corresponding author. E-mail address: [email protected] (B.-G. Park).
https://doi.org/10.1016/j.sse.2019.107701
Available online 07 November 2019 0038-1101/ © 2019 Published by Elsevier Ltd.
SiGe channel. This paper aims to solve the abovementioned problems. we fabricate p-channel SiGe nanowire with graded Ge concentration. The proposed SiGe channel has high Ge concentration (about 45%) at the channel surface to boost on-current, while Ge content is low (about 20%) at the interface between SiGe and Si substrate to reduce the lattice mismatch. In order to verify the feasibility, technology computer-aided design (TCAD) simulation are preceded. As the control groups, SiGe channel TFET with constant Ge content of 20% and Si channel TFET are fabricated. By changing channel Ge concentration, improvements of electrical characteristics are observed. In addition, in order to improve gate controllability in the SS region, post metallization annealing (PMA) with high pressure condition is performed to reduce the interface trap density. 2. Device structure Fig. 2(a) and (b) depict a schematic of the fabricated device and process flow, respectively. In this study, three different structures are fabricated. The step that makes the difference between the experimental group and the control group is the active formation step. After active Si fin etch, Si TFET without SiGe epitaxial growth step are made into a control group. After SiGe epitaxial growth, the group in which the Ge condensation step is omitted is made into the other control group (Si0.8Ge0.2 TFET). Fig. 2(c) and (d) depict the high-resolution transmission electron microscope (HRTEM) images of the fabricated
Solid State Electronics 164 (2020) 107701
J. Lee, et al.
perform better than transistors made with a planar structure [15]. Also, the Ge content on the surface of the SiGe channel is raised by the subsequent treatment (called Ge condensation technique) immediately after the epitaxial growth of SiGe. Since the material having a small band gap is used on the surface where the BTBT mainly occurred, the driving current of can be improved. In order to confirm the electrical performance of the surface Ge-rich TFET and the controls (constant Ge content Si0.8Ge0.2 TFET and Si TFET), the TCAD simulation is performed using Synopsys Sentaurus. Fig. 3(a)–(c) show the two-dimensional (2D) cross-sectional structures of the simulated TFETs. The physical parameters of the TFETs used for the simulations are shown in Fig. 3(d). Cylindrical model is applied to simulate the structure in which the gate surrounds the channel. Fig. 3(e) and its inset show the energy band diagrams and Fig. 3(f) depicts BTBT generation rates when the device is turned on [VGS = −1 V, drain voltage (VDS) = −1 V], respectively. The tunnel barrier width (WT) seen by the carrier on the source side of the experimental group is reduced compared to the control groups. This is because the band gap of the material becomes smaller as the content of Ge increases. As WT decreases, the probability that the carrier go through from the source to the channel exponentially increases [16], so that the drive current can be expected to increase. Actually, the amount of electrons generated in the same structure on the simulation is 4.27 × 1030 cm−3/s, which is larger than 6.71 × 1029 cm−3/s and 1.63 × 1029 cm−3/s of the control groups.
Fig. 1. Threading dislocation lines found at the channel surface of SiGe due to different lattice constants with Si.
devices. Fig. 2(c) is obtained by cutting the plane parallel to the channel, while Fig. 2(d) is obtained by cutting the channel perpendicularly. As shown in Fig. 2(c), HfO2 is used as a gate dielectric and thin Al2O3 is deposited before HfO2 step as an interlayer dielectric for better interface quality with SiGe. Fig. 2(d) shows the channel of this device. The omega-shaped channel allows the gate potential to be better transmitted to the channel. It can be able to fabricate transistors that
Fig. 2. (a) Process sequences and (b) schematic diagrams to fabricate SiGe and Si channel TFETs. HR cross-sectional TEM images (c) in parallel to channel and (d) in perpendicular to channel directions. 2
Solid State Electronics 164 (2020) 107701
J. Lee, et al.
Fig. 3. Simulated TFET structures. (a) surface Gerich SiGe TFET, (b) constant Ge concentration SiGe TFET, and (c) Si TFET. (The structure is drawn in 2D, and then rotated around the bottom of the Si substrate to form a nanowire structure.) (d) The physical parameters of the TFETs used for the simulations (e) energy band diagrams at turn on state (VGS and VD = −1 V), (f) Comparison of electron band to band generation rate.
Fig. 4. Process sequences for active formation.
Fig. 5. Capacitance-Voltage (C-V) curves (a) before PMA, (b) after PMA (red line is real capacitance value extracted from 2 frequency method). (c) comparison of hysteresis C-V curves. (d) Interfacial trap state density as a function of trap energy. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
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Solid State Electronics 164 (2020) 107701
J. Lee, et al.
post metallization annealing (PMA) is performed in a gas ambient containing 5% of H2 and 95% of N2 with high pressure at 450 °C for 30 min. 4. Result and discussion The cross-section of the channel after two step oxidations (rounding oxidation & Ge condensation) is shown in Fig. 2(d). By energy-dispersive x-ray spectroscopy (EDS), of Fig. 5 shows that the initial Ge content is about 20% and the Ge content of the channel surface reaches to ~45% after Ge condensation. The core part (bright part in the figure) is pure Si, but it can be seen that the portion surrounding the core (dark part of the figure) is SiGe and the Ge content increases to ~45% with increasing distance from the core. The oxide layer formed by the second oxidation process can be used as a buffer layer in subsequent processes without stripping, and the remaining processes can be performed using the gate-last process as depicted in Fig. 2(a). The effects of PMA on the quality of the high-κ/metal gate stacks are examined by capacitance measurements as a function of VGS in MOS capacitors by using HP4284A precision LCR meter. The capacitance–voltage (C–V) characteristics shown in Fig. 5(a) & (b). Capacitance is measured in parallel mode with changing frequency, and real capacitance value (red dot) is extracted by using 2 frequency method [17,18]. The capacitance equivalent thickness (CET) before and after PMA is 1.70 nm and 1.72 nm, respectively. This leads to a slight difference in the potential of the gate applied to the channel, while PMA has a greater benefit in terms of hysteresis and Dit. As shown in Fig. 5(c), the hysteresis decreases by 160 mV. And, Dit extracted by conductance method [19,20] is reduced by about 20%. Fig. 6 shows the comparison of the transfer characteristics of the fabricated TFETs for −1.0 V drain voltages (VDS). In the case of the experimental group, minimum subthreshold swing (SSmin) of 43 mV/ dec is obtained and the on–off ratio is 106, whereas those of control SiGe TFET are 97 mV/dec and 4.5 × 104. The differences are attributed to the narrower Wt as indicated in Fig. 2(b). Fig. 7 shows the SS of the surface Ge-rich TFET as a function of drain current (ID). The SS is maintained less than 60 mV/dec from OFF-state to more than three orders.
Fig. 6. Transfer characteristics of fabricated devices.
Fig. 7. SS vs. drain current curve for surface Ge-rich SiGe TFET.
3. Experiment The actual experiments are performed in the order shown in Fig. 2(a), and unit tests are conducted for some important steps such as active formation step and Ge condensation step. Devices are fabricated on the full 6 in sized Si-on-insulator (SOI) substrate. Si dioxide (SiO2) used as buried oxide layer has 375 nm thickness while silicon as a substrate is 60 nm thickness. The process of forming the active channel at the front-end-of-line (FEOL) is very important, and a related figure is shown in Fig. 4. A two-step oxidation method (Fig. 4) is used to make a nanowire with graded Ge concentration. After the active region with the narrow fin is formed by electron beam lithography [Fig. 4(a)], a first oxidation is performed to round the channel [Fig. 4(b)]. The edges of a rectangular channel are rounded because the oxidation speed of the edges is faster than a flat surface. Si atoms in the corner are more prone to encounter oxygen molecules, so the oxidation speed is faster at the corner. The temperature and time of the first oxidation process should be appropriately selected. Otherwise, the rounded shape may not be formed or the Si may be exhausted during the oxidation. After the first oxidation, the oxide layer which is formed by the first oxidation process is removed [Fig. 4(c)]. Then, the epitaxial growth of 20-nm thick SiGe layer with 20% Ge concentration is carried out [Fig. 4(d)]. Second oxidation process, called Ge condensation, is conducted [Fig. 4(e)]. Here, the temperature at which the oxidation rate of Si is higher than that of Ge should be selected. When the Si atoms in the SiGe are selectively oxidized, in reduced volume, the amount of Ge atom is preserved, leaving SiGe with increased Ge content. This Ge condensation is experimentally proved by 30 min. oxidation under an oxygen atmosphere at 950 °C. After the channel formation is completed, the next step follows the gate-last process shown in Fig. 2(a). In the process of forming high-κ metal gate stack (HKMG), HfO2 is used as a main dielectric material, and Al2O3 is inserted as an interlayer (IL) to improve interfacial state with SiGe. Additionally, in order to improve the quality of the electric [i.e., in order to lower the interface trap density (Dit)],
5. Conclusions In this study, the TFET with Ge-condensed SiGe nanowire channel is demonstrated. The problem of directly growing SiGe with a high concentration of Ge on a Si substrate is solved by using a technique called Ge condensation with SiGe initially having low concentration of Ge (~20%). We have confirmed that the ION and SS are improved as expected from the TCAD simulation. The omega shaped nanowires are formed by the two step oxidation processes; The first oxidation is the edge-rounding oxidation of rectangular-shape Si channel and the second oxidation is the Ge condensation oxidation. Moreover, PMA is conducted for better quality of gate dielectric. Consequently, the surface Ge-rich SiGe TFET shows remarkable performances in terms of SS and ION/IOFF (minimum 47 mV/dec and 106 ION/IOFF). Declaration of Competing Interest The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper. Acknowledgments This work was supported in part by the Brain Korea 21 Project in 2019, in part by the Future Semiconductor Device Technology Development Program (10067739 & 10080575) funded by Ministry of Trade, Industry and Energy (MOTIE) and Korea Semiconductor 4
Solid State Electronics 164 (2020) 107701
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Research Consortium (KSRC), and in part by Synopsys Inc.
determined by the metal-insulator-silicon conductance technique. Bell Syst Tech J 1967;46(6):1055–133. [20] Atkin JM, Cartier E, Shaw TM, Laibowitz RB, Heinz TF. Charge trapping at the lowk dielectric-silicon interface probed by the conductance and capacitance techniques. Appl Phys Lett 2008;93(12):122902.
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Junil Lee was born in Changwon, Korea, in 1987. He received the B.S degree in Electrical Engineering from Seoul National University in 2013. He is currently working toward Ph.D degree in electrical engineering. His research interests include nanoscale devices, tunnel field-effect transistor (TFET). Mr. Lee is a Student Member of the Institute of Electrical and Electronics Engineers (IEEE) and the Institute of Electronics Engineers of Korea (IEEK).
Byung-Gook Park received his B.S. and M.S. degrees in electronics engineering from Seoul National University (SNU) in 1982 and 1984, respectively, and his Ph. D. degree in electrical engineering from Stanford University in 1990. From 1990 to 1993, he worked at the AT&T Bell Laboratories, where he contributed to the development of 0.1 micron CMOS and its characterization. From 1993 to 1994, he was with Texas Instruments, developing 0.25 micron CMOS. In 1994, he joined SNU as an assistant professor in the School of Electrical Engineering (SoEE), where he is currently a professor. In 2002, he worked at Stanford University as a visiting professor, on his sabbatical leave from SNU. He led the Inter-university Semiconductor Research Center (ISRC) at SNU as the director from 2008 to 2010. His current research interests include the design and fabrication of nanoscale CMOS, flash memories, silicon quantum devices and organic thin film transistors. He has authored and co-authored over 1000 research papers in journals and conferences. Prof. Park has served as a committee member on several international conferences including Microprocesses and Nanotechnology, IEEE International Electron Devices. Meeting, International Conference on Solid State Devices and Materials, and IEEE SiliconNanoelectronics Workshop and served as an Editor of IEEE Electron Device Letters. He received “Best Teacher” Award from SoEE in 1997, Doyeon Award for Creative Research from ISRC in 2003, Haedong Parper Award from the Institude of Electronic Engineers of Korea (IEEK) in 2015, Educational Award from College of Engineering, SNU, in 2006, Haedong Research Award from IEEK in 2008, Nano Research Innovation Award from the Ministry of Science, ICT and Future Planning of Korea in 2013, and Academic Training Award from Seoul National University in 2015.
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