Temperature insensitive current-mode CMOS exponential function generator and its application in variable gain amplifier

Microelectronics Journal 45 (2014) 345–354

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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo

Temperature insensitive current-mode CMOS exponential function generator and its application in variable gain amplifier Karama M. AL-Tamimi n, Munir A. AL-Absi, Muhammad Taher Abuelma0 atti Electrical Engineering, King Fahd University of Petroleum & Minerals, Saudi Arabia

art ic l e i nf o

a b s t r a c t

Article history: Received 25 May 2013 Received in revised form 14 December 2013 Accepted 19 December 2013 Available online 27 January 2014

A new CMOS current-mode circuit to produce the exponential function, y ¼ expðxÞ, is proposed. The proposed design has large input and output dynamic ranges while keeping very small linearity error. The functionality of the proposed design, confirmed using Tanner tool with 0.35 μm CMOS process technology indicates that it has superior performance compared to previously reported designs. A nearly 96 dB output dynamic range is obtained with the linearity error less than 7 0.5 dB over an input range  5.75 rx r 5.75. The change in the output current due to temperature variation is 71.27 dB over 100 1C range. Application of the proposed exponential function generator in the design of an exponentially controlled variable gain amplifier is presented and its functionality is confirmed using simulation. 71 Linear-in-dB variable gain was achieved. The dB gain is controlled linearly by the control current, resulting in simple and low power structure. & 2013 Elsevier Ltd. All rights reserved.

Keywords: Exponential Current-mode Weak inversion CMOS Linear-in-dB Translinear principle Approximation VGA

1. Introduction An exponential function generator produces an output waveform (current/voltage) which is an exponential function of the input waveform (current/voltage). The exponential characteristics can be easily obtained in BJT or BiCMOS technologies using the intrinsic exponential characteristics (I C ¼ f ðV BE Þ) of the bipolar transistors [1]. However, it is not easy to realize such function in CMOS technology because of the inherent squarelaw or linear characteristics of MOSFET operating in strong inversion region. The widely used technique to implement analog exponential function circuits using MOSFET in strong inversion is based on pseudo-approximations. To mathematically implement the exponential function by this method, different approximations have been already introduced; Taylor series 2nd order [2–5], Taylor series 4th order [6], Pseudo exponential [7], Pseudo–Taylor approximation [8], Modified Pseudo–Taylor approximation [9] and rational function approximation [10]. On the other hand, a MOSFET device biased in weak inversion region is a well-known approach to produce an exponential function due to the exponential relationship between IDS and VGS of MOSFET in weak inversion regime; see for example Refs. [11,12,15] and some of the references cited therein. The drain current of MOSFET in weak

inversion region is given by
 V GS  V th W 2 nU T I DS ¼ 2nμn C ox V T e L

Although the low VGS voltage makes this technique efficient in low voltage applications compared with realizations that use MOSFET in strong inversion regime, the exponential relation between IDS and VGS suffers from strongly temperature dependency, threshold voltage variation effect, and sensitivity to process parameters variation. In this paper, a new exponential approximation is proposed. The new approximation demonstrates 96 dB output dynamic range over maximum input range  5:75 r x r 5:75 while keeping linearity error less than 7 0.5 dB level. The implemented circuit is designed and simulated using 0.35 μm CMOS process.

2. Proposed exponential circuit design 2.1. Design concept Based on Taylor0 s series expansion, the exponential function can be approximated as expressed by Eq. (2): ex ¼ 1 þ x þ

n

Corresponding author. E-mail address: [email protected] (K.M. AL-Tamimi).

0026-2692/$ - see front matter & 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.mejo.2013.12.010

ð1Þ

x2 x3 x4 xn þ þ þ⋯þ þ⋯ 2! 3! 4! n!

ð2Þ

where x is the independent input variable. For  1:2 rx r2:0; the higher order terms in Taylor0 s approximation can be neglected and

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Eq. (2) can be approximated up to the 4th order with 30 dB linear output range whereas the error in 70.5 dB level. It implies that large output range requires more terms and consequently more complexity. The proposed technique in this paper is incorporation of pseudo-exponential, 4th-order and coefficients optimization at the same time to significantly extend the output range without higher terms. The proposed approximation can be expressed as

40

20 Value (dB)

ex ¼

60

eðð1=2ÞxÞ 1 þ ϒ 0 þ ðϒ 1 =2Þx þ ðϒ 2 =4Þðx2 =2!Þ þ ðϒ 3 =8Þðx3 =3!Þ þ ðϒ 4 =16Þðx4 =4!Þ ¼ eð  ð1=2ÞxÞ 1 þ ϒ 0  ðϒ 1 =2Þx þ ðϒ 2 =4Þðx2 =2!Þ  ðϒ 3 =8Þðx3 =3!Þ þ ðϒ 4 =16Þðx4 =4!Þ

0 Exact

ð3Þ

Taylor series 2nd-order [2]

-20

Taylor series 4th-order [6]

equivalently, the numerator and denominator can be rewritten as illustrated in Eq. (4):

ϒ

1 þ ∑4n ¼ 0 ½ n xn =2n n! 1 þ ∑4n ¼ 0 ½ð  1Þn ð n xn =2n n!Þ

x

e ¼

Pseudo-exponential [7]

Modified Pseudo Taylor approximation [9] Rational Function Approximation [10]

ð4Þ

ϒ

Prposed approximation in this work

-60 -6

where Y0, Y1, Y2, Y3 and Y4 are linear polynomial coefficients which introduced to be optimized. The “Linear Least Squares” optimization method in MATLAB tool has been used to compute the optimum values for the coefficients Y0, Y1, Y2, Y3 and Y4 of the polynomials in Eq. (4) that approximate ex for input range 5:75 r x r 5:75 which result in 96 dB linear output range. It was found that ϒ 0 ¼ 0:025, ϒ 1 ¼ 1, ϒ 2 ¼ 3=4, ϒ 3 ¼ 3=8, and ϒ 4 ¼ 3=32. One of the features of this approximation and the obtained coefficients0 values is that a “perfect square trinomial” form can arise in the numerator and denominator which lead to the following final approximation: 0:025 þð1 þ 0:125xÞ4

ð5Þ

0:025 þð1  0:125xÞ4

The major difference in the proposed pseudo-exponential rather than conventional approximations is the consideration of the terms x2 and x4 only while the term x3 has been eliminated. These terms can be simply and accurately implemented in the CMOS technology. One squaring unit and two cascaded can provide the terms x2 and x4, respectively. Furthermore, the output range was extended more around three times compared to the conventional 4th order approximation with fewer terms. Fig. 1 shows the dB-scale of the proposed exponential function approximation given in Eq. (5). Fig. 2 shows a comparison between different approximation techniques reported in the literature and Fig. 3 shows the error in each approximation. Inspection of Figs. 2 and 3 clearly shows that the proposed approximation of Eq. (5) achieves the best output range and maximum normalized

-4

-2

0

2

4

6

Normalised Input(X)

Fig. 2. Comparison between different approximations. 1.5

1

0.5 Error(dB)

ex ffi

Pseudo-Taylor approximation [8]

-40

0

-0.5

-1

-1.5 -6

-4

-2

0

2

4

6

Normalised Input (X)

Fig. 3. The error between different approximations and the ideal function.

input range compared to the other approximations with 70.5 dB error. Table 1 compares the input and output ranges of different approximations.

80 Exact Prposed Approximation

60

2.2. Circuit description

40

Fig. 4 shows the block diagram of the proposed implementation of the exponential function of Eq. (5). In the following subsections the description of each block will be given and it will be shown that the relationship between the input current Ix and the output current Iout will be given by

Value (dB)

20 96 dB

0

-20

I out ¼ I w

-40

I num ¼ I w eðIx =Iref Þ I den

ð6Þ

where Iw and Iref are reference currents.

-60

-80 -8

-6

-4

-2

0

2

4

6

Normalised Input(x)

Fig. 1. Proposed exponential function approximation of Eq. (5).

8

2.2.1. Squaring circuit The circuit diagram of the squaring circuit used in Fig. 4 is shown in the dashed box in Fig. 5 [13]. The aspect ratios of all transistors are listed in Table 2.

K.M. AL-Tamimi et al. / Microelectronics Journal 45 (2014) 345–354

347

Table 1 Performance comparison between different exponential approximations approaches. Approximation

Equation

Input range

Output range (dB) 13.3

2nd order taylor series [2–5]

1 þ x þ 12x2

 0:6r x r 0:85

4th order taylor series [6]

1 3 1 4 1 þ x þ 12x2 þ 3! x þ 4! x

 1:2r x r 2:0

30

Pseudo exponential [7]

0:5x ex ffi 11 þ  0:5x

 0:85r x r 0:85

14.8

Pseudo–Taylor approximation (m¼1) [8]

þ ð1 þ 0:5xÞ ex ¼ ee 0:5x ffi m m þ ð1  0:5xÞ2

2

 1:08r x r 1:08

17.8

Pseudo–Taylor approximation (m¼0.82) [8]

þ ð1 þ 0:5xÞ ex ¼ ee 0:5x ffi m m þ ð1  0:5xÞ2

2

 1:63r x r 1:63

27.2

Modified Pseudo–Taylor approximation [9]

þ ð1 þ 0:25xÞ2 e ffi 0:12 0:12 þ ð1  0:25xÞ2 h 0:25ax i2 0:026ax þ ð1 þ 0:25axÞ2 ex ¼ ee 0:25ax ffi 0:026ax þ ð1  0:25axÞ2

 3:1r x r 3:1

56

 3:3r x r 3:3

60

 5:75r x r 5:75

96

0:5x

0:5x

x

Rational function approximation [10] Proposed

e

Generator

x

þ ð1 þ 0:125xÞ4 ffi 0:025 0:025 þ ð1  0:125xÞ4

Applying translinear loop principle in Fig. 5 for transistors M1– M4 yields

Generator

V gs1 þ V gs2 ¼ V gs3 þV gs4 1.6Iref

1.6Iref Single-Quadrant Divider

E

Squaring Circuit

C

I1 I2 ¼ I3 I4

D

Current Mirror

A

1:8

ð8Þ

Since, I 1 ¼ I 2 ¼ I x , I 3 ¼ 4I ref and I 4 ¼ I out , the output current can be written as

Squaring Circuit

Squaring Circuit

Iref

where,V gs1 , V gs2 , V gs3 and V gs4 are the gate-to-source voltages of transistors M1, M2, M3 and M4, respectively. From Eq. (7), with the four MOSFETs operating in weak inversion, it is easy to show that

F

Squaring Circuit

ð7Þ

I out ¼

B

1:8

I 2x 4I ref

ð9Þ

Eq. (9) represents the current-mode squaring function. The squaring circuit is a key block in the proposed current-mode exponential function generator of Fig. 4. Fig. 4. Block diagram of the proposed current-mode exponential generator.

2.2.2. Current divider The circuit diagram of one quadrant current-mode divider is shown in the dashed box in Fig. 6 [14]. A single quadrant current divider function is realized using transistors Ma–Md where all transistors are operating in the sub-threshold region. Writing the translinear loop for the transistors in the dashed box gives V sga þ V sgb ¼ V sgc þ V sgd

ð10Þ

with transistors Ma–Md working in the subthreshold region Eq. (10) yields Ia Ib ¼ Ic Id

ð11Þ

If I a ¼ I w , I b ¼ 0:125I num , I c ¼ 0:125I den , and I d ¼ I out , then Eq. (11) will become I out ¼ I w

Table 2 Aspect ratios of squaring unit. Aspect ratio

M1, M3 M2, M4 M5–M10

3:5=7 91:7=7 7=7

W ðμmÞ L ðμmÞ

ð12Þ

The transistor aspect ratios of Fig. 6 are shown in Table 3. It is worth mentioning here that ðW=LÞj;l ¼ ð1=8ÞðW=LÞi;k to scale down the currents Inum and Iden so that transistors Mb and Mc will remain operating in weak inversion. This implies that the aspect ratios of all the transistors involved in the translinear loop must be selected to meet the anticipated dynamic range of the input and output currents.

Fig. 5. Squaring circuit [13].

Transistor

I num I den

Ratio 0.5 13.1 1

2.2.3. Bidirectional current mirror (BDCM) Fig. 7 shows the circuit diagram of the current mirror used. If the input current is Ix then two copies of this current can be obtained at the output, Ix and  Ix. The aspect ratios of all the transistors used are listed in Table 4.

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K.M. AL-Tamimi et al. / Microelectronics Journal 45 (2014) 345–354

Fig. 6. Single-Quadrant Divider [14].

Table 3 Transistor aspect ratios. Transistor

IE ¼ Aspect ratio

Ma, Md Mb, Mc Me–Mh Mi, Mk Mj, Ml Mm–Mn

W ðμmÞ L ðμmÞ

Ratio

196=1:4 175=1:4 7=7 19:6=19:6 2:45=19:6 1=1

140 125 1 1 0.125 1

IF ¼

ð8I ref Þ4 ð1 þ 0:125ðI x =I ref ÞÞ4 ð4I ref Þ3 ð8I ref Þ4 ð1  0:125ðI x =I ref ÞÞ4 ð4I ref Þ3

¼ 64I ref ð1 þ 0:125ðI x =I ref ÞÞ4

ð17Þ

¼ 64I ref ð1  0:125ðI x =I ref ÞÞ4

ð18Þ

I num ¼ 1:6I ref þ64I ref ð1 þ 0:125ðI x =I ref ÞÞ4 ¼ 64I ref ½0:025 þð1 þ 0:125ðI x =I ref ÞÞ4 

ð19Þ

I den ¼ 1:6I ref þ 64I ref ð1  0:125ðI x =I ref ÞÞ4 ¼ 64I ref ½0:025 þ ð1  0:125ðI x =I ref ÞÞ4 

ð20Þ

Combining Eqs. (12), (19) and (20), the output current is given by I out ¼ I w

( ) ½0:025 þ ð1 þ 0:125ðI x =I ref ÞÞ4  I num ¼ Iw I den ½0:025 þ ð1  0:125ðI x =I ref ÞÞ4 

ð21Þ

Using the proposed approximation in Eq. (5), the output current can be written as I out ffi I w eðIx =Iref Þ

where Iout is the output current, Ix is the input current signal, Iref is a constant current and Iw is a DC component which can be used to scale the output signal. From Eq. (22), it is clear that an exponential current-mode function generator can be realized and its output current can be scaled by the current, Iw. The complete circuit diagram of the proposed current-mode exponential function generator (EXPFG) is shown in Fig. 8.

Fig. 7. Current mirror (a) circuit and (b) symbol.

Table 4 Transistors aspect ratios for the current mirror. Transistor

Aspect ratio

Mn1–Mn5 Mp1–Mp5

1=10 1:7=10

W ðμmÞ L ðμmÞ

ð22Þ

Ratio 0.1 0.17

3. Simulation results

2.2.4. Mathematical analysis With reference to Fig. 4, there are six nodes A–F. Applying KCL at each node and using Eq. (9) yields the following: I A ¼  ð8I ref þ I x Þ ¼  8I ref ð1 þ 0:125ðI x =I ref ÞÞ

ð13Þ

I B ¼  ð8I ref I x Þ ¼  8I ref ð1  0:125ðI x =I ref ÞÞ

ð14Þ

IC ¼

ð8I ref Þ2 ð1 þ 0:125ðI x =I ref ÞÞ2 4I ref

ð15Þ

ID ¼

ð8I ref Þ2 ð1 0:125ðI x =I ref ÞÞ2 4I ref

ð16Þ

The functionality of the proposed exponential circuit was verified by simulation using Tanner tools with 0.35 μm CMOS process technology and supply voltage 70.75 V. The simulation result is illustrated in Fig. 9 where Iref equals to 25 nA. Thus the x-axis, 150 nA r I x r 150 nA, can be normalized as 6 rI x =I ref r6. The curve of the proposed function is very close to the ideal exponential function, I w eðIx =25 nAÞ , with a high output dynamic range, nearly 96 dB. The error between the proposed function and the ideal exponential function, I w eðIx =25 nAÞ , is limited to 70.5 dB when  137:5 nA r I x r 137:5 nA, as illustrated in Fig. 10. Simulation of transient response was carried out with sinusoidal input signal of frequency 5 kHz. The results are shown in Fig. 11. Simulation for temperature analysis was carried out. The temperature was varied from  25 1C to þ75 1C and the simulation result, shown in Fig. 12, shows that the input–output characteristic is

K.M. AL-Tamimi et al. / Microelectronics Journal 45 (2014) 345–354

349

Fig. 8. The complete circuit diagram for the proposed exponential function.

insensitive to temperature variations. The linearity error remains less than 71.5 dB for the full scale of the input current range. The maximum deviation of the output current was about 71.27 dB and occurred for the normalized value I x =I ref ¼ 5:25. Simulation for power supply variation was also carried out. A 10% variation in the supply voltage at room temperature was used. Simulation results shown in Fig. 13 indicate that the circuit is stable with power supply variations within 10% of the nominal value. Table 5 summarizes the comparison between the performance of the proposed circuit and recently published works. Inspection of Table 5 clearly shows that the proposed exponential function generator enjoys the largest linear-in-dB range of 96 dB while consuming about 6.13 mW and is stable over a wider range of temperature variations.

4. Mismatch analysis Referring to Fig. 4, if there is a mismatch in the current mirror used in mirroring the constant current (1:6I ref Þ, (i.e., it is equal to 1:6I ref þ ΔI ref ), then Eqs. (19)–(21) can be reevaluated and the output current will be expressed as I out

( ) ½k þ ð1 þ 0:125ðI x =I ref ÞÞ4  I num ¼ Iw ¼ Iw I den ½k þ ð1  0:125ðI x =I ref ÞÞ4 

ð23Þ

where k ¼ 0:025 þ ðΔI ref =64I ref Þ. The simulation result shown in Fig. 14 indicates that the deviation due to 10% mismatch is less than 70.03%. In real implementation, there are always process variation and mismatch effects. To study such effect, Monte Carlo test

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60

60 Exact Proposed approximation

Normalised Iout (dB)

Normalised Iout (dB)

Exact Simulated Results@-25° Simulated Results@+25° Simulated Results@+75°

40

CMOS simulated results of the proposed approximation

40

20

0

20

0

±1.27dB

-20

-20 -40

-40 -60 -4

-6

-60 -6

-4

-2

0

2

4

-2

0

2

4

6

Normalised input current (Ix/Iref)

6

Fig. 12. Temperature variation  25 1C, þ 25 1C and þ 75 1C.

Normalised input current (Ix/Iref) Fig. 9. Linear-in-dB characteristics of the proposed EXPFG. 60

±3.35dB

2.5 Error of the proposed approximation

2

Normalised Iout (dB)

Error of CMOS implementation

1.5 1 Error(dB)

Exact Simulated Results@ ±0.675V Simulated Results@ ±0.750V Simulated Results@ ±0.825V

40

0.5 0 -0.5

20

0

-20

-40 ±0.72dB

-1 -60 -8

-1.5

-6

-4

-2

0

2

4

6

8

Normalised input current (Ix/Iref)

-2

Fig. 13. Linear-in-dB characteristics for 7 10% variation in voltage supply.

-2.5 -6

-4

-2

0

2

4

6

Normalised input current (Ix/Iref) Fig. 10. The error in dB between Eq. (2) and its CMOS implementation of Fig. 8.

the nominal value of the output current is found to be 7 1.8 dB for 1.2 normalized input, while the error in  3 dB frequency is 0.02%.

5. Exponential-control VGA

600 Input Current (Ix) Exact Iout

500

Simulated Iout

Value (nA)

400 300 200 100 0 -100 0

200

400

600

800

1000

Time(μs) Fig. 11. Transient response of the proposed EXPFG.

has been carried out for 100 iterations. For 5% variation in the aspect ratios of the core transistors in the squaring loop (M1, M2, M3 and M4), the histogram shown in Fig. 15(a) and (b) indicates that the corresponding maximum variation from

The linear-in-dB variable gain amplifier (VGA) is usually employed in Automatic Gain Control (AGC) loop to increase the signal-to-noise ratio (SNR) in wireless receivers [16], to enhance the system performance regarding the linearity, SNR and power consumption in the global positioning system (GPS) receivers [17], in disk drives [18], in biomedical signal acquisition [19] and directconversion receivers [20]. Various approaches to implement VGAs circuits have been reported [16–23] and such circuits can be found in several signal processing applications. Among the most significant demands of VGAs are the wide range of gain variation, low sensitivity against voltage supply variation, small chip size and low power consumption. In the following subsection a description for a new proposed exponential-control VGA, using the exponential function generator described in Fig. 8 will be highlighted. 5.1. Proposed exponential-control VGA The proposed exponential-control VGA, shown in Fig. 16, was developed based on the new exponential function generator obtained based on the approximation given in Eq. (5) and its CMOS implementation shown in Fig. 8. In Fig. 16 the control signal is applied to the input of the EXPFG cell and the input small signal

K.M. AL-Tamimi et al. / Microelectronics Journal 45 (2014) 345–354

351

Table 5 Performance comparison table between different exponential function circuits. Parameter

[2]a

[10]

[12]

[15]

This work

Year Voltage supply Process Power dissipation Technique Operation region Input signal Output signal Linear-in-dB range Linearity error BW ΔT range Error due ΔT ΔV range Error due ΔV

2005 1V 0.35 μm CMOS 3.5 μW Approximation Weak inversion Current Current 8.5 dB 7 0.45 dB NA NA NA NA NA

2008 1.8 V 0.18 μm CMOS NA Approximation Strong inversion Current Current 58 dB 7 0.5 dB NA NA NA NA NA

2012 1.5 V 0.35 μm CMOS 400 μW Exact Weak inversion Voltage Current 40 dB 70.75 dB NA  10 1C: 70 1C 73 dB 710% V 71 dB

2011 1.8 V 0.18 μm CMOS 214 nW Exact Weak inversion Voltage Current NA 7 0.92 dB NA NA Dependent NA NA

2012 7 0.75 V 0.35 μm, 2p4m CMOS 6.13 μW Approximation Weak inversion Current Current 96 dB 7 0.5 dB 105 kHz  25 1C: 75 1C 7 1.27 dB 7 10% V 7 3.35 dB

a

Experimental.

60

8

40

No. of Samples

Exact Prposed Approximation k=0.025 Prposed Approximation k=0.025+10% Prposed Approximation k=0.025-10%

Value (dB)

20

0

-20

6 4 2 0

8.576

8.578

8.58

Iout (dB)

-40

-60 -6

-4

-2

0

2

4

15

6

No. of Samples

Normalised Input(x)

Fig. 14. Effect of mismatch in the current mirror.

has been added to the DC component Iw in the divider included in EXPFG. Applying the Kirchhoff0 s Current Law (KCL) at node Z in Fig. 16 and using Eqs. (24)–(27) yields Using Eq. (22) the currents I out;1 and I out;2 can be expressed as I out;1 ¼ ðI w þ I in ÞeðIctrl =Iref Þ

ð24Þ

I out;2 ¼ I w eðIctrl =Iref Þ

ð25Þ

10

5

0

102.53 102.54 102.55 102.56 102.57

f3dB (kHz) Fig. 15. (a) Monte Carlo analysis for output current when normalized input ¼ 1.2 and (b) the frequency bandwidth histogram.

Applying KCL at node z yields I out ¼ I out;1  I out;2 ¼ ðI w þ I in ÞeðIctrl =Iref Þ  I w eðIctrl =Iref Þ

ð26Þ

or I out ¼ I in eðIctrl =Iref Þ

ð27Þ

Bidirectional Current Mirror

Eq. (24) can be rewritten as Ai ¼

I out ¼ eðIctrl =Iref Þ I in

Generator

ð28Þ

Single-Quadrant Divider

I Exponential Cell

where Ai is the current gain, I ctrl is the control signal and I ref is the reference constant current. From Eq. (28), it is obvious that a variable-gain current amplifier can be realized and its gain can be exponentially controlled by the control current I ctrl . The gain in linear dB scale is calculated as follows: Ai ðdBÞ ¼ 20 log 10 ðeðIctrl =Iref Þ Þ

Generator

ð29Þ

Bidirectional Current Mirror

Generator Generator

Single-Quadrant Divider

Z

Fig. 16. The proposed structure of exponential-control VGA.

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K.M. AL-Tamimi et al. / Microelectronics Journal 45 (2014) 345–354

Eq. (29) can be rewritten as

600

I Ai ðdBÞ ¼ 8:69 ctrl I ref

gives highest amplification

400

ð30Þ

Input Signal, Iin

Eq. (30) readily shows that the gain in dB scale is linearly proportional to the control signal. 60

Current (nA)

200

0

-200 Control Signal, Ictrl

Simulated VGA Gain Exact VGA Gain

40

gives highest attenuation

-400

-600

Output Signal, Iout

Gain (dB)

20 -800 0

0.5

1

0

1.5

2

2.5

3

Time(ms)

Fig. 20. VGA response with triangular control signal. -20

-40 1000

-60

-6

-4

-2 0 2 Normalised Control Current (Ictrl/Iref)

4

exponentially amplification

Input Signal, Iin

6 500 Current (nA)

Fig. 17. Simulation results of the proposed exponential-control VGA.

50 40

Iin Iout when Gain=-6dB Iout when Gain=0dB

30

Iout when Gain=6dB

Control Signal, Ictrl

-500

exponentially attenuation Output Signal, Iout

20 Current (nA)

0

-1000

10

0

0

0.5

1

1.5

2

2.5

3

Time(ms)

-10

Fig. 21. VGA response with sinusoidal control signal.

-20 -30 -40 -50

60 0

0.5

1

1.5

2

2.5

3

Exact

Time(ms)

Fig. 18. Different gain values effect.

40

800

20

600

Gain (dB)

Output Signal,Iout 400 Input Signal,Iin

Current (nA)

200 0 -200

Load increased from 0Ω to 1 M Ω with Iin=20nA

0

-20

Control Signal,Ictrl

-400 -600

-40

-800 -1000 0

0.5

1

1.5

2

2.5

3

Time(ms)

Fig. 19. Transient analysis of the overall circuit Iin is a 10-kHz sinusoidal signal and Ictrl is a ramp. Iout is shown to have variable amplitude.

-60 -6

-4 -2 0 2 4 Normalised Control Current (Ictrl/Iref) Fig. 22. Load effect figure.

6

K.M. AL-Tamimi et al. / Microelectronics Journal 45 (2014) 345–354

5.2. Simulation results of the proposed VGA Simulation results are given to verify the functionality of the proposed VGA. Tanner tool is used with standard 0.35 μm CMOS process to simulate the proposed structure of exponential-control VGA in Fig. 16. The DC supply voltage set to 70.75 V and the current Iref was set to 25 nA. Fig. 17 shows that the output control range is around 71 dB with 7 0.5 dB linearity error. Different

60 Exact 40

Iin increased from10nA to 50nA with 10M Ω Load

Gain (dB)

20

0

-20

-40

-60 -6

-4 -2 0 2 4 Normalised Control Current (Ictrl/Iref)

6. Conclusion

20 0 Gain= -6dB Gain= 0dB Gain= 6dB

Magnitude (dB)

-40

Load: R=10kΩ C=0F

-60 -80 -100 -120

Load: R=10kΩ C=50pF

-140 -160 -180 10-4

10-3

10-2

10-1

100

values of Ictrl (  17.33 nA, 0 nA and 17.33 nA) have been used to meet  6 dB, 0 dB and 6 dB gain values, respectively, and as a result the eventual output signal changed accordingly as shown in Fig. 18. Transient analysis of the overall circuit is shown in Fig. 19; where Iin is a sinusoidal signal with 10 kHz frequency and 20 nA amplitude and Ictrl is chosen to be a ramp signal. The figure demonstrates the variable gain effect on the amplitude of the output current. Simulation was carried out to confirm the functionality of the proposed VGA when 10 kHz sinusoidal input signal and amplitude 20 nA was used. The control signal was a triangular of 200 nA peak-to-peak and a frequency of 1 kHz and 10 kHz sinusoidal with amplitude of 100 nA as shown in Figs. 20 and 21, respectively. When I ctrl ¼ 100 nA the VGA gives highest amplification and when I ctrl ¼  100 nA it gives highest attenuation. The effect of the load and different amplitudes has been studied and simulated by sweeping the load from 0 to 10 MΩ when the amplitude is set to 40 nA and the amplitude of the input varies from 10 nA to 50 nA when the load set to be 10 kΩ and results are shown in Figs. 22 and 23, respectively. AC simulation is given in Fig. 24 with resistive (R) and complex (RC) load effect. If R¼10 kΩ while Gain ¼  6 dB, 0 dB and 6 dB, the corresponding  3 dB frequency is 174 kHz, 242 kHz and 291 kHz, respectively but if a capacitance C ¼50 pF is added in parallel with R, then for Gain¼ 0.5, 1 and 2 the  3 dB frequency is 132 kHz, 170 kHz and 181 kHz, respectively. Table 6 outlines the most important features of the proposed VGA compared to the prior works. These performance parameters are either better or compare favorably with the reported state-ofthe-art VGAs.

6

Fig. 23. Different Iin amplitude effect.

-20

353

101

102

103

Frequency (MHz)

Fig. 24. AC response of the proposed VGA.

In this paper, a new low power CMOS realization of a current mode exponential function generator has been developed. The developed design is based on a new exponential approximation and MOSFET transistors operate in the weak inversion region. The advantages of the proposed circuit are the extended output range, low voltage supply, temperature insensitive and the stability over the voltage supply variations. The circuit operation was confirmed by simulation with standard 0.35 mm CMOS process using 70.75 V nominal supply voltage. The simulation results demonstrate linear-dB input/output characteristics with 96 dB dynamic range featuring 71.27 dB for 100 1C temperature range and maximum 73.35 dB variation for 710% supply deviation from the nominal value. Using the proposed current-mode exponential function generator, an exponentially controlled current-mode variable gain amplifier (VGA) has been developed and simulated. The simulation results show that the proposed VGA compares well with the already published realizations.

Table 6 Comparison with prior works. Parameter

[20]

[21]

[22]

[23]

This work

Year Process (CMOS) (μm) Gain (dB) Stages Voltage supply (V) BW Power consumption

2012 0.18  3 to 45 1 1.8 3 MHz 0.549 mW

2004 0.5  26.79 to 23.94 1 2 134 kHz 1.6 μW

2006 0.18 0–95 3 1.8 32 MHz 6.48 mW

2009 0.18  10 to 50 3 1.8 8 MHz 6.7 mW

2012 0.35  49 to 22 1 7 0.75 181 kHza 12.782 μW

a

@ RC ¼ 0.5 μs and Gain ¼2.

354

K.M. AL-Tamimi et al. / Microelectronics Journal 45 (2014) 345–354

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