The impact of interface states on the mobility and drive current of In0.53Ga0.47As semiconductor n-MOSFETs

Solid-State Electronics xxx (2015) xxx–xxx

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The impact of interface states on the mobility and drive current of In0:53 Ga0:47 As semiconductor n-MOSFETs Patrik Osgnach ⇑, Enrico Caruso, Daniel Lizzit, Pierpaolo Palestri, David Esseni, Luca Selmi DIEGM, Università degli studi di Udine, Via delle Scienze 206, 33100 Udine, Italy

a r t i c l e

i n f o

Article history: Available online xxxx The review of this paper was arranged by B. Gunnar Malm Keywords: Monte Carlo III–V semiconductors Border traps Interface states Modelling

a b s t r a c t Accurate Schrödinger-Poisson and Multi-Subband Monte Carlo simulations are used to investigate the effect of interface states at the channel-insulator interface of In0:53 Ga0:47 As MOSFETs. Acceptor states with energy inside the conduction band of the semiconductor can explain the dramatic Fermi level pinning observed in the experiments. Our results show that these states significantly impact the electrical mobility measurements but they appear to have a limited influence on the static current drive of short channel devices. Ó 2015 Elsevier Ltd. All rights reserved.

1. Introduction

2. Model description

The replacement of silicon with III–V compound semiconductors as channel material in advanced MOSFETs has been widely investigated over the last years [1,2]. The surface trap-state density of III–V compounds is much larger than that of state of the art silicon/SiO2 interfaces [3,4], and Hall mobility measurements have shown that the charging of these states results in a remarkable Fermi level pinning which precludes attaining a free carrier density larger than N S  5  1012 cm2 [5,6]. This large trapped charge affects the electrostatics but it does not contribute to the drain current. Consequently, one of the basic assumptions at the foundation of split-CV mobility extraction techniques is violated [7]. In this paper, a self-consistent solution of the Schrödinger and Poisson equations in the presence of interface charge is used to extract the energy profile Dit ðEÞ of interface states. The extracted charge is then introduced in a Multi-Subband Monte Carlo (MSMC) simulator [8,9], both as a source of Coulomb scattering and as a contribution to device electrostatics, to asses its effect on low field electrical mobility and on the drive current, ION , of short channel devices. The paper extends our previous report in [10] by providing a more detailed analysis of the experiments including Hall and electrical mobility.

Interface states have been introduced in the equilibrium solution of the coupled Schrödinger and Poisson equations as a sheet of charge at the interface between the channel and the gate dielectric. The Schrödinger equation is solved using the parabolic effective mass approximation, then the non-parabolicity correction from [11] is applied. If we let EPm;n be the parabolic n-th subband minimum of valley m, then the corresponding non-parabolic subband minimum ENP m;n is given by:

⇑ Corresponding author. E-mail address: [email protected] (P. Osgnach).

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 þ 4am  ðEPm;n  U m;n Þ  1

ENP m;n ¼ U m;n þ 2am Z 2 U m;n ¼ jnm;n ðyÞj UðyÞdy

ð1Þ

where UðyÞ is the confining potential along the quantization direction y; am is the non-parabolicity coefficient and nm;n is the wavefunction obtained with parabolic bands. The model is thus appropriate for near equilibrium conditions to investigate, for instance, MOSFETs biased at low V DS and lowfield mobility measurements. The solution of the Schrödinger equation considers wave-function penetration in the dielectrics, which can be relevant in III–V materials [9], The interface charge per unit area Q it ¼ qN it is computed under the following assumptions: (a) traps below the semiconductor mid-gap (Em ) are donor-like, i.e., they contribute with a positive

http://dx.doi.org/10.1016/j.sse.2014.12.011 0038-1101/Ó 2015 Elsevier Ltd. All rights reserved.

Please cite this article in press as: Osgnach P et al. The impact of interface states on the mobility and drive current of In0:53 Ga0:47 As semiconductor n-MOSFETs. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2014.12.011

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P. Osgnach et al. / Solid-State Electronics xxx (2015) xxx–xxx

charge when empty [7]; (b) traps above the mid-gap are acceptorlike, i.e., they contribute with a negative charge when occupied by an electron [7]; and (c) the occupation probability f ðE; EF Þ follows the equilibrium Fermi–Dirac statistics. We further choose to express Dit as:

Z

Em

Dit ðEÞ  ½1  f ðE; EF ÞdE þ

Z

1

Dit ðEÞ  f ðE; EF ÞdE

ð3Þ

where EF is the equilibrium Fermi level and Em is the energy level that separates donor-like from acceptor-like traps. Eq. (2) is polynomial on a semi-logarithmic scale. The shape of the Dit energy distribution is set by the coefficients ai . Dit ðEC Þ is the trap concentration at the conduction band edge (EC ) of the semiconductor in units of eV1 cm2 . A correct choice of the Dit ðEC Þ, the polynomial degree, n, and coefficients, ai , is necessary to reproduce experimental N S and mobility curves [6,5]. Fig. 1 compares simulated N S ðV GS Þ curves with experimental data from [6]. Polynomials of different degree can be used to fit the measurements but, after choosing the appropriate coefficients, the trap distributions are very similar as can be seen by looking at the Dit energy profiles in the inset. In the following, we have opted for the lowest degree n ¼ 2 that results in a good agreement with the experiments. Also, this choice makes easier the task of finding the optimal coefficients. To this end, we note that for the sole purpose of finding the best coefficients in Eq. (2), traps do not necessarily need to enter the coupled Schrödinger-Poisson problem explicitly; in fact, since wave-function penetration beyond the surface charge layer is modest, self-consistent calculations with traps can be accurately reproduced if the abscissa of a simulated N S ðV GS Þ curve without traps is ‘‘stretched’’ by an amount equal to Q it ðV G Þ=C OX . Fig. 2 illustrates the use of this technique. The stretching implies that the same N S is found at a higher gate voltage in the case with traps. To extract the Dit energy spectrum and determine the fitting parameter values we set up a global optimisation problem whose solution is the set of ai and Dit ðEC Þ coefficients that yields the best agreement between measured and simulated N S ðV GS Þ curves. In other words, we have to find the correction term Q it ðV Gsim Þ that minimises the difference between the experimental and simulated N S ðV GS Þ. In formula, the problem is to minimise:

4.5 exp. from [6], unstrained n=2 n=3 n=4

4.0

16

10

3.5

15

10 -2

Dit [eV cm ]

3.0

-1

-2

NS [1e12 cm ]

4

-2

Em

1

2.5

14

10

13

10

12

10

11

10

10

10

2.0

9

10

-0.4

-0.2

0

0.2

0.4

E - EC [eV]

1.5

NS [10

where E is the state energy. The N it is then given by:

Nit ¼ 

6

12

ð2Þ

Simulation w/o traps Stretched Simulation w/ traps

8

cm ]

 Pn  i Dit ðEÞ ¼ Dit ðEC Þ  10 i¼1 ai ðEEC Þ

10

0

1

2

3

4

5

6

VGS [V] Fig. 1. Simulated N S ðV GS Þ for different polynomial degree n in Eq. (2). The inset shows the extracted Dit corresponding to each polynomial function.

2

0 0

2

4

6

8

VGS [V] Fig. 2. Illustration of the stretching technique used to fit the free carrier density versus gate bias curves. First, an N S ðV GS Þ curve is simulated without considering the effect of interface traps (solid line); then, this curve is stretched by Q it ðV GS Þ=C OX (dashed line). The circles represent N S ðV GS Þ simulations with the full self-consistent loop considering the effect of interface traps. The agreement between the dashed curve and the symbols proves the validity of the proposed extraction algorithm.

  2   V Gexp ðNSexp Þ  V Gsim ðNSsim Þ  Q it ðV Gsim Þ    C OX 2

ð4Þ

where V Gsim ðN Ssim Þ is obtained from simulations without interface traps. The search for the solution of the minimisation problem (that is, the sought set of Dit ðEC Þ and a1 ; . . . ; an ) must be adequately constrained, otherwise the result may still fit the experiments but with an unrealistic Dit profile. In particular, based on results in [5], we expect Dit profiles with exactly one minimum at a specific energy (e.g. the midgap) and no maximum. It is not always straightforward to satisfy these requirements, but if the polynomial is a second order one, we just need to enforce a2 to be positive. Note that, since the Dit is fitted on Fermi level pinning experiments, it may end up being inaccurate in the gap. We will return later on this point. Note that the stretching technique described so far is used only for the purpose of finding the optimal coefficients of Eq. (2), whereas in the other calculation of this paper, the full self-consistent problem is solved. 3. Results: Fermi level pinning and Dit profiles We define the Fermi level pinning as the condition at which an increase of the gate voltage corresponds to a very small increase of the Fermi level with respect to the minimum of the conduction band, and we consider MOSFETs at equilibrium (V DS ¼ 0 V), consistently with the bias used during Hall mobility measurements and N S ðV GS Þ extraction. Fig. 3 reports a few of the N S ðV GS Þ as measured by different groups [5,6,12]. The curves saturate at high gate voltage, indicating Fermi level pinning. If we express Dit as in Eq. (2) and determine the coefficients Dit ðEC Þ; a1 and a2 by solving the minimisation problem of Eq. (4), good agreement between our model and experiments can be obtained. Each data set saturates at a different free carrier density, therefore in principle each set has a different Dit profile. Fig. 4 reports the Dit ðEÞ over the energy range spanned by the Fermi level when V GS spans from approximately 0V to the maximum V GS in the experiments (see Fig. 3). Interestingly, the spread between the various Dit profiles is not too large for the considered In0:53 Ga0:47 As=Al2 O3 devices, demonstrating a comparable degree of maturity in the fabrication process. However, given the exponential increase of Dit ðEÞ, small horizontal shifts of energy have

Please cite this article in press as: Osgnach P et al. The impact of interface states on the mobility and drive current of In0:53 Ga0:47 As semiconductor n-MOSFETs. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2014.12.011

3

6

5

5

4

4

12

-2

cm ]

6

3

NS [10

NS [10

12

-2

cm ]

P. Osgnach et al. / Solid-State Electronics xxx (2015) xxx–xxx

exp. [6], unstrained exp. [6], strained exp. [5] exp. [13]

2

1

3

exp. [6], unstrained exp. [6], strained

2

1

Lines = simulations

Lines = simulations 0

0

2

4

6

VGS [V]

10 16 extr. in [5] extr. in [14] Dit fitting for [6], unstrained Dit fitting for [6], strained Dit fitting for [5] Dit fitting [13]

-1

-2

Dit [eV cm ]

10 14

10 13

10 12

10 11

10 10

-0.6

-0.4

-0.2

0

2

4

6

VGS [V]

Fig. 3. Simulated (lines) and experimental (symbols) free carrier density versus gate voltage. The corresponding Dit profiles are reported in Fig. 4.

10 15

0

0

0.2

0.4

E-EC [eV] Fig. 4. Interface trap densities extracted by fitting the experimental N S ðV GS Þ data in Fig. 3. Circles and squares indicate the Dit extracted in [5] by comparing simulated CV and N S ðV GS Þ curves with experiments and in [13] via the conductance method, respectively. Solid lines are used for the range of energies actually explored by Hall measurements (i.e. the range of EF  Ec corresponding to the V GS range where Fermi level pinning is observed), dashed lines are extrapolations of solid lines following the functional form given by Eq. (2).

non-negligible consequences on the simulation results. As expected, higher N S saturation values, as observed for instance in strained samples, correspond to lower trap densities (triangles up in Fig. 4). We also see that the Dit which reproduces the data in [5] are lower than for the other cases; this may be related to the much thicker oxide used in [5] (16 nm of Al2 O3 ) with respect to the other works [6,12]. The Dit profiles diverge significantly from the distributions shown in [5,13]) when looking inside the band-gap. In fact, our extraction method based on the free carrier density above threshold is not so accurate in the gap region because those traps have a negligible effect on the Fermi level pinning. Therefore, Fig. 4 shows the Dit in the energy range actually covered by the experiments as solid lines, while the dashed lines are just an extrapolation that follows the functional form given by Eq. (2). However, a trap density as low as extracted in Fig. 4 is not completely unrealistic [14]. An additional remark applies to the data in [6]: a biaxial strain of 0.49% shifts down the conduction band by approximately

Fig. 5. Simulated N S of the devices from [6]. The dotted curve show the simulation of the strained device using the same Dit for the unstrained device, but with the conduction band shifted by 33 meV. The energy shift alone is not enough to reproduce the experiment (squares). Dashed line: beside the 33 meV conduction band shift, the shape of Dit is modified too.

33 meV, and it is assumed in [6] that the energy position of the Dit profile with respect to the vacuum level and the profile itself do not change with strain. Here we embrace the same assumption and furthermore we keep the same Dit used to fit the unstrained N S results (diamonds of Fig. 4). As can be seen in Fig. 5 the simulated N S comes very close to the measurements but an additional modification of the Dit profile has been necessary to better reproduce the experimental N S ðV GS Þ results. Fig. 6 compares N S to the (signed) trapped carrier density N it . Note that N it is positive throughout the whole V GS range. Fig. 7 shows the position of the Fermi level and the first two subbands versus the gate voltage. As V GS increases, the surface potential is pinned and N it becomes very large, and eventually overcomes N S . The most effective traps in pinning the potential are those with energy below the Fermi level but above the lowest subband energy E0 . These states are occupied but are also expected to respond very rapidly to the time dependent voltages at the device terminals and thus they may affect the CV curves even at high-frequency. If this is the case, the validity of techniques proposed to compensate the effect of interface states on the mobility is challenged [15,16] because they assume that interface traps will not respond to high frequency AC probe signal used for CV measurements.

4. Model description: Multi-Subband Monte Carlo To assess the impact of interface states on the mobility and on the drive current of short channel devices, ION , we used the MultiSubband Monte Carlo simulator described in [8]. The simulator operates by dividing the device in a number of sections along the transport direction x. The 1D Schrödinger equation is solved in each section to obtain the subband profile. Subband occupation along x is computed by solving the BTE with the Monte Carlo method [17]. In this way far-from-equilibrium transport and quantization normal to transport are accounted for. For mobility simulations, low field conditions are assumed. The potential energy profile in the quantization direction does not change much along the transport direction, so only one section is considered. The potential energy profile is obtained as described in Section 2 and is kept frozen through the simulation. The scattering rate parameters for both mobility and ION simulations are reported in [18] and have been calibrated on experimental

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10

14

10

14

13

10

12

10

11

-2

10

(b) Density [cm ]

-2

Density [cm ]

(a)

NS Nit

-1

0

1

2

3

4

5

6

10

13

10

12

10

11

NS Nit

-1

0

1

2

VGS [V]

3

4

5

6

VGS [V]

Fig. 6. Simulated N S compared to interface trap density N it . Plot (a) is obtained from the simulation of the device in [6] (unstrained case), while plot (b) is obtained from the simulation of the device in [5]. Both N S profiles are the same as in Fig. 3.

0.80

0.80

0.60

Energy [eV]

(b)

EF - EC E0 - EC E1 - EC EF - EC w/o traps

0.50

0.60

Energy [eV]

0.70

(a)

0.40 0.30 0.20

0.40

0.10 0.00 -1

EF - EC E0 - EC E1 - EC

0.20 EF - EC w/o traps

0

1

2

3

4

5

6

0.00

0

2

4

6

VGS [V]

VGS [V]

Fig. 7. Fermi level (EF ), first two subband (E0 and E1 ) referred to the conduction band edge (EC ). Plot (a) is obtained with the Dit profile that fits the N S ðV GS Þ from [6] (unstrained case), while plot (b) with the one that fits the N S ðV GS Þ from [5]. Dashed line shows the Fermi level with respect to the conduction band edge for a simulation without traps.

NS ðxÞ ¼

X Z i2subband

1

DosðEÞ  f ðE; EFeff ðxÞÞdE

ð5Þ

Ei

EFS=0

0.2 0.0 -0.2 -0.4

EFD=-qVDS

-0.6 -0.8 -1.0

EFeff EC E0

-1.2

Channel

-1.4 -40

-20

0

20

40

x [nm]

which means finding an effective Fermi energy such that the right hand side of Eq. (5) yields the same NS as the one computed by the Monte Carlo transport model. Once EFeff ðxÞ has been computed, N it is obtained as:

Z Em Nit ðxÞ ¼  Dit ðEÞ  ½1  f ðE; EFeff ðxÞÞdE Z1 1 Dit ðEÞ  f ðE; EFeff ðxÞÞdE þ

0.4

Energy [eV]

mobility data for In0:53 Ga0:47 As. The simulator uses the non-parabolic Effective Mass Approximation model for the In0:53 Ga0:47 As band structure, whose parameters are: mC ¼ 0:043m0 and aC ¼ 1:36 eV1 for the unstrained case, mC (transport plane) ¼ 0:0421m0 ; mC (quantization direction) ¼ 0:0384m0 and aC ¼ 1:4 eV1 for the strained case. For short device simulations, the effect of interface states poses an additional modelling challenge. In fact, equilibrium or near-equilibrium conditions were assumed so far, as can be seen from the use of f in Eq. (3). This model must be adapted for an out of equilibrium condition. For a sake of simplicity, we have used the same expression as in the previous analysis, but replacing the equilibrium Fermi level EF with an ‘‘effective’’ Fermi level EFeff . This effective Fermi level is computed by solving Eq. (5) for EFeff in each section:

ð6Þ

Em

Fig. 8 reports an example of effective Fermi level plotted along the channel. As expected, it changes smoothly from the source to the

Fig. 8. Effective Fermi level computed for the template device of Fig. 11, profile of the conduction band at the semiconductor/dielectric interface and the lowest subband along the transport direction. V DS ¼ 0:9 V; V GS ¼ 0:9 V.

drain equilibrium Fermi levels. The difference between EFeff and EC along the channel implies that, under our modelling assumptions, the concentration of occupied traps is higher near the source side of the channel. The figure also shows the profile of the lowest subband that is always well below the Fermi level. This means that most of the traps are exposed to a large concentration of free electrons with the same energy. Exchanges between traps and free

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electrons in this energy range are expected to be very fast and the energy distribution of the trapped electrons may deviate from an equilibrium distribution and get close to the distribution of the free electrons in the channel. 5. Results: Mobility

lHall ¼

In the following, we study the effects of the interface trapped charge on the Hall mobility, and on the effective mobility extracted from split-CV measurements. In particular, we focus on the data in [5] for an In0:53 Ga0:47 As MOSFET with a 16 nm Al2O3 gate dielectric. Besides the scattering mechanisms described in [18], we include here Coulomb scattering with charged centres of opposite signs due to traps in the high-k dielectric and corresponding to an equivalent interface density of centres N fix ¼ 9  1012 cm2. In addition we consider Coulomb scattering with the bias-dependent (see Fig. 6) charged interface states qN it (see the bias dependence of N it in Fig. 6). The model for Coulomb scattering is strictly valid only if the density of interface states is not too high, so that each Coulomb centre acts as an independent source of scattering [17]. However, at large density of Coulomb centres, the single trap scattering potentials overlap, resulting in a less severe mobility degradation [17] than predicted by the chosen model. Concerning N fix , this charge is a fitting parameter to obtain a better agreement with experiments and is not included in the solution of the Poisson equation based on the assumption that positive and negative centres essentially compensate each other. The same problem (i.e. need to introduce high density of Coulomb centres to match the experimental mobility) has been reported in previous simulation studies of MOSFETs featuring high-k dielectrics [19]. A detailed discussion of its formulation and implications for high-k dielectrics on top of silicon channels is reported in [20]. We believe that this additional charge is playing the role of neutral defects in the channel or at the interface that are not included in the model and requires us to mimic their effect by increasing the ionised impurity scattering. 5.1. Hall mobility The Hall mobility differs from the effective mobility even in the absence of interface states [7] but the exact calculation of lHall according to its definition [7] requires 3D simulations in real space whereas our MSMC is 2D in real space [8]. To overcome this difficulty, in this paper we denote as simulated Hall mobility the mobility computed assuming that N S is known. This assumption is not verified for the effective mobility measured with the split-CV technique in the samples examined, since the charge in the traps par-

3000

hv x i Fx

ð7Þ

Comparison between measured and simulated Hall mobility according to this definition is reported in Fig. 9a. As anticipated when discussing Fig. 6, due to the increased N it at large bias, we observe a limited mobility roll-off even without surface roughness scattering despite the counteracting effect of screening. When surface roughness mechanism is active instead, the main trends and the value of the experimental mobility are reproduced with reasonable accuracy. 5.2. Effective mobility As for the effective mobility, we adopt an empirical correction to mimic the limitations of the split-CV method in extracting hv x i from the ratio of the drain current per unit of width to the gate charge per unit of area. In particular, since for mobility extraction from split-CV measurements the charge is obtained by integration of the gate differential capacitance, which includes the contribution of the traps that can respond to the AC signal, we multiply the MSMC value of hv x i by the ratio between the free charge and the total charge N TOT . Thus, we evaluate

leff ¼

hv x i NS NS  ¼ lHall  F x NS þ Nit NS þ Nit

ð8Þ

where N it is the trap population that responds to high frequency AC signals in the CV measurements and hv x i is the same as in the Hall mobility calculations. Following a similar reasoning we transform the x-axis of the l  NS plot from N S to N TOT ¼ Nit þ NS . Nit is estimated as the fraction of traps with energy above the lowest subband energy but different physically reasonable choices yield essentially the same qualitative results [10]. Fig. 10 shows the ratio between N S and the total charge NS +Nit as obtained from our model and as extracted by comparing Hall and CV experiments in [5]. The mutual agreement is more than satisfactory. The comparison between measured [5] and simulated leff is then reported in Fig. 9b. The mutual agreements is essentially as good as for the Hall mobility. We notice a small roll-off at high N S even when both Coulomb scattering due to trapped charge and surface roughness scattering are off. This is an artefact due to the charge in the traps that in our model is assumed to respond to the CV. In the experiments

3000

µeff [cm \Vs]

(a)

(b)

2

2

µHall [cm \Vs]

tially responds to the AC signal; hence, it contributes to the capacitance, but negligibly to the current. Consistently with the discussion above, in the MSMC simulations we set a lateral field F x , we compute the average free carrier velocity hv x i and then derive:

1000 800

exp. [5] w/o surface roughness and Coulomb Scattering w/o surface roughness w/ surface roughness w/o surface roughness (ztrap= -0.5 nm) Solid lines = Simulations

600 400 12

1×10 -2

NS [cm ]

exp. [5] w/o surface roughness and Coulomb Scattering w/o surface roughness w/ surface roughness Hall Mobility w/correction

600 400

13

1×10

1000 800

Solid lines = Simulations 12

13

1×10

1×10 -2

NTOT [cm ]

Fig. 9. (a): Hall mobility lHall : comparison between the MSMC model and the experimental data in [5]. (b) Like (a) but for the effective mobility. The slanted triangles are the experimental mobility modified according to Eq. (8). The slanted squares in plot (a) refer to a simulation where the charge N it associated to the traps is moved 0.5 nm inside the dielectric, see text in Section 5.3.

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30 nm

24nm G

1.00

30 nm

HfO2 - 2nm

Interfacial layer - 0.95nm

D

SiO2 - 30nm 0.60

0.20 12 1×10

Fig. 11. Sketch of the simulated short channel device. The device is a single gate fully depleted SOI MOSFET. Channel is p-doped with a doping density of 2  1016 cm3 . Source and drain regions are n-doped with a doping density of 3  1019 cm3 . Interfacial layer is made of SiOn with r ¼ 7:0.

Simulations Exp. [5]

12

13

4×10

2×10 -2

NTOT [cm ] Fig. 10. Ratio between the free carriers density N S and the total carrier density (free plus trapped charge) as obtained with our model for the same device as in [5] (circles) and as extracted from the comparison between Hall and CV experiments in [5]. The Dit profile is the one indicated by left pointing triangles in Fig. 4.

this charge cannot be distinguished from free charge and this results in an underestimation of the mobility at high N S . It is also interesting to note that if the same correction used for the simulated Hall mobility is applied to the measured Hall mobility (slanted triangles in Fig. 9b), the resulting curve gets very close to the experimental effective mobility. The corresponding Hall coefficient r H ’ 1:05 is close to expectations. The analysis in Fig. 9b supports our view that the traps in the conduction band respond to the split-CV measures introducing an error in the experimental extraction of the effective mobility at high NS . 5.3. Interface versus border traps: effect of trap position So far, we have assumed that the trapped charge is placed at the interface between the semiconductor and the dielectric. However, border traps are present in the dielectric and may contribute to Fermi level pinning as well as respond to fast CV [21,22]. To check the impact of the trap position on the model results, we have considered a limiting case where the sheet of charge is at the position ztrap with respect to the semiconductor/dielectric interface (set at z ¼ 0). This displacement cannot be too large, otherwise traps do not respond to the high frequency CV experiments used for mobility measurements; we therefore tentatively set ztrap ¼ 0:5 nm, a reasonable value to represent the combination of a sheet of charge that is the combination of fast interface and border traps. Traps deeper into the dielectric are not considered here because they are not expected to affect the split-CV used in mobility measurements, although they are important when trying to reproduce CV experiments at different frequencies [23]. The effect of a charge displacement by ztrap on the electrostatics is modest. In fact, traps shift the V GS by qN it ðtox  jztrap jÞ=ox . This shift has an impact only for small t ox . For a 4 nm dielectric as in [6], a modest adjustment of the Dit profile with respect to the case ztrap ¼ 0 nm is sufficient to reproduce the experimental N S ðV GS Þ (not shown). This results in a slightly larger N it (about 10%) for given N S with respect to the case ztrap ¼ 0 nm. For a 16 nm dielectric as in [5], we found that the Dit profile and the resulting N S ðV GS Þ curve are essentially the same for ztrap ¼ 0 nm and ztrap ¼ 0:5 nm (not shown). Although the trap position has a modest influence the electrostatics, it affects the Coulomb-limited mobility. In Fig. 9 we show the mobility without surface roughness

when the trapped charge is located at ztrap ¼ 0:5 nm. The N it values are the same as in the case ztrap ¼ 0 nm. As one can see (compare filled and slanted squares), the mobility roll-off at high N S caused by the trapped charge is slightly smaller when traps are at 0.5 nm. Results at low N S are not affected by ztrap , because N it in this range is small and N fix is right at the interface (z ¼ 0 nm) in both cases.

6. Impact of traps on the I D of short devices In this Section we investigate the effect of trapped charges on the static drain current of a short channel device. The template structure used in the simulations is sketched in Fig. 11. Traps occupancy out of equilibrium has been modelled as described in Section 4. The carrier distribution in the semiconductor significantly deviates from the equilibrium Fermi–Dirac distribution. On the other hand one cannot simply replace the Fermi–Dirac distribution in Eq. (6) with the distribution function computed by the MSMC unless elastic trapping-detrapping processes are much more efficient than capture-emission processes among traps. Having in mind the limits of this analysis, Fig. 12 reports the drain current versus the gate voltage for the device in Fig. 11 at V DS ¼ 0:9 V. First, a trap distribution that pins the Fermi level at a free carrier density of about 6  1012 cm2 is considered (consistent with [6], squares of Fig. 3). Since the device is not exactly the same of Fig. 3, the trap distribution is slightly different from the one used to reproduce the data of [6] (squares of Fig. 4). The interface states

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Please cite this article in press as: Osgnach P et al. The impact of interface states on the mobility and drive current of In0:53 Ga0:47 As semiconductor n-MOSFETs. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2014.12.011

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The research leading to these results has received funding from the European Community’s Seventh Framework Programme (FP7/ 2007-2013) under grant agreement 619326-III-V-MOS Project.

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VGS [V] Fig. 13. Drain current versus gate voltage curves for the device in Fig. 11 using the trap profile from [13]. V DS ¼ 0:9 V. Gate workfunctions have been chosen so that the IOFF is 100 nA/lm for both simulations.

have a marginal effect on the current (compare squares in Fig. 12 to the result without traps). The reason for the small effect is that there are many interface states at high energy, but the gate voltage is not large enough to populate them. In fact, Fig. 8 shows that in the channel EFeff  EC is small and this difference decreases towards the drain region. Also, the impact of Coulomb scattering with trapped charge is limited since the ‘‘deflection’’ angles are small and have a small impact on back-scattering [24]. A more pessimistic trap profile that pins the Fermi level at a free carrier density of about 3  1012 cm2 produces a more significant saturation that limits the drain current to 1:7 mA=lm. Since the Dit profiles used in these simulations fall down to very low values inside the gap (as the ones in Fig. 4) the subthreshold slope is not affected by the traps. To investigate this point, we report in Fig. 13 the simulated IV characteristics of the same device in Fig. 11 using the trap distribution given by the squares of Fig. 4, consistent with the values from [13,5]. We see that the subthreshold slope is degraded from 73.3 mV/dec to 90.8 mV/dec as expected. 7. Conclusions Self-consistent solution of the Schrödinger and Poisson equations and accurate Multi-Subband Monte Carlo simulations were used to investigate the effect of interface states on the electrostatics, mobility and current drive of MOSFETs with In0:53 Ga0:47 As semiconductor channels. It has been found that very large concentrations of interface states are necessary to reproduce the strong Fermi level pinning found in the experiments. Most of these states have energy above the bottom of the conduction band, thus are expected to somehow respond to high frequency AC signals, thus limiting the accuracy of the split-CV method for the determination of the mobility, in particular at high free carrier densities. According to our model, which assumes trap occupancy in equilibrium with a local Fermi level, interface states are found to have a limited impact on the static current of short channel devices, mainly because the V GS is not high enough to reach the pinning condition: interface states at higher energies are not populated and thus the trapped charge is low. However, this latter aspect deserves a more detailed experimental and simulation analysis with the development of ad hoc models to handle far-from-equilibrium trap occupancy.

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Please cite this article in press as: Osgnach P et al. The impact of interface states on the mobility and drive current of In0:53 Ga0:47 As semiconductor n-MOSFETs. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2014.12.011