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Total solution in 157 nm lithography for below 65 nm node semiconductor devices
Microelectronic Engineering 73–74 (2004) 11–15 www.elsevier.com/locate/mee
Total solution in 157 nm lithography for below 65 nm node semiconductor devices Toshiro Itani *, Toshifumi Suganaga, Wataru Wakamiya Semiconductor Leading Edge Technologies, Inc. (Selete), 16-1 Onogawa, Tsukuba, Ibaraki, 305-8569, Japan Available online 9 March 2004
Abstract In order to apply 157 nm lithography for the mass production of below 65 nm-node semiconductor devices, several technology modules such as exposure tool, resist material, resist processing and resolution enhancement techniques were developed and integrated. The resolution limits were obtained as 45 nm lines and spaces with an attenuated phaseshifting mask (PSM) and 40 nm lines and spaces with an alternating PSM (Alt-PSM) using a high-numerical-aperture lens and high-transmittance fluorinated polymer resist. Furthermore, 60 nm poly-Si gate patterns were obtained using a hard mask process or a bi-layer process. Combining with the above-mentioned technologies, 65 nm SRAM gates were successfully fabricated. It was confirmed that 157 nm lithography might be reliable for realizing mass-production of below 65-nm node semiconductor devices. Ó 2004 Elsevier B.V. All rights reserved. Keywords: 157 nm lithography; F2 laser; Fluorinated polymer resist; Pattern transfer process; Phase-shifting mask
1. Introduction 157 nm lithography is the leading candidate for fabrication of below 65 nm-node semiconductor devices. In order to apply 157 nm lithography for the mass production of such devices, several technology modules such as exposure tool, resist material, resist processing and resolution enhancement techniques (RETs) need to be developed and integrated. Many efforts have been reported on each technology module [1–8]. In this * Corresponding author. Present address: NEC Electronics Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 2291198, Japan. E-mail address: [email protected] (T. Itani).
article, we describe the 157 nm lithography integration combining microstepper, fluorinated polymer resist, phase-shifting mask, optical proximity correction and pattern transfer process for both line pattern and contact hole formation. 2. Experimental and simulation The lithographic evaluations were carried out with the following procedure. The resist solutions were coated with a thickness of 90–150 nm onto silicon substrates directly or onto bottom anti-reflective coating (BARC) film on silicon substrates and prebaked at 110–120 °C for 60 s. The resist samples were exposed by F2 laser microstepper
0167-9317/$ - see front matter Ó 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2004.02.008
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T. Itani et al. / Microelectronic Engineering 73–74 (2004) 11–15
(Exitech Ltd.), having a 0.85 numerical aperture (NA) lens with a phase-shifting mask (PSM). After the exposure, post-exposure bakes were carried out at 110–120 °C for 60 s, and then they were developed in aqueous tetramethylammoniumhydroxide (TMAH) alkaline developer of 0.26 N for 30–60 s with a single puddle development process. The dry-etching was carried out using an Unity IIe etcher of Tokyo Electron Ltd., with CF4 /O2 based gas for hard mask process, and N2 /O2 based gas for bi-layer process. The optical simulations were obtained using PROLITH/3D produced by KLATencor Corp. The model simulation is based on the high-NA scalar approximation, which can be derived directly from MaxwellÕs equations.
Fig. 1. Chemical structure of the fluorinated polymer resist and its resolution limit.
The exposure tool platform for the high NA lens was a 157 nm microstepper designed and manufactured by Exitech Ltd., UK. The light source for the system is a Lambda Physik Novaline F1030 F2 laser that emits more than 10 W into both F2 lines at 1000 Hz repetition rate. The projection lens is a 0.85 NA catadioptric objective (manufactured by Corning Tropel Corp.), chromatically corrected over the full emission spectrum of the F2 laser. The details have been reported in the literature [1].
hard mask process for L/S pattern and bi-layer resist process for both L/S pattern and contact hole (C/H) pattern [4,5]. Fig. 2 shows hard mask process for gate formation using the fluorinated polymer resist. BARC/SiN etching, resist/BARC ashing and poly-Si etching were successfully performed and then 60 nm 1:1 gate pattern was obtained. Fig. 3 shows bi-layer resist process for gate formation using fluorine containing silsesquioxane polymer resist. Organic film etching, WSi/poly-Si etching and resist ashing were successfully performed and then 60 nm 1:1 gate pattern was obtained. Fig. 4 shows bi-layer resist process for C/H formation using fluorine containing silsesquioxane polymer resist. Organic film etching, TEOS etching and resist ashing were successfully performed and then 85 nm isolated hole was fabricated. Dense hole pattern will be formed in the near future.
3.2. Resist material and processing
3.3. Resolution enhancement techniques
Fig. 1 shows the chemical structure of the monocyclic fluorinated polymer contained aliphatic monocyclic rings (1,1,2,3,3,-Pentafluoro, 4trifluoromethyl-4-hydroxy-1, 6-heptadiene) with a blocking group of cyclohexylcyclohexyloxymethyl (CCOM), and a SEM image of its resolution limit. This polymer was developed by Asahi Glass Co., Ltd. and us [2,3]. The absorption coefficient was 0.64 lm 1 at 157 nm exposure wavelength, and the dry-etching rate was 1.75 times to that of the KrF resist. The resolution limit of 55 nm 1:1 lines and spaces (L/S) pattern was obtained at 150 nm resist thickness using alternating-PSM (Alt-PSM). As for pattern transfer processes, we have evaluated
As for RET, attenuated phase-shifting mask (Att-PSM) was evaluated because of its superior compatibility with actual circuit design and exposure process for the mass production [6,7]. Fig. 5 shows mask structure and resolution limit of AttPSM for 1:2 L/S pattern. The bi-layer film of TaSiO/Ta was used for attenuated phase-shifting film with the transmittance of 5%. The resolution limit of 45 nm 1:2 L/S pattern was obtained. Fig. 6 shows mask structure and simulated resist profile and experimental resist profile of chrome-shielding type Att-PSM, comparing with no-shielding type Att-PSM for C/H formation. Chrome-shielding film was arranged around the C/H pattern to
3. Results and discussion 3.1. Exposure tool
T. Itani et al. / Microelectronic Engineering 73–74 (2004) 11–15
Fig. 2. Hard mask process for gate formation using the fluorinated polymer resist.
Fig. 3. Bi-layer resist process for gate formation using fluorine containing silsesquioxane polymer resist.
Fig. 4. Bi-layer resist process for hole formation using fluorine containing silsesquioxane polymer resist.
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Fig. 5. Mask structure and resolution limit of Att-PSM for 1:2 L/S pattern.
prevent the side-lobe formation. Based on the results of both simulated and experimental resist profiles, the side-lobe formation was prevented using chrome-shielding type Att-PSM, and the resolution limit of 70 nm level isolated hole was obtained. The lithographic margin such as exposure and focus margin will be evaluated in the near future. As for strong RET Alt-PSM was evaluated, because of its superior resolution improvement capability. Fig. 7 shows mask structure and resolution limit of Alt-PSM for 1:2 L/S pattern. The mask structure is side-wall chrome alternating aperture mask (SCAAM) [8]. The resolution limit of 40 nm 1:2 L/S pattern was obtained. As another RET, optical proximity correction (OPC) was evaluated for the device gate pattern [9]. Fig. 8 shows mask design and experimental resist profile for 65 nm SRAM gate; (a) without OPC and (b) with OPC. The resist pattern shape was drastically improved by OPC, and the resist pattern of 65 nm SRAM gate was successfully obtained. 3.4. Device fabrication
Fig. 6. Chrome-shielding type Att-PSM for C/H formation.
Combining the above-mentioned technology modules, 65 nm SRAM gate was fabricated. Fig. 9 shows SEM image of pattern transfer using bilayer resist process for 65 nm SRAM gate. After organic film/poly-Si etching and resist ashing, 65 nm SRAM gate was successfully fabricated. Fig. 10 shows focus margin of resist pattern of the 65 nm SRAM gate. The focus margin was ob-
Fig. 7. Mask structure and resolution limit of Alt-PSM for 1:2 L/S pattern.
T. Itani et al. / Microelectronic Engineering 73–74 (2004) 11–15
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4. Conclusion The individual technology modules of 157 nm lithography, such as exposure tool, resist material, resist processing and RETs were developed and integrated. As a result, 65 nm SRAM gate was successfully fabricated. It was confirmed that these technology were feasible for actual semiconductor device fabrication. We confirmed that 157 nm lithography might be reliable for realizing massproduction of below 65 nm node semiconductor devices.
Fig. 8. Mask design and experimental resist profile for 65 nm SRAM gate: (a) without OPC; (b) with OPC.
Acknowledgements The authors thank the whole F2 lithography group at Selete and our member companies of Selete for their cooperation. The authors also thank to Dr. N. Endo for helpful suggestions and encouragement.
References
Fig. 9. Pattern transfer using bi-layer resist process for 65 nm SRAM gate.
Fig. 10. Focus margin of resist pattern of the 65 nm SRAM gate.
tained as only 50 nm because of relatively large lens aberration of 80 nm RMS value [10]. However, future production exposure tool should have lower aberration lens, the focus margin as well as exposure margin should be improved to satisfy the requirements for the mass-production of actual semiconductor devices.
[1] T. Itani, W. Wakamiya, J. Cashmore, M. Gower, Microelectron. Eng. 67–68 (2003) 39. [2] S. Irie, S. Ishikawa, T. Hagiwara, T. Yamazaki, T. Furukawa, T. Itani, Y. Kawaguchi, S. Kodama, O. Yokokoji, I. Kaneko, Y. Takebe, S. Okada, Jpn. J. Appl. Phys. 42 (2003) 3743. [3] S. Ishikawa, S. Irie, T. Itani, Y. Kawaguchi, O. Yokokoji, S. Kodama, Proc. SPIE 5039 (2003) 580. [4] S. Miyoshi, T. Furukawa, H. Watanabe, S. Irie, T. Itani, Digest of Technical Papers, Symposium on VLSI Technology 2002, pp. 198. [5] S. Miyoshi, T. Furukawa, E. Kawaguchi, T. Itani, Proc. SPIE 5039 (2003) 462. [6] K. Watanabe, O. Yamabe, N. Kanda, J.-H. Kim, N. Uchida, S. Irie, T. Suganaga, T. Itani, Proc. SPIE 4754 (2002) 444. [7] K. Watanabe, E. Kurose, T. Suganaga, T. Itani, Proc. SPIE 5130 (2003) 736. [8] Y. Morikawa, H. Kokubo, K. Noguchi, S. Sasaki, H. Mohri, M. Hoga, N. Kanda, S. Irie, K. Watanabe, T. Suganaga, T. Itani, Proc. SPIE 5040 (2003) 1137. [9] T. Suganaga, S. Irie, S. Miyoshi, J.-H. Kim, K. Watanabe, E. Kurose, T. Furukawa, T. Hagiwara, T. Ishimaru, T. Itani, Proc. SPIE 5040 (2003) 261. [10] J-H. Kim, T. Suganaga, K. Watanabe, N. Kanda, T. Itani, J. Cashmore, M. Gower, Proc. SPIE 5040 (2003) 1408.
Total solution in 157 nm lithography for below 65 nm node semiconductor devices Toshiro Itani *, Toshifumi Suganaga, Wataru Wakamiya Semiconductor Leading Edge Technologies, Inc. (Selete), 16-1 Onogawa, Tsukuba, Ibaraki, 305-8569, Japan Available online 9 March 2004
Abstract In order to apply 157 nm lithography for the mass production of below 65 nm-node semiconductor devices, several technology modules such as exposure tool, resist material, resist processing and resolution enhancement techniques were developed and integrated. The resolution limits were obtained as 45 nm lines and spaces with an attenuated phaseshifting mask (PSM) and 40 nm lines and spaces with an alternating PSM (Alt-PSM) using a high-numerical-aperture lens and high-transmittance fluorinated polymer resist. Furthermore, 60 nm poly-Si gate patterns were obtained using a hard mask process or a bi-layer process. Combining with the above-mentioned technologies, 65 nm SRAM gates were successfully fabricated. It was confirmed that 157 nm lithography might be reliable for realizing mass-production of below 65-nm node semiconductor devices. Ó 2004 Elsevier B.V. All rights reserved. Keywords: 157 nm lithography; F2 laser; Fluorinated polymer resist; Pattern transfer process; Phase-shifting mask
1. Introduction 157 nm lithography is the leading candidate for fabrication of below 65 nm-node semiconductor devices. In order to apply 157 nm lithography for the mass production of such devices, several technology modules such as exposure tool, resist material, resist processing and resolution enhancement techniques (RETs) need to be developed and integrated. Many efforts have been reported on each technology module [1–8]. In this * Corresponding author. Present address: NEC Electronics Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 2291198, Japan. E-mail address: [email protected] (T. Itani).
article, we describe the 157 nm lithography integration combining microstepper, fluorinated polymer resist, phase-shifting mask, optical proximity correction and pattern transfer process for both line pattern and contact hole formation. 2. Experimental and simulation The lithographic evaluations were carried out with the following procedure. The resist solutions were coated with a thickness of 90–150 nm onto silicon substrates directly or onto bottom anti-reflective coating (BARC) film on silicon substrates and prebaked at 110–120 °C for 60 s. The resist samples were exposed by F2 laser microstepper
0167-9317/$ - see front matter Ó 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2004.02.008
12
T. Itani et al. / Microelectronic Engineering 73–74 (2004) 11–15
(Exitech Ltd.), having a 0.85 numerical aperture (NA) lens with a phase-shifting mask (PSM). After the exposure, post-exposure bakes were carried out at 110–120 °C for 60 s, and then they were developed in aqueous tetramethylammoniumhydroxide (TMAH) alkaline developer of 0.26 N for 30–60 s with a single puddle development process. The dry-etching was carried out using an Unity IIe etcher of Tokyo Electron Ltd., with CF4 /O2 based gas for hard mask process, and N2 /O2 based gas for bi-layer process. The optical simulations were obtained using PROLITH/3D produced by KLATencor Corp. The model simulation is based on the high-NA scalar approximation, which can be derived directly from MaxwellÕs equations.
Fig. 1. Chemical structure of the fluorinated polymer resist and its resolution limit.
The exposure tool platform for the high NA lens was a 157 nm microstepper designed and manufactured by Exitech Ltd., UK. The light source for the system is a Lambda Physik Novaline F1030 F2 laser that emits more than 10 W into both F2 lines at 1000 Hz repetition rate. The projection lens is a 0.85 NA catadioptric objective (manufactured by Corning Tropel Corp.), chromatically corrected over the full emission spectrum of the F2 laser. The details have been reported in the literature [1].
hard mask process for L/S pattern and bi-layer resist process for both L/S pattern and contact hole (C/H) pattern [4,5]. Fig. 2 shows hard mask process for gate formation using the fluorinated polymer resist. BARC/SiN etching, resist/BARC ashing and poly-Si etching were successfully performed and then 60 nm 1:1 gate pattern was obtained. Fig. 3 shows bi-layer resist process for gate formation using fluorine containing silsesquioxane polymer resist. Organic film etching, WSi/poly-Si etching and resist ashing were successfully performed and then 60 nm 1:1 gate pattern was obtained. Fig. 4 shows bi-layer resist process for C/H formation using fluorine containing silsesquioxane polymer resist. Organic film etching, TEOS etching and resist ashing were successfully performed and then 85 nm isolated hole was fabricated. Dense hole pattern will be formed in the near future.
3.2. Resist material and processing
3.3. Resolution enhancement techniques
Fig. 1 shows the chemical structure of the monocyclic fluorinated polymer contained aliphatic monocyclic rings (1,1,2,3,3,-Pentafluoro, 4trifluoromethyl-4-hydroxy-1, 6-heptadiene) with a blocking group of cyclohexylcyclohexyloxymethyl (CCOM), and a SEM image of its resolution limit. This polymer was developed by Asahi Glass Co., Ltd. and us [2,3]. The absorption coefficient was 0.64 lm 1 at 157 nm exposure wavelength, and the dry-etching rate was 1.75 times to that of the KrF resist. The resolution limit of 55 nm 1:1 lines and spaces (L/S) pattern was obtained at 150 nm resist thickness using alternating-PSM (Alt-PSM). As for pattern transfer processes, we have evaluated
As for RET, attenuated phase-shifting mask (Att-PSM) was evaluated because of its superior compatibility with actual circuit design and exposure process for the mass production [6,7]. Fig. 5 shows mask structure and resolution limit of AttPSM for 1:2 L/S pattern. The bi-layer film of TaSiO/Ta was used for attenuated phase-shifting film with the transmittance of 5%. The resolution limit of 45 nm 1:2 L/S pattern was obtained. Fig. 6 shows mask structure and simulated resist profile and experimental resist profile of chrome-shielding type Att-PSM, comparing with no-shielding type Att-PSM for C/H formation. Chrome-shielding film was arranged around the C/H pattern to
3. Results and discussion 3.1. Exposure tool
T. Itani et al. / Microelectronic Engineering 73–74 (2004) 11–15
Fig. 2. Hard mask process for gate formation using the fluorinated polymer resist.
Fig. 3. Bi-layer resist process for gate formation using fluorine containing silsesquioxane polymer resist.
Fig. 4. Bi-layer resist process for hole formation using fluorine containing silsesquioxane polymer resist.
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T. Itani et al. / Microelectronic Engineering 73–74 (2004) 11–15
Fig. 5. Mask structure and resolution limit of Att-PSM for 1:2 L/S pattern.
prevent the side-lobe formation. Based on the results of both simulated and experimental resist profiles, the side-lobe formation was prevented using chrome-shielding type Att-PSM, and the resolution limit of 70 nm level isolated hole was obtained. The lithographic margin such as exposure and focus margin will be evaluated in the near future. As for strong RET Alt-PSM was evaluated, because of its superior resolution improvement capability. Fig. 7 shows mask structure and resolution limit of Alt-PSM for 1:2 L/S pattern. The mask structure is side-wall chrome alternating aperture mask (SCAAM) [8]. The resolution limit of 40 nm 1:2 L/S pattern was obtained. As another RET, optical proximity correction (OPC) was evaluated for the device gate pattern [9]. Fig. 8 shows mask design and experimental resist profile for 65 nm SRAM gate; (a) without OPC and (b) with OPC. The resist pattern shape was drastically improved by OPC, and the resist pattern of 65 nm SRAM gate was successfully obtained. 3.4. Device fabrication
Fig. 6. Chrome-shielding type Att-PSM for C/H formation.
Combining the above-mentioned technology modules, 65 nm SRAM gate was fabricated. Fig. 9 shows SEM image of pattern transfer using bilayer resist process for 65 nm SRAM gate. After organic film/poly-Si etching and resist ashing, 65 nm SRAM gate was successfully fabricated. Fig. 10 shows focus margin of resist pattern of the 65 nm SRAM gate. The focus margin was ob-
Fig. 7. Mask structure and resolution limit of Alt-PSM for 1:2 L/S pattern.
T. Itani et al. / Microelectronic Engineering 73–74 (2004) 11–15
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4. Conclusion The individual technology modules of 157 nm lithography, such as exposure tool, resist material, resist processing and RETs were developed and integrated. As a result, 65 nm SRAM gate was successfully fabricated. It was confirmed that these technology were feasible for actual semiconductor device fabrication. We confirmed that 157 nm lithography might be reliable for realizing massproduction of below 65 nm node semiconductor devices.
Fig. 8. Mask design and experimental resist profile for 65 nm SRAM gate: (a) without OPC; (b) with OPC.
Acknowledgements The authors thank the whole F2 lithography group at Selete and our member companies of Selete for their cooperation. The authors also thank to Dr. N. Endo for helpful suggestions and encouragement.
References
Fig. 9. Pattern transfer using bi-layer resist process for 65 nm SRAM gate.
Fig. 10. Focus margin of resist pattern of the 65 nm SRAM gate.
tained as only 50 nm because of relatively large lens aberration of 80 nm RMS value [10]. However, future production exposure tool should have lower aberration lens, the focus margin as well as exposure margin should be improved to satisfy the requirements for the mass-production of actual semiconductor devices.
[1] T. Itani, W. Wakamiya, J. Cashmore, M. Gower, Microelectron. Eng. 67–68 (2003) 39. [2] S. Irie, S. Ishikawa, T. Hagiwara, T. Yamazaki, T. Furukawa, T. Itani, Y. Kawaguchi, S. Kodama, O. Yokokoji, I. Kaneko, Y. Takebe, S. Okada, Jpn. J. Appl. Phys. 42 (2003) 3743. [3] S. Ishikawa, S. Irie, T. Itani, Y. Kawaguchi, O. Yokokoji, S. Kodama, Proc. SPIE 5039 (2003) 580. [4] S. Miyoshi, T. Furukawa, H. Watanabe, S. Irie, T. Itani, Digest of Technical Papers, Symposium on VLSI Technology 2002, pp. 198. [5] S. Miyoshi, T. Furukawa, E. Kawaguchi, T. Itani, Proc. SPIE 5039 (2003) 462. [6] K. Watanabe, O. Yamabe, N. Kanda, J.-H. Kim, N. Uchida, S. Irie, T. Suganaga, T. Itani, Proc. SPIE 4754 (2002) 444. [7] K. Watanabe, E. Kurose, T. Suganaga, T. Itani, Proc. SPIE 5130 (2003) 736. [8] Y. Morikawa, H. Kokubo, K. Noguchi, S. Sasaki, H. Mohri, M. Hoga, N. Kanda, S. Irie, K. Watanabe, T. Suganaga, T. Itani, Proc. SPIE 5040 (2003) 1137. [9] T. Suganaga, S. Irie, S. Miyoshi, J.-H. Kim, K. Watanabe, E. Kurose, T. Furukawa, T. Hagiwara, T. Ishimaru, T. Itani, Proc. SPIE 5040 (2003) 261. [10] J-H. Kim, T. Suganaga, K. Watanabe, N. Kanda, T. Itani, J. Cashmore, M. Gower, Proc. SPIE 5040 (2003) 1408.