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Towards a benchmark for symbolic layout and compaction
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Integration
News
Towards a benchmark for symbolic layout and compaction A remarkable initiative has been taken at the MCNC. All those attending the International Workshop on Symbolic Layout and Compaction are encouraged to parcipate in an open forum to discuss the results of applying their respective tools to (proposed) benchmarks. These benchmarks have been designed to fairly yet critically test the wide spectrum of symbolic design and compaction tools. This is an opportunity for you to discuss new ideas you may be exploring. The MOSIS CMOS and NMOS scalable design rules (lambda= 1.5 micron) will be the common design rules used for benchmarking. Although the MOSIS rules are not as aggressive as is generally available to industry, these rules are in the public domain, and will provide for an accurate one-to-one comparison of various techniques. For each of the different benchmarks a sticks diagram is provided, and if applicable a SPICE-like netlist is provided. This information will be distributed both in the form of hard copy and electronically (for the SPICE netlists). Such information will be contained in the next issue of INTEGRATION but can also be ob tamed from William T. Krakow Microelectronics Center of North Carolina Research Triangle Park, NC 27709 (USA) Phone: (919) 248-1959 Email: krakow@mcnc The design examples comprise - standard cell components, such as an and-or-invert gate, a master-slave dynamic d-type flipflop and a multiwire routing channel, - custom components, such as a six-transistor static RAM bit and a conventional full-adder, - hierarchical units, such as twelve cells & a routing channel, a three by three SRAM array and an eight-bit adder. Participants in the benchmarking exercise should indicate any manual intervention required to enhance the resulting design. This includes manual insertion of jogs, or alterations to the layout to achieve adherence to design constraints such as fixed standard cell heights.
Integration
News
Towards a benchmark for symbolic layout and compaction A remarkable initiative has been taken at the MCNC. All those attending the International Workshop on Symbolic Layout and Compaction are encouraged to parcipate in an open forum to discuss the results of applying their respective tools to (proposed) benchmarks. These benchmarks have been designed to fairly yet critically test the wide spectrum of symbolic design and compaction tools. This is an opportunity for you to discuss new ideas you may be exploring. The MOSIS CMOS and NMOS scalable design rules (lambda= 1.5 micron) will be the common design rules used for benchmarking. Although the MOSIS rules are not as aggressive as is generally available to industry, these rules are in the public domain, and will provide for an accurate one-to-one comparison of various techniques. For each of the different benchmarks a sticks diagram is provided, and if applicable a SPICE-like netlist is provided. This information will be distributed both in the form of hard copy and electronically (for the SPICE netlists). Such information will be contained in the next issue of INTEGRATION but can also be ob tamed from William T. Krakow Microelectronics Center of North Carolina Research Triangle Park, NC 27709 (USA) Phone: (919) 248-1959 Email: krakow@mcnc The design examples comprise - standard cell components, such as an and-or-invert gate, a master-slave dynamic d-type flipflop and a multiwire routing channel, - custom components, such as a six-transistor static RAM bit and a conventional full-adder, - hierarchical units, such as twelve cells & a routing channel, a three by three SRAM array and an eight-bit adder. Participants in the benchmarking exercise should indicate any manual intervention required to enhance the resulting design. This includes manual insertion of jogs, or alterations to the layout to achieve adherence to design constraints such as fixed standard cell heights.